From d2782ff43c6f0dec28a391c94ce6d9f986a295bb Mon Sep 17 00:00:00 2001 From: Shepard Siegel Date: Mon, 27 Jan 2014 12:03:45 -0500 Subject: [PATCH 1/3] Increase BLUART RX FIFO from 2 chars to 8 chars --- bsv/dev/BLUART.bsv | 57 +- bsv/inf/OCCP.bsv | 2 +- bsv/utl/CompileTime.bsv | 2 +- logs/ml605-20140126_1604/fpgaTop-ml605.srp | 13926 ++++++++++++++++++ logs/ml605-20140126_1604/fpgaTop.bld | 5797 ++++++++ logs/ml605-20140126_1604/fpgaTop.par | 1217 ++ logs/ml605-20140126_1604/fpgaTop.twr | 10712 ++++++++++++++ logs/ml605-20140126_1604/fpgaTop_map.mrp | 8344 +++++++++++ logs/ml605-20140127_1142/fpgaTop-ml605.srp | 13979 +++++++++++++++++++ logs/ml605-20140127_1142/fpgaTop.bld | 5797 ++++++++ logs/ml605-20140127_1142/fpgaTop.par | 1219 ++ logs/ml605-20140127_1142/fpgaTop.twr | 10752 ++++++++++++++ logs/ml605-20140127_1142/fpgaTop_map.mrp | 8368 +++++++++++ rtl/mkBLUART.v | 130 +- rtl/mkBiasWorker16B.v | 2 +- rtl/mkBiasWorker32B.v | 2 +- rtl/mkBiasWorker4B.v | 2 +- rtl/mkBiasWorker8B.v | 2 +- rtl/mkCTop16B.v | 2 +- rtl/mkDramServer_v6.v | 2 +- rtl/mkFMC150.v | 2 +- rtl/mkFTop_ml605.v | 14 +- rtl/mkFlashController2416.v | 2 +- rtl/mkFlashWorker.v | 2 +- rtl/mkGMAC.v | 2 +- rtl/mkGbeWorker.v | 2 +- rtl/mkICAPWorker.v | 2 +- rtl/mkMemiTestWorker.v | 2 +- rtl/mkOCApp16B.v | 2 +- rtl/mkOCCP.v | 386 +- rtl/mkOCDP16B.v | 35 +- rtl/mkOCInf16B.v | 42 +- rtl/mkPktFork.v | 2 +- rtl/mkPktMerge.v | 2 +- rtl/mkQABSMF.v | 2 +- rtl/mkQABSMF3.v | 2 +- rtl/mkSMAdapter16B.v | 2 +- rtl/mkSMAdapter32B.v | 2 +- rtl/mkSMAdapter4B.v | 2 +- rtl/mkSMAdapter8B.v | 2 +- rtl/mkTLPCM.v | 2 +- rtl/mkTLPClientNode.v | 2 +- rtl/mkTLPSM.v | 2 +- rtl/mkTLPSerializer.v | 2 +- rtl/mkTLPServerNode.v | 2 +- rtl/mkTimeClient.v | 2 +- rtl/mkUUID.v | 2 +- rtl/mkWSICaptureWorker4B.v | 2 +- rtl/mkWciInitiator.v | 2 +- rtl/mkWciMonitor.v | 2 +- rtl/mkWciTarget.v | 2 +- rtl/mkWsiAdapter16B4B.v | 2 +- rtl/mkWsiAdapter32B4B.v | 2 +- rtl/mkWsiAdapter4B16B.v | 2 +- rtl/mkWsiAdapter4B32B.v | 2 +- 55 files changed, 80461 insertions(+), 392 deletions(-) create mode 100644 logs/ml605-20140126_1604/fpgaTop-ml605.srp create mode 100644 logs/ml605-20140126_1604/fpgaTop.bld create mode 100644 logs/ml605-20140126_1604/fpgaTop.par create mode 100644 logs/ml605-20140126_1604/fpgaTop.twr create mode 100644 logs/ml605-20140126_1604/fpgaTop_map.mrp create mode 100644 logs/ml605-20140127_1142/fpgaTop-ml605.srp create mode 100644 logs/ml605-20140127_1142/fpgaTop.bld create mode 100644 logs/ml605-20140127_1142/fpgaTop.par create mode 100644 logs/ml605-20140127_1142/fpgaTop.twr create mode 100644 logs/ml605-20140127_1142/fpgaTop_map.mrp diff --git a/bsv/dev/BLUART.bsv b/bsv/dev/BLUART.bsv index 9030ca00..1ce3a209 100644 --- a/bsv/dev/BLUART.bsv +++ b/bsv/dev/BLUART.bsv @@ -1,5 +1,8 @@ // BLUART.bsv - A Bluespec SystemVerilog (BSV) UART // Copyright (c) 2014 Atomic Rules LLC - ALL RIGHTS RESERVED +// +// Default Configuration: 115200 baud, 8 bits, 1 stop bit, no parity +// Baud rate may be set at runtime by the setClkDiv method package BLUART; @@ -20,12 +23,12 @@ interface UART_pads; endinterface: UART_pads interface BLUARTIfc; - interface Put#(UInt#(16)) setClkDiv; // clkDiv = module clock / desired baudrate - method UInt#(16) txLevel; - method UInt#(16) rxLevel; - interface Put#(Bit#(8)) txChar; - interface Get#(Bit#(8)) rxChar; - interface UART_pads pads; + interface Put#(UInt#(16)) setClkDiv; // clkDiv = module clock freq / desired baudrate + method UInt#(8) txLevel; // 0=Nothing to send; 1=Sending TX data + method UInt#(8) rxLevel; // 0=Nothing to receive; 1=One or more Bytes in rxF + interface Put#(Bit#(8)) txChar; // Method to Put() TX data + interface Get#(Bit#(8)) rxChar; // Method to Get() RX data + interface UART_pads pads; // Interface to UART pads endinterface @@ -40,7 +43,7 @@ module mkBLUART (BLUARTIfc); Reg#(UInt#(16)) rxBaudCnt <- mkReg(0); Reg#(UInt#(4)) rxBitCnt <- mkReg(0); - FIFOF#(Bit#(8)) rxF <- mkFIFOF; + FIFOF#(Bit#(8)) rxF <- mkSizedFIFOF(4); Reg#(Bit#(1)) rxInReg <- mkReg(1); Reg#(Bit#(1)) rxCtsReg <- mkReg(1); Reg#(Vector#(2,Bit#(1))) rxD <- mkReg(unpack('1)); @@ -59,18 +62,8 @@ module mkBLUART (BLUARTIfc); endrule rule tx_DataMux; - case (txBitCnt) - 0 : txData <= 1; - 1 : txData <= 0; // 1 stop bit - 2 : txData <= txF.first[0]; - 3 : txData <= txF.first[1]; - 4 : txData <= txF.first[2]; - 5 : txData <= txF.first[3]; - 6 : txData <= txF.first[4]; - 7 : txData <= txF.first[5]; - 8 : txData <= txF.first[6]; - 9 : txData <= txF.first[7]; - endcase + Bit#(10) txa = {txF.first, 2'b01}; // 1 stop bit, then data + txData <= txa[txBitCnt]; // LS first, parallel to serial endrule // Rx Logic... @@ -83,13 +76,13 @@ module mkBLUART (BLUARTIfc); (* fire_when_enabled, no_implicit_conditions *) rule update_rxCnts; rxD <= shiftInAt0(rxD, rxInReg); - if (rxGo) rxBaudCnt <= 1; // Start baud counter on new bit falling edge - else if (rxStop) rxBaudCnt <= 0; // Clear when done - else if (rxBaudCnt>=clkDiv) rxBaudCnt <= 1; // Hold at clkDic + if (rxGo) rxBaudCnt <= 1; // Start baud counter + else if (rxStop) rxBaudCnt <= 0; // Clear when done + else if (rxBaudCnt>=clkDiv) rxBaudCnt <= 1; // Hold at clkDiv else if (rxBaudCnt!=0) rxBaudCnt <= rxBaudCnt + 1; // Inc rxBaudCnt - if (rxGo) rxBitCnt <= 1; - else if (rxStop) rxBitCnt <= 0; - else if (rxBaudCnt==clkDiv) rxBitCnt <= rxBitCnt + 1; + if (rxGo) rxBitCnt <= 1; // Start bit counter + else if (rxStop) rxBitCnt <= 0; // Stop bit counter + else if (rxBaudCnt==clkDiv) rxBitCnt <= rxBitCnt + 1; // Inc rxBitCnt endrule rule rx_d_shift (rxShift); @@ -100,14 +93,14 @@ module mkBLUART (BLUARTIfc); rxF.enq(pack(rxV)); endrule - method UInt#(16) txLevel = (txF.notEmpty) ? 1 : 0; - method UInt#(16) rxLevel = (rxF.notEmpty) ? 1 : 0; - interface Put txChar = toPut(txF); - interface Put setClkDiv = toPut(asReg(clkDiv)); - interface Get rxChar = toGet(rxF); + interface Put txChar = toPut(txF); + interface Get rxChar = toGet(rxF); + interface Put setClkDiv = toPut(asReg(clkDiv)); + method UInt#(8) txLevel = (txF.notEmpty) ? 1 : 0; + method UInt#(8) rxLevel = (rxF.notEmpty) ? 1 : 0; interface UART_pads pads; - method Bool rts = True; // connect to CTS - method Bool tx = unpack(txData); // connect to RX + method Bool rts = True; // connect to CTS + method Bool tx = unpack(txData); // connect to RX method Action cts (Bool arg) = rxCtsReg._write(pack(arg)); // connect to RTS method Action rx (Bool arg) = rxInReg._write(pack(arg)); // connect to TX endinterface diff --git a/bsv/inf/OCCP.bsv b/bsv/inf/OCCP.bsv index bcdfbe25..8a723c18 100644 --- a/bsv/inf/OCCP.bsv +++ b/bsv/inf/OCCP.bsv @@ -134,7 +134,7 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) endfunction rule init_uart_text (!uartInited); - Vector#(40,Bit#(8)) initText = uartLine("OpenCPI USB-UART v0.01 2014-01-26 *good*"); + Vector#(40,Bit#(8)) initText = uartLine("OpenCPI USB-UART v0.01 2014-01-24 *safe*"); case (uartTxtP) 0,42 : bluart.txChar.put(8'h0d); // CR 1,43 : bluart.txChar.put(8'h0a); // LF diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv index 1700532d..301b6e16 100644 --- a/bsv/utl/CompileTime.bsv +++ b/bsv/utl/CompileTime.bsv @@ -1 +1 @@ -Bit#(32) compileTime = 1390768038; // Verilog Sun Jan 26 15:27:18 EST 2014 +Bit#(32) compileTime = 1390838362; // Verilog Mon Jan 27 10:59:22 EST 2014 diff --git a/logs/ml605-20140126_1604/fpgaTop-ml605.srp b/logs/ml605-20140126_1604/fpgaTop-ml605.srp new file mode 100644 index 00000000..71b6ca1d --- /dev/null +++ b/logs/ml605-20140126_1604/fpgaTop-ml605.srp @@ -0,0 +1,13926 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter xsthdpini set to ocpihdp_v6.ini + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-ml605.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc6vlx240t-ff1156-1 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +LUT Combining : off +Reduce Control Sets : off +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Power Reduction : NO +Library Search Order : fpgaTop.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +---- Other Options +change_error_to_warning : "HDLCompiler:532 HDLCompiler:597" + +========================================================================= + +INFO:Xst - Changing 'HDLCompiler:532' to warning +INFO:Xst - Changing 'HDLCompiler:597' to warning + +========================================================================= +* HDL Parsing * +========================================================================= +The vhdl library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +The veri library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFO.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/Ethernet_v6_v1_5.v" into library work +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" Line 85. parameter declaration becomes local in pcie_upconfig_fix_3451_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" Line 76. parameter declaration becomes local in pcie_reset_delay_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" Line 120. parameter declaration becomes local in pcie_brams_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" Line 216. parameter declaration becomes local in pcie_gtx_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 325. parameter declaration becomes local in pcie_pipe_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" Line 103. parameter declaration becomes local in pcie_pipe_lane_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" Line 90. parameter declaration becomes local in pcie_pipe_misc_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 85. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 87. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 88. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 89. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 90. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 91. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 93. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 94. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 95. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 96. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 107. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 108. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 109. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 110. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 90. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 91. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 92. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 93. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 94. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 95. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 96. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 97. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 98. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 99. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 100. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTimeClient.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCRC32.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGMAC.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkICAPWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 200. parameter declaration becomes local in mc with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_buf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_dec_fix.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into library work +Parsing module . +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" into library work +Parsing module . +WARNING:HDLCompiler:751 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 271: Redeclaration of ansi port app_addr is not allowed +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPCM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktFork.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktMerge.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkUUID.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCCP.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWciMonitor.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFMC150.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkLCDController.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" into library work +Parsing module . + +========================================================================= +* HDL Elaboration * +========================================================================= +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Port flash_wp_n is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1440: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1472: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1473: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1480: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1481: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1482: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1483: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1484: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1488: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1489: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1490: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1491: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1492: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1493: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1494: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1495: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1496: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1497: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1506: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1507: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1508: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1509: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1510: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1514: Assignment to wtiS_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1515: Assignment to wtiS_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1516: Assignment to wtiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1517: Assignment to wtiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1519: Assignment to nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1520: Assignment to statusReg_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1521: Assignment to statusReg_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1522: Assignment to dataBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1529: Assignment to dataBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1533: Assignment to dataBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1537: Assignment to dataBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1538: Assignment to dataBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1539: Assignment to dataBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1540: Assignment to dataBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1541: Assignment to dataBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1542: Assignment to dataBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1543: Assignment to dataBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1544: Assignment to dataBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1546: Assignment to dataBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1547: Assignment to dataBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1548: Assignment to dataBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1555: Assignment to dataBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1560: Assignment to dataBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1561: Assignment to dataBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1563: Assignment to dataBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1564: Assignment to dataBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1566: Assignment to dataBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1567: Assignment to dataBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1568: Assignment to dataBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1569: Assignment to dataBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1571: Assignment to dataBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1572: Assignment to dataBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1574: Assignment to metaBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1581: Assignment to metaBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1585: Assignment to metaBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1589: Assignment to metaBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1590: Assignment to metaBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1591: Assignment to metaBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1592: Assignment to metaBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1593: Assignment to metaBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1594: Assignment to metaBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1595: Assignment to metaBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1596: Assignment to metaBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1598: Assignment to metaBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1599: Assignment to metaBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1600: Assignment to metaBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1607: Assignment to metaBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1612: Assignment to metaBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1613: Assignment to metaBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1615: Assignment to metaBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1616: Assignment to metaBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1618: Assignment to metaBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1619: Assignment to metaBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1620: Assignment to metaBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1621: Assignment to metaBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1623: Assignment to metaBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1624: Assignment to metaBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1626: Assignment to metaBram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1633: Assignment to metaBram_1_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1637: Assignment to metaBram_1_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1640: Assignment to metaBram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1641: Assignment to metaBram_1_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1642: Assignment to metaBram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1643: Assignment to metaBram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1644: Assignment to metaBram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1645: Assignment to metaBram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1646: Assignment to metaBram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1647: Assignment to metaBram_1_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1649: Assignment to metaBram_1_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1650: Assignment to metaBram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1651: Assignment to metaBram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1658: Assignment to metaBram_1_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1663: Assignment to metaBram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1664: Assignment to metaBram_1_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1666: Assignment to metaBram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1671: Assignment to metaBram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1672: Assignment to metaBram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1673: Assignment to metaBram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1674: Assignment to metaBram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1676: Assignment to metaBram_1_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1677: Assignment to metaBram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1679: Assignment to metaBram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1686: Assignment to metaBram_2_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1690: Assignment to metaBram_2_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1694: Assignment to metaBram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1695: Assignment to metaBram_2_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1696: Assignment to metaBram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1697: Assignment to metaBram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1698: Assignment to metaBram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1699: Assignment to metaBram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1700: Assignment to metaBram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1701: Assignment to metaBram_2_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1703: Assignment to metaBram_2_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1704: Assignment to metaBram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1705: Assignment to metaBram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1712: Assignment to metaBram_2_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1717: Assignment to metaBram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1718: Assignment to metaBram_2_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1720: Assignment to metaBram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1721: Assignment to metaBram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1723: Assignment to metaBram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1724: Assignment to metaBram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1725: Assignment to metaBram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1726: Assignment to metaBram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1728: Assignment to metaBram_2_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1729: Assignment to metaBram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1731: Assignment to metaBram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1738: Assignment to metaBram_3_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1742: Assignment to metaBram_3_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1746: Assignment to metaBram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1747: Assignment to metaBram_3_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1748: Assignment to metaBram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1749: Assignment to metaBram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1750: Assignment to metaBram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1751: Assignment to metaBram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1752: Assignment to metaBram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1753: Assignment to metaBram_3_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1755: Assignment to metaBram_3_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1756: Assignment to metaBram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1757: Assignment to metaBram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1764: Assignment to metaBram_3_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1769: Assignment to metaBram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1770: Assignment to metaBram_3_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1772: Assignment to metaBram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1773: Assignment to metaBram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1775: Assignment to metaBram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1776: Assignment to metaBram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1777: Assignment to metaBram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1778: Assignment to metaBram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1780: Assignment to metaBram_3_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1781: Assignment to metaBram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1783: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1784: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1785: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1786: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1787: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1788: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1789: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1790: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1791: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1792: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1793: Assignment to wti_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1794: Assignment to wti_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1795: Assignment to wti_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1796: Assignment to wti_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1797: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1801: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1808: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1809: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1819: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1820: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1822: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1823: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1824: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1826: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1827: Assignment to dataBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1831: Assignment to metaBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1836: Assignment to metaBram_1_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1837: Assignment to metaBram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1839: Assignment to metaBram_2_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1844: Assignment to metaBram_3_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1849: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1850: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1851: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2108: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2132: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2692: Assignment to isFirst ignored, since the identifier is never used +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1519: Port EN_uuid is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 829: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 883: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 884: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 888: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 889: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 890: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 891: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 892: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 896: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 897: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 898: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 899: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 900: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 901: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 902: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 903: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 904: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 905: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 906: Assignment to wmemi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 909: Assignment to wmemi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 910: Assignment to wmemi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 913: Assignment to wmemi_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 914: Assignment to wmemi_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 915: Assignment to wmemi_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 916: Assignment to wmemi_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 917: Assignment to wmemi_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 918: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 919: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 920: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 921: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 922: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 923: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 924: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 925: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 926: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 930: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 934: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 935: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 949: Assignment to wmemi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 952: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1120: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1144: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1238: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1286: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1307: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1434: Assignment to respCnt ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 787: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 830: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 831: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 835: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 836: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 837: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 838: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 839: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 843: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 844: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 845: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 846: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 847: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 848: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 849: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 850: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 851: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 852: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 861: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 862: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 863: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 864: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 865: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 869: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 870: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 872: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 873: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 874: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 875: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 876: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 877: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 878: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 879: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 880: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 881: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 882: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 883: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 884: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 885: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 886: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 890: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 894: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 895: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 905: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 906: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 908: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 909: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 910: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 912: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 913: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 915: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 916: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 917: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 918: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 919: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1019: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1043: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1128: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1152: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1349: Assignment to wci_wslv_cEdge ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1743: Assignment to tieOff0_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1744: Assignment to tieOff0_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1745: Assignment to tieOff0_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1746: Assignment to tieOff0_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1747: Assignment to tieOff0_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1748: Assignment to tieOff0_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1749: Assignment to tieOff0_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1750: Assignment to tieOff0_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1751: Assignment to tieOff0_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1752: Assignment to tieOff0_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1753: Assignment to tieOff5_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1754: Assignment to tieOff5_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1755: Assignment to tieOff5_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1756: Assignment to tieOff5_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1757: Assignment to tieOff5_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1758: Assignment to tieOff5_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1759: Assignment to tieOff5_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1760: Assignment to tieOff5_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1761: Assignment to tieOff5_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1762: Assignment to tieOff5_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1763: Assignment to tieOff6_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1764: Assignment to tieOff6_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1765: Assignment to tieOff6_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1766: Assignment to tieOff6_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1767: Assignment to tieOff6_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1768: Assignment to tieOff6_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1769: Assignment to tieOff6_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1770: Assignment to tieOff6_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1771: Assignment to tieOff6_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1772: Assignment to tieOff6_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1773: Assignment to tieOff7_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1774: Assignment to tieOff7_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1775: Assignment to tieOff7_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1776: Assignment to tieOff7_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1777: Assignment to tieOff7_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1778: Assignment to tieOff7_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1779: Assignment to tieOff7_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1780: Assignment to tieOff7_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1781: Assignment to tieOff7_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1782: Assignment to tieOff7_wci_Es_mData_w_whas ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBLUART.v" Line 383: Assignment to rxCtsReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9527: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9606: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9683: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9760: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9837: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9914: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9990: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10066: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10218: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10294: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10370: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10446: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10522: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10598: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10646: Assignment to warmResetP_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10647: Assignment to warmResetP_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10648: Assignment to timeServ_jamFrac_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10651: Assignment to timeServ_jamFracVal_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10652: Assignment to timeServ_jamFracVal_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10653: Assignment to deviceDNA_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10654: Assignment to deviceDNA_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10657: Assignment to devDNAV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10658: Assignment to rom_serverAdapter_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10672: Assignment to rom_serverAdapter_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10673: Assignment to rom_serverAdapter_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10675: Assignment to rom_serverAdapter_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10676: Assignment to rom_serverAdapter_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10678: Assignment to rom_serverAdapter_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10679: Assignment to rom_serverAdapter_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10680: Assignment to rom_serverAdapter_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10681: Assignment to rom_serverAdapter_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10683: Assignment to rom_serverAdapter_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10684: Assignment to rom_serverAdapter_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10686: Assignment to dna_rdReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10688: Assignment to dna_shftReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10690: Assignment to uuidV_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10691: Assignment to uuidV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10692: Assignment to wci_0_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10698: Assignment to wci_0_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10699: Assignment to wci_0_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10700: Assignment to wci_0_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10701: Assignment to wci_0_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10705: Assignment to wci_1_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10711: Assignment to wci_1_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10712: Assignment to wci_1_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10713: Assignment to wci_1_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10714: Assignment to wci_1_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10718: Assignment to wci_2_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10724: Assignment to wci_2_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10725: Assignment to wci_2_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10726: Assignment to wci_2_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10727: Assignment to wci_2_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10731: Assignment to wci_3_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10737: Assignment to wci_3_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10738: Assignment to wci_3_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10739: Assignment to wci_3_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10740: Assignment to wci_3_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10744: Assignment to wci_4_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10750: Assignment to wci_4_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10751: Assignment to wci_4_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10752: Assignment to wci_4_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10753: Assignment to wci_4_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10757: Assignment to wci_5_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10763: Assignment to wci_5_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10764: Assignment to wci_5_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10765: Assignment to wci_5_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10766: Assignment to wci_5_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10770: Assignment to wci_6_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10776: Assignment to wci_6_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10777: Assignment to wci_6_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10778: Assignment to wci_6_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10779: Assignment to wci_6_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10783: Assignment to wci_7_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10789: Assignment to wci_7_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10790: Assignment to wci_7_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10791: Assignment to wci_7_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10792: Assignment to wci_7_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10796: Assignment to wci_8_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10802: Assignment to wci_8_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10803: Assignment to wci_8_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10804: Assignment to wci_8_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10805: Assignment to wci_8_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10809: Assignment to wci_9_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10815: Assignment to wci_9_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10816: Assignment to wci_9_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10817: Assignment to wci_9_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10818: Assignment to wci_9_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10822: Assignment to wci_10_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10828: Assignment to wci_10_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10829: Assignment to wci_10_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10830: Assignment to wci_10_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10831: Assignment to wci_10_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10835: Assignment to wci_11_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10841: Assignment to wci_11_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10842: Assignment to wci_11_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10843: Assignment to wci_11_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10844: Assignment to wci_11_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10848: Assignment to wci_12_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10854: Assignment to wci_12_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10855: Assignment to wci_12_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10856: Assignment to wci_12_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10857: Assignment to wci_12_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10861: Assignment to wci_13_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10867: Assignment to wci_13_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10868: Assignment to wci_13_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10869: Assignment to wci_13_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10870: Assignment to wci_13_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10874: Assignment to wci_14_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10880: Assignment to wci_14_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10881: Assignment to wci_14_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10882: Assignment to wci_14_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10883: Assignment to wci_14_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10887: Assignment to wci_Emv_0_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10888: Assignment to wci_Emv_0_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10889: Assignment to wci_Emv_0_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10890: Assignment to wci_Emv_0_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10891: Assignment to wci_Emv_1_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10892: Assignment to wci_Emv_1_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10893: Assignment to wci_Emv_1_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10894: Assignment to wci_Emv_1_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10895: Assignment to wci_Emv_2_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10896: Assignment to wci_Emv_2_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10897: Assignment to wci_Emv_2_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10898: Assignment to wci_Emv_2_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10899: Assignment to wci_Emv_3_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10900: Assignment to wci_Emv_3_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10901: Assignment to wci_Emv_3_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10902: Assignment to wci_Emv_3_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10903: Assignment to wci_Emv_4_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10904: Assignment to wci_Emv_4_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10905: Assignment to wci_Emv_4_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10906: Assignment to wci_Emv_4_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10907: Assignment to wci_Emv_5_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10908: Assignment to wci_Emv_5_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10909: Assignment to wci_Emv_5_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10910: Assignment to wci_Emv_5_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10911: Assignment to wci_Emv_6_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10912: Assignment to wci_Emv_6_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10913: Assignment to wci_Emv_6_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10914: Assignment to wci_Emv_6_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10915: Assignment to wci_Emv_7_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10916: Assignment to wci_Emv_7_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10917: Assignment to wci_Emv_7_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10918: Assignment to wci_Emv_7_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10919: Assignment to wci_Emv_8_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10920: Assignment to wci_Emv_8_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10921: Assignment to wci_Emv_8_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10922: Assignment to wci_Emv_8_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10923: Assignment to wci_Emv_9_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10924: Assignment to wci_Emv_9_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10925: Assignment to wci_Emv_9_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10926: Assignment to wci_Emv_9_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10927: Assignment to wci_Emv_10_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10928: Assignment to wci_Emv_10_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10929: Assignment to wci_Emv_10_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10930: Assignment to wci_Emv_10_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10931: Assignment to wci_Emv_11_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10932: Assignment to wci_Emv_11_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10933: Assignment to wci_Emv_11_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10934: Assignment to wci_Emv_11_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10935: Assignment to wci_Emv_12_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10936: Assignment to wci_Emv_12_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10937: Assignment to wci_Emv_12_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10938: Assignment to wci_Emv_12_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10939: Assignment to wci_Emv_13_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10940: Assignment to wci_Emv_13_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10941: Assignment to wci_Emv_13_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10942: Assignment to wci_Emv_13_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10943: Assignment to wci_Emv_14_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10944: Assignment to wci_Emv_14_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10945: Assignment to wci_Emv_14_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10946: Assignment to wci_Emv_14_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10952: Assignment to wci_0_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10956: Assignment to wci_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10957: Assignment to wci_1_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10961: Assignment to wci_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10962: Assignment to wci_2_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10966: Assignment to wci_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10967: Assignment to wci_3_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10971: Assignment to wci_3_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10972: Assignment to wci_4_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10976: Assignment to wci_4_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10977: Assignment to wci_5_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10981: Assignment to wci_5_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10982: Assignment to wci_6_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10986: Assignment to wci_6_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10987: Assignment to wci_7_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10991: Assignment to wci_7_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10992: Assignment to wci_8_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10996: Assignment to wci_8_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10997: Assignment to wci_9_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11001: Assignment to wci_9_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11002: Assignment to wci_10_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11007: Assignment to wci_10_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11008: Assignment to wci_11_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11013: Assignment to wci_11_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11014: Assignment to wci_12_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11019: Assignment to wci_12_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11020: Assignment to wci_13_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11025: Assignment to wci_13_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11026: Assignment to wci_14_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11031: Assignment to wci_14_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12324: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12346: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12511: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12533: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12699: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12721: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12887: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12909: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13075: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13097: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13263: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13285: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13450: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13472: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13636: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13658: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13822: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13844: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14008: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14030: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14194: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14216: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14380: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14402: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14566: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14588: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14752: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14774: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14938: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14960: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15048: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15360: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15547: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15604: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15662: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15720: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15778: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15836: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15894: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15951: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16008: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16065: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16122: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16179: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16236: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16293: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16350: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 24738: Assignment to warmResetP ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 25886: Assignment to timeServ_ppsExtCapture ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3477: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3523: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3537: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3544: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3545: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3547: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3548: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3549: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3557: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3559: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3573: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3580: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3582: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3583: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3584: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3591: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3593: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3607: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3614: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3615: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3617: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3618: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3619: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3627: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3629: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3643: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3650: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3652: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3653: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3654: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3675: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3682: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3683: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3685: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3686: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3695: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3697: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3711: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3717: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3718: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3720: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3721: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3729: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3743: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3750: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3751: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3753: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3754: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3763: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3765: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3779: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3785: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3786: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3788: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3789: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3803: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3804: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3821: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3822: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3823: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3830: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3834: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3844: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3852: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3853: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3854: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3858: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3859: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3867: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3868: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3869: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3875: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3876: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3877: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3891: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3893: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3898: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3902: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3906: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3917: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3921: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3922: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3923: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3961: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3968: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3975: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3977: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3981: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3985: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3986: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3999: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4001: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4003: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4007: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4011: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4015: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4022: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4097: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4509: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4578: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4646: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4751: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4776: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4832: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4875: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4911: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5064: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5088: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5237: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5484: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5508: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5578: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5596: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5613: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5630: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5696: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5714: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5731: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5748: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5814: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5832: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5849: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5866: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5932: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5950: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5967: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5984: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6069: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6126: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7298: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3477: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3523: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3537: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3544: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3545: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3547: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3548: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3549: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3557: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3559: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3573: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3580: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3582: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3583: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3584: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3591: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3593: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3607: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3614: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3615: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3617: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3618: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3619: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3627: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3629: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3643: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3650: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3652: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3653: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3654: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3675: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3682: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3683: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3685: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3686: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3695: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3697: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3711: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3717: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3718: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3720: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3721: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3729: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3743: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3750: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3751: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3753: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3754: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3763: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3765: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3779: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3785: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3786: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3788: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3789: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3803: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3804: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3821: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3822: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3823: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3830: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3834: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3844: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3852: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3853: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3854: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3858: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3859: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3867: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3868: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3869: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3875: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3876: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3877: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3891: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3893: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3898: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3902: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3906: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3917: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3921: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3922: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3923: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3961: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3968: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3975: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3977: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3981: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3985: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3986: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3999: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4001: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4003: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4007: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4011: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4015: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4022: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4097: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4509: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4578: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4646: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4751: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4776: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4832: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4875: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4911: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5064: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5088: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5217: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5237: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5484: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5508: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5578: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5596: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5613: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5630: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5696: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5714: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5731: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5748: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5814: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5832: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5849: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5866: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5932: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5950: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5967: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5984: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6069: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6126: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7298: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 118: Assignment to wti_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 119: Assignment to wti_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 120: Assignment to wti_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 140: Assignment to wti_peerIsReady ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 198: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 240: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1731: Assignment to wtiM_0_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1732: Assignment to wtiM_0_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1733: Assignment to wtiM_1_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1734: Assignment to wtiM_1_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1735: Assignment to wtiM_2_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1736: Assignment to wtiM_2_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1737: Assignment to wtiM_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1738: Assignment to wtiM_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1739: Assignment to wtiM_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1960: Assignment to wtiM_0_peerIsReady ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1519: Input port EN_uuid is not connected on this instance +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1243: Port sda is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 353: Port pd_PSEN is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 347: Assignment to ocb_mon_PSDONE ignored, since the identifier is never used +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 369: Module memc_ui_top does not have a parameter named OCB_MONITOR +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 379: Module memc_ui_top does not have a parameter named SIM_CAL_OPTION +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 380: Module memc_ui_top does not have a parameter named SIM_INIT_OPTION + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 386: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 432: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" Line 146: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" Line 153: Net does not have a driver. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 443: Result of 64-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 444: Result of 64-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 168: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 169: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 201: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" Line 426: Result of 32-bit expression is truncated to fit in 6-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 140: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 198: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 204: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:532 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 323: Index <13> is out of range [12:0] for signal . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 151: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 506: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 764: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 854: Result of 8-bit expression is truncated to fit in 7-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 879: Result of 11-bit expression is truncated to fit in 10-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 888: Result of 10-bit expression is truncated to fit in 9-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 935: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 950: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 966: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 987: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1038: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1051: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1179: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1208: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1083: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1561: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1573: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1657: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1735: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1745: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" Line 232: Assignment to rst_r ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 152: Assignment to dqs_ibuf_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 288: Assignment to dqs_n_tfb ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" Line 147: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" Line 239: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" Line 199: Assignment to dqs_oe_r ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 269: Assignment to wrdata_en_r7 ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1549: Assignment to wrlvl_done_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1634: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1758: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1761: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1764: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1767: Result of 32-bit expression is truncated to fit in 8-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 284: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 298: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 523: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 540: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 453: Assignment to wl_state_r1 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 310: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 324: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 331: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 339: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 301: Found full_case directive in module phy_rdclk_gen. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 173: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 180: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" Line 163: Result of 10-bit expression is truncated to fit in 9-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 566: Result of 8-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 647: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 707: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 878: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 918: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 946: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1025: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1046: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1048: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1167: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1179: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1283: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1292: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1296: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1317: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1343: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1356: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1357: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1372: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1395: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1405: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1413: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1479: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1481: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1483: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1497: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1525: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1073: Assignment to found_two_edge_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1541: Result of 31-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1650: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1784: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1809: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1880: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1974: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1984: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1995: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2037: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2091: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" Line 275: Result of 32-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 199: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 229: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 416: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 417: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 593: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 977: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 568: Assignment to ecc_single ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 570: Assignment to ecc_err_addr ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" Line 232: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" Line 199: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 620: Assignment to hi_priority ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 377: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 378: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 396: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 412: Assignment to ddr3_parity ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 419: Assignment to bank_mach_next ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 423: Assignment to app_ecc_multiple_err_i ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 267: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 268: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 298: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 306: Net does not have a driver. +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 399: Input port pd_PSDONE is not connected on this instance +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1246: Size mismatch in connection of port . Formal port size is 27-bit while actual signal size is 33-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1295: Size mismatch in connection of port . Formal port size is 256-bit while actual signal size is 32-bit. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1655: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1701: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1702: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1708: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1709: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1710: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1711: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1712: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1716: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1717: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1718: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1719: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1720: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1721: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1722: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1723: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1724: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1725: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1726: Assignment to memc_wdfWren_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1730: Assignment to memc_wdfEnd_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1731: Assignment to memc_wdfEnd_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1737: Assignment to wmemi_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1743: Assignment to wmemi_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1744: Assignment to wmemi_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1749: Assignment to wmemi_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1754: Assignment to wmemi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1755: Assignment to wmemi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1756: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1757: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1758: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1759: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1760: Assignment to memInReset_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1761: Assignment to memInReset_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1762: Assignment to wmemiReadInFlight_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1766: Assignment to wmemiReadInFlight_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1767: Assignment to wmemiReadInFlight_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1768: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1769: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1770: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1771: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1772: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1773: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1774: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1775: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1776: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1777: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1778: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1782: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1788: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1789: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1803: Assignment to wmemi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1804: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1805: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1806: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1996: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2020: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2121: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2143: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2289: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2746: Assignment to pioReadInFlight ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2869: Assignment to dbgCtrl ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 915: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 948: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 949: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 955: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 956: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 957: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 958: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 959: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 963: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 964: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 965: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 966: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 967: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 968: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 969: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 970: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 971: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 972: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 973: Assignment to flashC_rseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 977: Assignment to flashC_rseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 978: Assignment to flashC_rseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 979: Assignment to flashC_rseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 980: Assignment to flashC_rseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 981: Assignment to flashC_rseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 982: Assignment to flashC_rseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 984: Assignment to flashC_wseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 988: Assignment to flashC_wseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 989: Assignment to flashC_wseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 990: Assignment to flashC_wseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 991: Assignment to flashC_wseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 992: Assignment to flashC_wseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 993: Assignment to flashC_wseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 995: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 999: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1005: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1006: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1025: Assignment to flashC_rseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1052: Assignment to flashC_wseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1268: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1446: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1470: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1586: Assignment to flashC_wdReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1227: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1264: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1265: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1273: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1274: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1275: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1276: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1277: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1281: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1282: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1283: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1284: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1285: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1286: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1287: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1288: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1289: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1290: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1297: Assignment to spiCDC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1298: Assignment to spiCDC_doResp_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1302: Assignment to spiDAC_cGate_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1305: Assignment to spiDAC_csbR_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1306: Assignment to spiDAC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1314: Assignment to fcCdc_pulseAction_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1315: Assignment to fcCdc_pulseAction_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1316: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1320: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1328: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1329: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1342: Assignment to spiCDC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1343: Assignment to spiCDC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1344: Assignment to spiCDC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1345: Assignment to spiCDC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1346: Assignment to spiCDC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1347: Assignment to spiCDC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1348: Assignment to spiCDC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1349: Assignment to spiCDC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1350: Assignment to spiCDC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1354: Assignment to spiDAC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1355: Assignment to spiDAC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1356: Assignment to spiDAC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1357: Assignment to spiDAC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1358: Assignment to spiDAC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1359: Assignment to spiDAC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1360: Assignment to spiDAC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1361: Assignment to spiDAC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1362: Assignment to spiDAC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1363: Assignment to fcCdc_grayCounter_pwIncrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1364: Assignment to fcCdc_grayCounter_pwDecrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1365: Assignment to oneKHz_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1366: Assignment to oneKHz_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1367: Assignment to spiCDC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1368: Assignment to spiDAC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1369: Assignment to fcCdc_grayCounter_wdCounterCrossing_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1719: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1743: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 2023: Assignment to splitReadInFlight ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 614: Assignment to gmii_rx_clk_O ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 624: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 626: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 627: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 628: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1023: Assignment to rxRS_rxOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1024: Assignment to rxRS_rxOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1025: Assignment to txRS_txOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1026: Assignment to txRS_txOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1035: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1051: Assignment to txRS_txDV_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1056: Assignment to txRS_txER_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1057: Assignment to txRS_txER_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1058: Assignment to txRS_underflow_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1059: Assignment to txRS_underflow_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1062: Assignment to rxRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1065: Assignment to rxRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1066: Assignment to txRS_preambleCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1067: Assignment to txRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1068: Assignment to txRS_ifgCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1078: Assignment to txRS_lenCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1085: Assignment to txRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1437: Assignment to txRS_underflow ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1485: Assignment to rxRS_isSOF ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1768: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1802: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1803: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1809: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1810: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1811: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1812: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1813: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1817: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1818: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1819: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1820: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1821: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1822: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1823: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1824: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1825: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1826: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1827: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1828: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1829: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1830: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1831: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1832: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1833: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1836: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1837: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1846: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1847: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1848: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1849: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1850: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1854: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1855: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1856: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1857: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1858: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1859: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1860: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1861: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1862: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1863: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1864: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1868: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1874: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1875: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1885: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1886: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1887: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1888: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1889: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1891: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1892: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1893: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1895: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1896: Assignment to mdi_pwTick_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1897: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1898: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1899: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2341: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2365: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3497: Assignment to txDBGPos ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3755: Assignment to wti_nowReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1806: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1877: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1923: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2064: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2278: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2746: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2822: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 719: Assignment to block_clk ignored, since the identifier is never used + +Elaborating module +. + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1273: Assignment to TRNRDLLPSRCRDYN ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 180: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 229: Result of 9-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1886: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 69-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1894: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 68-bit. + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 986: Assignment to rx_func_level_reset_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1918: Assignment to pciw_pci0_wTrnTxSof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1919: Assignment to pciw_pci0_wTrnTxSof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1920: Assignment to pciw_pci0_wTrnTxEof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1921: Assignment to pciw_pci0_wTrnTxEof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1922: Assignment to pciw_pci0_wTrnTxDsc_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1923: Assignment to pciw_pci0_wTrnTxDsc_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1924: Assignment to pciw_pci0_wTrnTxRem_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1925: Assignment to pciw_pci0_wTrnTxRem_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1926: Assignment to pciw_pci0_wTrnTxDat_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1927: Assignment to pciw_pci0_wTrnTxDat_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1928: Assignment to pciw_pci0_wTrnRxNpOk_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1929: Assignment to pciw_pci0_wTrnRxNpOk_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1930: Assignment to pciw_pci0_wTrnRxCplS_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1931: Assignment to pciw_pci0_wTrnRxCplS_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1932: Assignment to pciw_pcie_irq_wInterruptRdyN_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1934: Assignment to pciw_pcie_irq_wInterruptRdyN_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1935: Assignment to pciw_pcie_irq_wInterruptDo_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1937: Assignment to pciw_pcie_irq_wInterruptDo_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1950: Assignment to pciw_p2iAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1951: Assignment to pciw_p2iAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1952: Assignment to pciw_p2iAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1957: Assignment to pciw_i2pAF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1959: Assignment to pciw_i2pAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1960: Assignment to pciw_i2pAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1961: Assignment to pciw_i2pAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1962: Assignment to infLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1963: Assignment to blinkLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2348: Assignment to pciw_pcie_irq_rMMEnabled ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Input port gmii_col_i is not connected on this instance +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v". +WARNING:Xst:2898 - Port 'gmii_col_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_crs_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_intr_i', unconnected in block instance 'ftop', is tied to GND. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1242: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1242: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1778: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 82-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 82-bit register for signal . + Found 32-bit adder for signal created at line 1966. + Found 1-bit comparator equal for signal created at line 1868 + Found 1-bit comparator equal for signal created at line 2133 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 538 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1202: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 3-bit register for signal . + Found 2-bit subtractor for signal created at line 2087. + Found 2-bit subtractor for signal created at line 2205. + Found 2-bit subtractor for signal created at line 2537. + Found 32-bit adder for signal created at line 1421. + Found 32-bit adder for signal created at line 1422. + Found 2-bit adder for signal created at line 1428. + Found 2-bit adder for signal created at line 2086. + Found 32-bit adder for signal created at line 2173. + Found 32-bit adder for signal created at line 2192. + Found 2-bit adder for signal created at line 2204. + Found 32-bit adder for signal created at line 2230. + Found 3-bit adder for signal created at line 2474. + Found 3-bit adder for signal created at line 2474. + Found 3-bit adder for signal created at line 2485. + Found 3-bit adder for signal created at line 2485. + Found 3-bit adder for signal created at line 2493. + Found 3-bit adder for signal created at line 2493. + Found 3-bit adder for signal created at line 2499. + Found 3-bit adder for signal created at line 2499. + Found 3-bit adder for signal created at line 2507. + Found 3-bit adder for signal created at line 2507. + Found 14-bit adder for signal created at line 2515. + Found 3-bit adder for signal created at line 2518. + Found 3-bit adder for signal created at line 2538. + Found 3-bit adder for signal created at line 2539. + Found 4x3-bit Read Only RAM for signal <_n1538> + Found 1-bit 4-to-1 multiplexer for signal created at line 2589. + Found 32-bit 4-to-1 multiplexer for signal created at line 2624. + Found 1-bit 4-to-1 multiplexer for signal created at line 2649. + Found 1-bit 4-to-1 multiplexer for signal created at line 2674. + Found 34-bit 8-to-1 multiplexer for signal <_n1602> created at line 867. + Found 2-bit comparator greater for signal created at line 944 + Found 2-bit comparator greater for signal created at line 1511 + Found 1-bit comparator not equal for signal created at line 2089 + Found 1-bit comparator not equal for signal created at line 2207 + Found 3-bit comparator greater for signal created at line 2457 + Found 3-bit comparator greater for signal created at line 2459 + Found 3-bit comparator greater for signal created at line 2460 + Found 3-bit comparator greater for signal created at line 2461 + Found 3-bit comparator greater for signal created at line 2462 + Found 32-bit comparator greater for signal created at line 2481 + Found 32-bit comparator greater for signal created at line 2514 + Found 3-bit comparator greater for signal created at line 2592 + Found 3-bit comparator greater for signal created at line 2595 + Found 3-bit comparator greater for signal created at line 2598 + Found 3-bit comparator greater for signal created at line 2601 + Found 3-bit comparator greater for signal created at line 2613 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 347 D-type flip-flop(s). + inferred 16 Comparator(s). + inferred 22 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 1024x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 77 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCTop16B.v". +WARNING:Xst:2898 - Port 'EN_uuid', unconnected in block instance 'inf', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1519: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1519: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCApp16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" line 623: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit subtractor for signal created at line 813. + Found 32-bit subtractor for signal created at line 997. + Found 2-bit subtractor for signal created at line 1099. + Found 32-bit subtractor for signal created at line 1341. + Found 2-bit subtractor for signal created at line 1403. + Found 2-bit subtractor for signal created at line 1404. + Found 2-bit subtractor for signal created at line 1405. + Found 2-bit adder for signal created at line 819. + Found 2-bit adder for signal created at line 849. + Found 2-bit adder for signal created at line 860. + Found 32-bit adder for signal created at line 955. + Found 32-bit adder for signal created at line 961. + Found 32-bit adder for signal created at line 965. + Found 32-bit adder for signal > created at line 1006. + Found 32-bit adder for signal > created at line 1007. + Found 32-bit adder for signal > created at line 1008. + Found 32-bit adder for signal > created at line 1009. + Found 32-bit adder for signal created at line 1019. + Found 2-bit adder for signal created at line 1098. + Found 32-bit adder for signal > created at line 1171. + Found 32-bit adder for signal > created at line 1172. + Found 32-bit adder for signal > created at line 1173. + Found 32-bit adder for signal > created at line 1174. + Found 32-bit adder for signal created at line 1178. + Found 32-bit adder for signal created at line 1185. + Found 32-bit adder for signal created at line 1192. + Found 4x3-bit Read Only RAM for signal <_n1567> + Found 34-bit 13-to-1 multiplexer for signal <_n1655> created at line 525. + Found 2-bit comparator greater for signal created at line 576 + Found 1-bit comparator not equal for signal created at line 1101 + Found 128-bit comparator not equal for signal created at line 1372 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 25 Adder/Subtractor(s). + inferred 1201 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 264 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n1964> + Found 34-bit 24-to-1 multiplexer for signal <_n2118> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x169-bit dual-port RAM for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 338 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x169-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 174 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit subtractor for signal created at line 808. + Found 2-bit subtractor for signal created at line 998. + Found 2-bit subtractor for signal created at line 1245. + Found 2-bit subtractor for signal created at line 1318. + Found 2-bit adder for signal created at line 777. + Found 2-bit adder for signal created at line 809. + Found 2-bit adder for signal created at line 997. + Found 32-bit adder for signal created at line 1085. + Found 32-bit adder for signal created at line 1101. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1213. + Found 32-bit adder for signal created at line 1232. + Found 2-bit adder for signal created at line 1244. + Found 32-bit adder for signal created at line 1271. + Found 32-bit adder for signal > created at line 1321. + Found 32-bit adder for signal > created at line 1322. + Found 32-bit adder for signal > created at line 1323. + Found 32-bit adder for signal > created at line 1324. + Found 4x3-bit Read Only RAM for signal <_n0684> + Found 34-bit 15-to-1 multiplexer for signal <_n0763> created at line 537. + Found 2-bit comparator greater for signal created at line 579 + Found 2-bit comparator greater for signal created at line 866 + Found 1-bit comparator not equal for signal created at line 1000 + Found 1-bit comparator not equal for signal created at line 1247 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 16 Adder/Subtractor(s). + inferred 710 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2038> + Found 34-bit 24-to-1 multiplexer for signal <_n2111> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkUUID.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit comparator not equal for signal created at line 68 + Found 1-bit comparator equal for signal created at line 69 + Summary: + inferred 6 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCInf16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2077: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2524: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2524: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCCP.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5317: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5317: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5317: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5485: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5504: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5523: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5542: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5561: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5580: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5599: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5618: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5637: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5656: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5675: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5694: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5713: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5732: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5751: Output port of the instance is unconnected or connected to loadless signal. + Found 65-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 57-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 64-bit subtractor for signal created at line 11098. + Found 50-bit subtractor for signal created at line 12077. + Found 28-bit subtractor for signal created at line 12182. + Found 50-bit subtractor for signal <_281474976710656_MINUS_timeServ_delSecond__q1> created at line 17457. + Found 4-bit subtractor for signal created at line 17698. + Found 4-bit subtractor for signal created at line 17699. + Found 6-bit subtractor for signal created at line 17753. + Found 32-bit adder for signal created at line 9496. + Found 1-bit adder for signal created at line 9518. + Found 1-bit adder for signal created at line 9597. + Found 1-bit adder for signal created at line 9674. + Found 1-bit adder for signal created at line 9751. + Found 1-bit adder for signal created at line 9828. + Found 1-bit adder for signal created at line 9905. + Found 1-bit adder for signal created at line 9981. + Found 1-bit adder for signal created at line 10057. + Found 1-bit adder for signal created at line 10133. + Found 1-bit adder for signal created at line 10209. + Found 1-bit adder for signal created at line 10285. + Found 1-bit adder for signal created at line 10361. + Found 1-bit adder for signal created at line 10437. + Found 1-bit adder for signal created at line 10513. + Found 1-bit adder for signal created at line 10589. + Found 7-bit adder for signal created at line 11999. + Found 50-bit adder for signal created at line 12084. + Found 8-bit adder for signal created at line 12123. + Found 28-bit adder for signal created at line 12170. + Found 28-bit adder for signal created at line 12192. + Found 28-bit adder for signal created at line 12199. + Found 6-bit adder for signal created at line 12233. + Found 3-bit adder for signal created at line 17543. + Found 3-bit adder for signal created at line 17543. + Found 32-bit adder for signal created at line 17732. + Found 32-bit adder for signal created at line 17733. + Found 32-bit adder for signal created at line 17734. + Found 32-bit adder for signal created at line 17735. + Found 32-bit adder for signal created at line 17736. + Found 32-bit adder for signal created at line 17737. + Found 32-bit adder for signal created at line 17739. + Found 32-bit adder for signal created at line 17743. + Found 50-bit adder for signal created at line 17744. + Found 32-bit adder for signal created at line 17745. + Found 32-bit adder for signal created at line 17746. + Found 32-bit adder for signal created at line 17747. + Found 32-bit adder for signal created at line 17748. + Found 32-bit adder for signal created at line 17749. + Found 32-bit adder for signal created at line 17750. + Found 32-bit adder for signal created at line 17751. + Found 32-bit adder for signal created at line 17752. + Found 32-bit shifter logical left for signal created at line 4612 + Found 32-bit shifter logical left for signal created at line 4613 + Found 32-bit shifter logical left for signal created at line 4614 + Found 32-bit shifter logical left for signal created at line 4615 + Found 32-bit shifter logical left for signal created at line 4616 + Found 32-bit shifter logical left for signal created at line 4617 + Found 32-bit shifter logical left for signal created at line 4618 + Found 32-bit shifter logical left for signal created at line 4619 + Found 32-bit shifter logical left for signal created at line 4620 + Found 32-bit shifter logical left for signal created at line 4621 + Found 32-bit shifter logical left for signal created at line 4622 + Found 32-bit shifter logical left for signal created at line 4623 + Found 32-bit shifter logical left for signal created at line 4624 + Found 32-bit shifter logical left for signal created at line 4625 + Found 32-bit shifter logical left for signal created at line 4626 + Found 64x8-bit Read Only RAM for signal + Found 32-bit 16-to-1 multiplexer for signal created at line 17848. + Found 1-bit 16-to-1 multiplexer for signal created at line 17917. + Found 1-bit 16-to-1 multiplexer for signal created at line 17986. + Found 1-bit 16-to-1 multiplexer for signal created at line 18066. + Found 1-bit 16-to-1 multiplexer for signal created at line 18134. + Found 1-bit 16-to-1 multiplexer for signal created at line 18203. + Found 1-bit 16-to-1 multiplexer for signal created at line 18271. + Found 1-bit 16-to-1 multiplexer for signal created at line 18340. + Found 1-bit 16-to-1 multiplexer for signal created at line 18408. + Found 1-bit 16-to-1 multiplexer for signal created at line 18477. + Found 1-bit 16-to-1 multiplexer for signal created at line 18545. + Found 1-bit 16-to-1 multiplexer for signal created at line 18614. + Found 1-bit 16-to-1 multiplexer for signal created at line 18682. + Found 1-bit 16-to-1 multiplexer for signal created at line 18751. + Found 1-bit 16-to-1 multiplexer for signal created at line 18819. + Found 1-bit 16-to-1 multiplexer for signal created at line 18888. + Found 1-bit 16-to-1 multiplexer for signal created at line 18956. + Found 1-bit 16-to-1 multiplexer for signal created at line 19025. + Found 1-bit 16-to-1 multiplexer for signal created at line 19093. + Found 1-bit 16-to-1 multiplexer for signal created at line 19162. + Found 1-bit 16-to-1 multiplexer for signal created at line 19230. + Found 1-bit 16-to-1 multiplexer for signal created at line 19299. + Found 1-bit 16-to-1 multiplexer for signal created at line 19367. + Found 1-bit 16-to-1 multiplexer for signal created at line 19436. + Found 1-bit 16-to-1 multiplexer for signal created at line 19504. + Found 1-bit 16-to-1 multiplexer for signal created at line 19573. + Found 1-bit 16-to-1 multiplexer for signal created at line 19641. + Found 1-bit 16-to-1 multiplexer for signal created at line 19710. + Found 1-bit 16-to-1 multiplexer for signal created at line 19778. + Found 1-bit 16-to-1 multiplexer for signal created at line 19847. + Found 1-bit 16-to-1 multiplexer for signal created at line 19914. + Found 1-bit 16-to-1 multiplexer for signal created at line 19981. + Found 1-bit 16-to-1 multiplexer for signal created at line 20094. + Found 1-bit 16-to-1 multiplexer for signal created at line 20344. + Found 1-bit 16-to-1 multiplexer for signal created at line 20413. + Found 1-bit 16-to-1 multiplexer for signal created at line 20493. + Found 1-bit 16-to-1 multiplexer for signal created at line 20698. + Found 1-bit 16-to-1 multiplexer for signal created at line 20767. + Found 1-bit 16-to-1 multiplexer for signal created at line 20972. + Found 1-bit 16-to-1 multiplexer for signal created at line 21041. + Found 1-bit 16-to-1 multiplexer for signal created at line 21246. + Found 1-bit 16-to-1 multiplexer for signal created at line 21315. + Found 1-bit 16-to-1 multiplexer for signal created at line 21520. + Found 1-bit 16-to-1 multiplexer for signal created at line 21589. + Found 1-bit 16-to-1 multiplexer for signal created at line 21794. + Found 1-bit 16-to-1 multiplexer for signal created at line 21863. + Found 1-bit 16-to-1 multiplexer for signal created at line 22068. + Found 1-bit 16-to-1 multiplexer for signal created at line 22137. + Found 1-bit 16-to-1 multiplexer for signal created at line 22342. + Found 1-bit 16-to-1 multiplexer for signal created at line 22411. + Found 1-bit 16-to-1 multiplexer for signal created at line 22616. + Found 1-bit 16-to-1 multiplexer for signal created at line 22685. + Found 1-bit 16-to-1 multiplexer for signal created at line 22890. + Found 1-bit 16-to-1 multiplexer for signal created at line 22959. + Found 1-bit 16-to-1 multiplexer for signal created at line 23164. + Found 1-bit 16-to-1 multiplexer for signal created at line 23233. + Found 1-bit 16-to-1 multiplexer for signal created at line 23438. + Found 1-bit 16-to-1 multiplexer for signal created at line 23507. + Found 1-bit 16-to-1 multiplexer for signal created at line 23712. + Found 1-bit 16-to-1 multiplexer for signal created at line 23781. + Found 1-bit 16-to-1 multiplexer for signal created at line 23986. + Found 1-bit 16-to-1 multiplexer for signal created at line 24055. + Found 1-bit 16-to-1 multiplexer for signal created at line 24256. + Found 1-bit 16-to-1 multiplexer for signal created at line 24323. + Found 1-bit 16-to-1 multiplexer for signal created at line 24420. + Found 1-bit 16-to-1 multiplexer for signal created at line 24516. + Found 32-bit 16-to-1 multiplexer for signal created at line 24684. + Found 3-bit comparator greater for signal created at line 5928 + Found 7-bit comparator lessequal for signal created at line 10689 + Found 7-bit comparator lessequal for signal created at line 10689 + Found 28-bit comparator greater for signal created at line 12119 + Found 2-bit comparator not equal for signal created at line 16592 + Found 8-bit comparator greater for signal created at line 17481 + Found 8-bit comparator greater for signal created at line 17510 + Found 24-bit comparator greater for signal created at line 17512 + Found 24-bit comparator greater for signal created at line 17522 + Found 28-bit comparator greater for signal created at line 17552 + Found 28-bit comparator greater for signal created at line 17560 + Found 28-bit comparator greater for signal created at line 17562 + Found 32-bit comparator greater for signal created at line 17594 + Found 32-bit comparator greater for signal created at line 17601 + Found 32-bit comparator greater for signal created at line 17608 + Found 32-bit comparator greater for signal created at line 17615 + Found 32-bit comparator greater for signal created at line 17622 + Found 32-bit comparator greater for signal created at line 17629 + Found 32-bit comparator greater for signal created at line 17636 + Found 32-bit comparator greater for signal created at line 17643 + Found 32-bit comparator greater for signal created at line 17650 + Found 32-bit comparator greater for signal created at line 17657 + Found 32-bit comparator greater for signal created at line 17664 + Found 32-bit comparator greater for signal created at line 17671 + Found 32-bit comparator greater for signal created at line 17678 + Found 32-bit comparator greater for signal created at line 17685 + Found 32-bit comparator greater for signal created at line 17692 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 4107 D-type flip-flop(s). + inferred 27 Comparator(s). + inferred 300 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBLUART.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit adder for signal created at line 263. + Found 16-bit adder for signal created at line 284. + Found 4-bit adder for signal created at line 293. + Found 16-bit adder for signal created at line 338. + Found 16-bit comparator equal for signal created at line 243 + Found 16-bit comparator greater for signal created at line 284 + Found 16-bit comparator equal for signal created at line 339 + Found 16-bit comparator greater for signal created at line 340 + Found 16-bit comparator equal for signal created at line 349 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 68 D-type flip-flop(s). + inferred 5 Comparator(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 18 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM1Load.v". + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x64-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 86 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 30-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 10-bit subtractor for signal created at line 313. + Found 10-bit subtractor for signal created at line 314. + Found 2-bit subtractor for signal created at line 322. + Found 10-bit subtractor for signal created at line 323. + Found 12-bit subtractor for signal created at line 490. + Found 12-bit subtractor for signal created at line 522. + Found 2-bit adder for signal created at line 319. + Found 30-bit adder for signal created at line 321. + Found 2-bit subtractor for signal > created at line 203. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n0624> + Found 4x2-bit Read Only RAM for signal <_n0642> + Found 4x2-bit Read Only RAM for signal <_n0661> + Found 32-bit 4-to-1 multiplexer for signal created at line 548. + Summary: + inferred 4 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 283 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 56-bit register for signal . + Found 56-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 114 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 308 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2331: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 10-bit subtractor for signal created at line 3259. + Found 10-bit subtractor for signal created at line 3262. + Found 10-bit subtractor for signal created at line 3263. + Found 10-bit subtractor for signal created at line 3265. + Found 10-bit subtractor for signal created at line 3269. + Found 4-bit subtractor for signal created at line 3270. + Found 17-bit subtractor for signal created at line 3300. + Found 10-bit subtractor for signal created at line 3310. + Found 10-bit subtractor for signal created at line 3311. + Found 10-bit subtractor for signal created at line 3313. + Found 4-bit subtractor for signal created at line 3377. + Found 10-bit subtractor for signal created at line 3442. + Found 10-bit subtractor for signal created at line 3444. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3452. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3460. + Found 2-bit subtractor for signal created at line 3497. + Found 14-bit subtractor for signal created at line 3498. + Found 14-bit subtractor for signal created at line 3502. + Found 16-bit subtractor for signal created at line 4042. + Found 16-bit subtractor for signal created at line 4063. + Found 2-bit subtractor for signal created at line 5198. + Found 2-bit subtractor for signal created at line 5403. + Found 2-bit subtractor for signal created at line 5455. + Found 2-bit subtractor for signal created at line 6547. + Found 2-bit subtractor for signal created at line 6548. + Found 2-bit subtractor for signal created at line 6549. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6553. + Found 13-bit subtractor for signal created at line 6661. + Found 13-bit subtractor for signal created at line 6662. + Found 2-bit subtractor for signal created at line 6779. + Found 2-bit subtractor for signal created at line 6793. + Found 12-bit subtractor for signal created at line 6796. + Found 16-bit subtractor for signal created at line 6820. + Found 16-bit subtractor for signal created at line 6822. + Found 16-bit subtractor for signal created at line 6824. + Found 16-bit subtractor for signal created at line 6826. + Found 16-bit adder for signal created at line 3007. + Found 16-bit adder for signal created at line 3011. + Found 32-bit adder for signal created at line 3027. + Found 32-bit adder for signal created at line 3031. + Found 16-bit adder for signal created at line 3035. + Found 16-bit adder for signal created at line 3055. + Found 16-bit adder for signal created at line 3059. + Found 16-bit adder for signal created at line 3063. + Found 16-bit adder for signal created at line 3067. + Found 16-bit adder for signal created at line 3071. + Found 11-bit adder for signal created at line 3122. + Found 32-bit adder for signal created at line 3271. + Found 32-bit adder for signal created at line 3272. + Found 17-bit adder for signal created at line 3290. + Found 17-bit adder for signal created at line 3292. + Found 16-bit adder for signal created at line 3378. + Found 16-bit adder for signal created at line 3379. + Found 13-bit adder for signal created at line 3446. + Found 13-bit adder for signal created at line 3448. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3456. + Found 2-bit adder for signal created at line 3467. + Found 14-bit adder for signal created at line 3496. + Found 32-bit adder for signal created at line 3503. + Found 2-bit adder for signal created at line 3511. + Found 16-bit adder for signal created at line 4233. + Found 16-bit adder for signal created at line 4260. + Found 16-bit adder for signal created at line 4301. + Found 16-bit adder for signal created at line 4327. + Found 12-bit adder for signal created at line 4457. + Found 5-bit adder for signal created at line 4545. + Found 32-bit adder for signal created at line 4637. + Found 2-bit adder for signal created at line 5197. + Found 16-bit adder for signal created at line 5378. + Found 2-bit adder for signal created at line 5402. + Found 2-bit adder for signal created at line 5454. + Found 16-bit adder for signal created at line 5554. + Found 32-bit adder for signal created at line 6381. + Found 3-bit adder for signal created at line 6392. + Found 3-bit adder for signal created at line 6392. + Found 3-bit adder for signal created at line 6404. + Found 3-bit adder for signal created at line 6404. + Found 3-bit adder for signal created at line 6420. + Found 3-bit adder for signal created at line 6420. + Found 3-bit adder for signal created at line 6426. + Found 3-bit adder for signal created at line 6426. + Found 3-bit adder for signal created at line 6440. + Found 3-bit adder for signal created at line 6440. + Found 3-bit adder for signal created at line 6456. + Found 3-bit adder for signal created at line 6456. + Found 3-bit adder for signal created at line 6462. + Found 3-bit adder for signal created at line 6462. + Found 3-bit adder for signal created at line 6468. + Found 3-bit adder for signal created at line 6468. + Found 17-bit adder for signal created at line 6687. + Found 13-bit adder for signal created at line 6701. + Found 13-bit adder for signal created at line 6703. + Found 13-bit adder for signal created at line 6705. + Found 2-bit adder for signal created at line 6709. + Found 13-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6714. + Found 13-bit adder for signal created at line 6716. + Found 16-bit adder for signal created at line 6819. + Found 16-bit adder for signal created at line 6821. + Found 16-bit adder for signal created at line 6823. + Found 16-bit adder for signal created at line 6825. + Found 12-bit subtractor for signal created at line 6164. + Found 2-bit subtractor for signal created at line 1968. + Found 2-bit subtractor for signal created at line 1972. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4201> + Found 4x2-bit Read Only RAM for signal <_n4219> + Found 4x2-bit Read Only RAM for signal <_n4238> + Found 4x3-bit Read Only RAM for signal <_n4255> + Found 11-bit 4-to-1 multiplexer for signal created at line 3078. + Found 11-bit 4-to-1 multiplexer for signal created at line 3097. + Found 11-bit 4-to-1 multiplexer for signal created at line 3129. + Found 11-bit 4-to-1 multiplexer for signal created at line 3148. + Found 11-bit 4-to-1 multiplexer for signal created at line 3173. + Found 11-bit 4-to-1 multiplexer for signal created at line 3192. + Found 11-bit 4-to-1 multiplexer for signal created at line 3217. + Found 11-bit 4-to-1 multiplexer for signal created at line 3236. + Found 1-bit 4-to-1 multiplexer for signal created at line 6971. + Found 1-bit 4-to-1 multiplexer for signal created at line 6992. + Found 1-bit 4-to-1 multiplexer for signal created at line 7013. + Found 1-bit 4-to-1 multiplexer for signal created at line 7034. + Found 1-bit 4-to-1 multiplexer for signal created at line 7055. + Found 32-bit 4-to-1 multiplexer for signal created at line 7072. + Found 32-bit 4-to-1 multiplexer for signal created at line 7089. + Found 32-bit 4-to-1 multiplexer for signal created at line 7106. + Found 32-bit 4-to-1 multiplexer for signal created at line 7123. + Found 1-bit 4-to-1 multiplexer for signal created at line 7144. + Found 1-bit 4-to-1 multiplexer for signal created at line 7234. + Found 32-bit 4-to-1 multiplexer for signal created at line 7259. + Found 1-bit 4-to-1 multiplexer for signal created at line 7280. + Found 34-bit 44-to-1 multiplexer for signal <_n4512> created at line 1683. + Found 2-bit comparator greater for signal created at line 2039 + Found 2-bit comparator greater for signal created at line 3882 + Found 2-bit comparator greater for signal created at line 3887 + Found 1-bit comparator not equal for signal created at line 5200 + Found 1-bit comparator not equal for signal created at line 5405 + Found 1-bit comparator not equal for signal created at line 5457 + Found 10-bit comparator greater for signal created at line 6316 + Found 10-bit comparator greater for signal created at line 6318 + Found 10-bit comparator greater for signal created at line 6320 + Found 16-bit comparator equal for signal created at line 6377 + Found 16-bit comparator equal for signal created at line 6379 + Found 16-bit comparator equal for signal created at line 6388 + Found 16-bit comparator equal for signal created at line 6390 + Found 3-bit comparator greater for signal created at line 6396 + Found 3-bit comparator greater for signal created at line 6413 + Found 3-bit comparator greater for signal created at line 6424 + Found 3-bit comparator greater for signal created at line 6430 + Found 3-bit comparator greater for signal created at line 6444 + Found 3-bit comparator greater for signal created at line 6460 + Found 3-bit comparator greater for signal created at line 6466 + Found 3-bit comparator greater for signal created at line 6472 + Found 8-bit comparator equal for signal created at line 6486 + Found 17-bit comparator lessequal for signal created at line 6516 + Found 13-bit comparator lessequal for signal created at line 6670 + Found 10-bit comparator greater for signal created at line 6674 + Found 10-bit comparator greater for signal created at line 6676 + Found 8-bit comparator equal for signal created at line 6678 + Found 5-bit comparator equal for signal created at line 6679 + Found 3-bit comparator equal for signal created at line 6680 + Found 10-bit comparator lessequal for signal created at line 6690 + Found 10-bit comparator greater for signal created at line 6692 + Found 10-bit comparator lessequal for signal created at line 6699 + Found 10-bit comparator lessequal for signal created at line 6707 + Found 17-bit comparator lessequal for signal created at line 6815 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 91 Adder/Subtractor(s). + inferred 2516 D-type flip-flop(s). + inferred 34 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 153-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2448-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 153-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2608 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x146-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 151 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2331: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 4-bit subtractor for signal created at line 3270. + Found 17-bit subtractor for signal created at line 3308. + Found 10-bit subtractor for signal created at line 3310. + Found 10-bit subtractor for signal created at line 3311. + Found 10-bit subtractor for signal created at line 3313. + Found 4-bit subtractor for signal created at line 3377. + Found 10-bit subtractor for signal created at line 3442. + Found 10-bit subtractor for signal created at line 3444. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3452. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3460. + Found 2-bit subtractor for signal created at line 3497. + Found 14-bit subtractor for signal created at line 3498. + Found 14-bit subtractor for signal created at line 3502. + Found 16-bit subtractor for signal created at line 4042. + Found 16-bit subtractor for signal created at line 4063. + Found 2-bit subtractor for signal created at line 5198. + Found 2-bit subtractor for signal created at line 5403. + Found 2-bit subtractor for signal created at line 5455. + Found 2-bit subtractor for signal created at line 6547. + Found 2-bit subtractor for signal created at line 6548. + Found 2-bit subtractor for signal created at line 6549. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6553. + Found 13-bit subtractor for signal created at line 6661. + Found 13-bit subtractor for signal created at line 6662. + Found 2-bit subtractor for signal created at line 6779. + Found 2-bit subtractor for signal created at line 6793. + Found 12-bit subtractor for signal created at line 6796. + Found 16-bit subtractor for signal created at line 6820. + Found 16-bit subtractor for signal created at line 6822. + Found 16-bit subtractor for signal created at line 6824. + Found 16-bit subtractor for signal created at line 6826. + Found 16-bit adder for signal created at line 3007. + Found 16-bit adder for signal created at line 3011. + Found 32-bit adder for signal created at line 3027. + Found 32-bit adder for signal created at line 3031. + Found 16-bit adder for signal created at line 3035. + Found 16-bit adder for signal created at line 3055. + Found 16-bit adder for signal created at line 3059. + Found 16-bit adder for signal created at line 3063. + Found 16-bit adder for signal created at line 3067. + Found 16-bit adder for signal created at line 3071. + Found 11-bit adder for signal created at line 3122. + Found 32-bit adder for signal created at line 3271. + Found 32-bit adder for signal created at line 3272. + Found 16-bit adder for signal created at line 3378. + Found 16-bit adder for signal created at line 3379. + Found 32-bit adder for signal created at line 3383. + Found 13-bit adder for signal created at line 3446. + Found 13-bit adder for signal created at line 3448. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3456. + Found 2-bit adder for signal created at line 3467. + Found 14-bit adder for signal created at line 3496. + Found 32-bit adder for signal created at line 3503. + Found 2-bit adder for signal created at line 3511. + Found 16-bit adder for signal created at line 4233. + Found 16-bit adder for signal created at line 4260. + Found 16-bit adder for signal created at line 4301. + Found 16-bit adder for signal created at line 4327. + Found 12-bit adder for signal created at line 4457. + Found 32-bit adder for signal created at line 4637. + Found 2-bit adder for signal created at line 5197. + Found 16-bit adder for signal created at line 5378. + Found 2-bit adder for signal created at line 5402. + Found 2-bit adder for signal created at line 5454. + Found 16-bit adder for signal created at line 5554. + Found 32-bit adder for signal created at line 6381. + Found 3-bit adder for signal created at line 6392. + Found 3-bit adder for signal created at line 6392. + Found 3-bit adder for signal created at line 6404. + Found 3-bit adder for signal created at line 6404. + Found 3-bit adder for signal created at line 6420. + Found 3-bit adder for signal created at line 6420. + Found 3-bit adder for signal created at line 6426. + Found 3-bit adder for signal created at line 6426. + Found 3-bit adder for signal created at line 6440. + Found 3-bit adder for signal created at line 6440. + Found 3-bit adder for signal created at line 6456. + Found 3-bit adder for signal created at line 6456. + Found 3-bit adder for signal created at line 6462. + Found 3-bit adder for signal created at line 6462. + Found 3-bit adder for signal created at line 6468. + Found 3-bit adder for signal created at line 6468. + Found 17-bit adder for signal created at line 6689. + Found 13-bit adder for signal created at line 6701. + Found 13-bit adder for signal created at line 6703. + Found 13-bit adder for signal created at line 6705. + Found 2-bit adder for signal created at line 6709. + Found 13-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6714. + Found 13-bit adder for signal created at line 6716. + Found 16-bit adder for signal created at line 6819. + Found 16-bit adder for signal created at line 6821. + Found 16-bit adder for signal created at line 6823. + Found 16-bit adder for signal created at line 6825. + Found 12-bit subtractor for signal created at line 6164. + Found 2-bit subtractor for signal created at line 1968. + Found 2-bit subtractor for signal created at line 1972. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4123> + Found 4x3-bit Read Only RAM for signal <_n4132> + Found 4x2-bit Read Only RAM for signal <_n4153> + Found 4x2-bit Read Only RAM for signal <_n4180> + Found 11-bit 4-to-1 multiplexer for signal created at line 3078. + Found 11-bit 4-to-1 multiplexer for signal created at line 3097. + Found 11-bit 4-to-1 multiplexer for signal created at line 3129. + Found 11-bit 4-to-1 multiplexer for signal created at line 3148. + Found 11-bit 4-to-1 multiplexer for signal created at line 3173. + Found 11-bit 4-to-1 multiplexer for signal created at line 3192. + Found 11-bit 4-to-1 multiplexer for signal created at line 3217. + Found 11-bit 4-to-1 multiplexer for signal created at line 3236. + Found 1-bit 4-to-1 multiplexer for signal created at line 6971. + Found 1-bit 4-to-1 multiplexer for signal created at line 6992. + Found 1-bit 4-to-1 multiplexer for signal created at line 7013. + Found 1-bit 4-to-1 multiplexer for signal created at line 7034. + Found 1-bit 4-to-1 multiplexer for signal created at line 7055. + Found 32-bit 4-to-1 multiplexer for signal created at line 7072. + Found 32-bit 4-to-1 multiplexer for signal created at line 7089. + Found 32-bit 4-to-1 multiplexer for signal created at line 7106. + Found 32-bit 4-to-1 multiplexer for signal created at line 7123. + Found 1-bit 4-to-1 multiplexer for signal created at line 7144. + Found 1-bit 4-to-1 multiplexer for signal created at line 7234. + Found 32-bit 4-to-1 multiplexer for signal created at line 7259. + Found 1-bit 4-to-1 multiplexer for signal created at line 7280. + Found 34-bit 44-to-1 multiplexer for signal <_n4424> created at line 1683. + Found 2-bit comparator greater for signal created at line 2039 + Found 2-bit comparator greater for signal created at line 3882 + Found 2-bit comparator greater for signal created at line 3887 + Found 1-bit comparator not equal for signal created at line 5200 + Found 1-bit comparator not equal for signal created at line 5405 + Found 1-bit comparator not equal for signal created at line 5457 + Found 10-bit comparator greater for signal created at line 6316 + Found 10-bit comparator greater for signal created at line 6318 + Found 10-bit comparator greater for signal created at line 6320 + Found 16-bit comparator equal for signal created at line 6377 + Found 16-bit comparator equal for signal created at line 6379 + Found 16-bit comparator equal for signal created at line 6388 + Found 16-bit comparator equal for signal created at line 6390 + Found 3-bit comparator greater for signal created at line 6396 + Found 3-bit comparator greater for signal created at line 6413 + Found 3-bit comparator greater for signal created at line 6424 + Found 3-bit comparator greater for signal created at line 6430 + Found 3-bit comparator greater for signal created at line 6444 + Found 3-bit comparator greater for signal created at line 6460 + Found 3-bit comparator greater for signal created at line 6466 + Found 3-bit comparator greater for signal created at line 6472 + Found 17-bit comparator equal for signal created at line 6655 + Found 13-bit comparator lessequal for signal created at line 6666 + Found 10-bit comparator lessequal for signal created at line 6690 + Found 10-bit comparator greater for signal created at line 6692 + Found 10-bit comparator lessequal for signal created at line 6699 + Found 10-bit comparator lessequal for signal created at line 6707 + Found 17-bit comparator lessequal for signal created at line 6805 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 87 Adder/Subtractor(s). + inferred 2502 D-type flip-flop(s). + inferred 28 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTimeClient.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSM.v". + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktFork.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit shifter logical left for signal created at line 107 + Found 7-bit shifter logical left for signal created at line 107 + Found 1-bit 4-to-1 multiplexer for signal created at line 247. + Found 3-bit comparator equal for signal created at line 225 + Found 7-bit comparator equal for signal created at line 226 + Found 1-bit comparator equal for signal created at line 226 + Found 4-bit comparator equal for signal created at line 230 + Found 8-bit comparator equal for signal created at line 237 + Found 7-bit comparator equal for signal created at line 250 + Summary: + inferred 2 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 4 Multiplexer(s). + inferred 2 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktMerge.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1243: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1400: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit subtractor for signal created at line 1975. + Found 2-bit subtractor for signal created at line 2544. + Found 2-bit subtractor for signal created at line 2547. + Found 2-bit adder for signal created at line 1643. + Found 8-bit adder for signal created at line 1680. + Found 8-bit adder for signal created at line 1680. + Found 2-bit adder for signal created at line 1683. + Found 16-bit adder for signal created at line 1840. + Found 16-bit adder for signal created at line 1845. + Found 8-bit adder for signal created at line 1905. + Found 32-bit adder for signal created at line 1915. + Found 2-bit adder for signal created at line 1974. + Found 32-bit adder for signal created at line 2070. + Found 32-bit adder for signal created at line 2074. + Found 32-bit adder for signal created at line 2085. + Found 4x3-bit Read Only RAM for signal <_n1689> + Found 32-bit 39-to-1 multiplexer for signal <_n1810> created at line 887. + Found 34-bit 4-to-1 multiplexer for signal created at line 856. + Found 2-bit comparator greater for signal created at line 959 + Found 1-bit comparator not equal for signal created at line 1977 + Found 8-bit comparator greater for signal created at line 2314 + Found 8-bit comparator greater for signal created at line 2546 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 849 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 161 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 5-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 10 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 24-bit register for signal . + Found 24-bit register for signal . + Summary: + inferred 48 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x177-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 199 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x128-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 150 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v". +WARNING:Xst:2898 - Port 'dbg_wr_dqs_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_dq_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'pd_PSDONE', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_tap_set_en', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_inc_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_dec_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 334: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "syn_maxfan = 10" for signal . + Found 31-bit register for signal . + Summary: + inferred 31 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v". + Set property "syn_maxfan = 10" for signal . + Set property "syn_maxfan = 10" for signal . + Found 33-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 612: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'dfi_dram_clk_disable', unconnected in block 'mc', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'dfi_reset_n', unconnected in block 'mc', is tied to its initial value (1). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v". +WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 206. + Found 3-bit subtractor for signal created at line 267. + Found 4-bit subtractor for signal created at line 326. + Found 3-bit subtractor for signal created at line 385. + Found 3-bit adder for signal created at line 205. + Found 4-bit adder for signal created at line 329. + Found 3-bit comparator lessequal for signal created at line 271 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 17 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 6 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 236: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 321: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit subtractor for signal created at line 122. + Found 6-bit subtractor for signal created at line 147. + Found 20-bit subtractor for signal created at line 175. + Found 1-bit adder for signal created at line 267. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 43 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_col_r<10>', unconnected in block 'bank_compare', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 280 + Found 3-bit comparator equal for signal created at line 221 + Found 13-bit comparator equal for signal created at line 230 + Summary: + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 7 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 8 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'bank_common', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 2-bit subtractor for signal created at line 393. + Found 6-bit subtractor for signal created at line 430. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 18 Adder/Subtractor(s). + inferred 21 D-type flip-flop(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 159: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 185: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 235: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'arb_row_col', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'arb_row_col', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'row_mux.row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:2935 - Signal 'col_mux.col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 349 + Found 1-bit shifter logical left for signal > created at line 351 + Found 1-bit shifter logical left for signal created at line 390 + Summary: + inferred 13 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 3 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 11-bit register for signal >. + Found 1-bit register for signal >. + Found 11-bit register for signal . + Found 3-bit subtractor for signal created at line 260. + Found 2-bit subtractor for signal created at line 280. + Found 5-bit adder for signal created at line 377. + Found 5-bit adder for signal created at line 386. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 45 D-type flip-flop(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1131: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v". +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst - Value "0" of property "syn_replicate" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 256-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:1799 - State 011110 is never reached in FSM . +INFO:Xst:1799 - State 100101 is never reached in FSM . +INFO:Xst:1799 - State 100100 is never reached in FSM . +INFO:Xst:1799 - State 100111 is never reached in FSM . +INFO:Xst:1799 - State 011101 is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 86 | + | Inputs | 31 | + | Outputs | 43 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit subtractor for signal created at line 1560. + Found 7-bit adder for signal created at line 854. + Found 10-bit adder for signal created at line 879. + Found 9-bit adder for signal created at line 888. + Found 8-bit adder for signal created at line 935. + Found 8-bit adder for signal created at line 966. + Found 2-bit adder for signal created at line 987. + Found 2-bit adder for signal created at line 1038. + Found 3-bit adder for signal created at line 1051. + Found 2-bit adder for signal created at line 1561. + Found 2-bit adder for signal created at line 1573. + Found 2-bit adder for signal created at line 1657. + Found 4-bit adder for signal created at line 1735. + Found 5-bit subtractor for signal > created at line 764. + Found 16x256-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal + Found 2-bit comparator greater for signal created at line 1208 + Found 32-bit comparator not equal for signal created at line 1560 + Found 2-bit comparator greater for signal created at line 1597 + WARNING:Xst:2404 - FFs/Latches <7:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:2>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <2:10>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 468 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 21 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v". + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_keep = 1" for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 D-type flip-flop(s). + inferred 17 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v". + Set property "syn_maxfan = 1" for signal . + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 6-bit register for signal . + Found 6-bit register for signal . + Summary: + inferred 12 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal created at line 109. + Found 4-bit 4-to-1 multiplexer for signal created at line 133. + Summary: + inferred 17 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Summary: + inferred 14 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Summary: + inferred 26 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 108 D-type flip-flop(s). + inferred 124 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 2-bit adder for signal created at line 1634. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 137 D-type flip-flop(s). + inferred 146 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 40-bit register for signal >. + Found 16-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal >. + Found 40-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <9>>. + Found 1-bit register for signal <8>>. + Found 1-bit register for signal <7>>. + Found 1-bit register for signal <6>>. + Found 1-bit register for signal <5>>. + Found 1-bit register for signal <14>>. + Found 1-bit register for signal <13>>. + Found 1-bit register for signal <12>>. + Found 1-bit register for signal <11>>. + Found 1-bit register for signal <10>>. + Found 1-bit register for signal <19>>. + Found 1-bit register for signal <18>>. + Found 1-bit register for signal <17>>. + Found 1-bit register for signal <16>>. + Found 1-bit register for signal <15>>. + Found 1-bit register for signal <24>>. + Found 1-bit register for signal <23>>. + Found 1-bit register for signal <22>>. + Found 1-bit register for signal <21>>. + Found 1-bit register for signal <20>>. + Found 1-bit register for signal <29>>. + Found 1-bit register for signal <28>>. + Found 1-bit register for signal <27>>. + Found 1-bit register for signal <26>>. + Found 1-bit register for signal <25>>. + Found 1-bit register for signal <34>>. + Found 1-bit register for signal <33>>. + Found 1-bit register for signal <32>>. + Found 1-bit register for signal <31>>. + Found 1-bit register for signal <30>>. + Found 1-bit register for signal <39>>. + Found 1-bit register for signal <38>>. + Found 1-bit register for signal <37>>. + Found 1-bit register for signal <36>>. + Found 1-bit register for signal <35>>. + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal >. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 23 | + | Inputs | 10 | + | Outputs | 11 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 541. + Found 4-bit subtractor for signal created at line 581. + Found 2-bit adder for signal created at line 284. + Found 2-bit adder for signal created at line 298. + Found 5-bit adder for signal created at line 492. + Found 4-bit adder for signal created at line 566. + Found 4-bit adder for signal created at line 567. + Found 4-bit adder for signal created at line 568. + Found 2-bit adder for signal created at line 586. + Found 5-bit adder for signal created at line 641. + Found 3x4-bit multiplier for signal created at line 408. + Found 1-bit 8-to-1 multiplexer for signal created at line 264. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 299. + Found 5-bit 8-to-1 multiplexer for signal created at line 341. + Found 1-bit 8-to-1 multiplexer for signal created at line 512. + Found 1-bit 8-to-1 multiplexer for signal created at line 529. + Found 1-bit 16-to-1 multiplexer for signal created at line 640. + Found 1-bit 16-to-1 multiplexer for signal created at line 641. + Found 1-bit 8-to-1 multiplexer for signal created at line 665. + Found 1-bit 8-to-1 multiplexer for signal created at line 668. + Found 2-bit comparator lessequal for signal created at line 230 + Found 5-bit comparator greater for signal created at line 280 + Found 1-bit comparator equal for signal created at line 282 + Found 2-bit comparator greater for signal created at line 283 + Found 1-bit comparator equal for signal created at line 295 + Found 2-bit comparator greater for signal created at line 297 + Found 4-bit comparator lessequal for signal created at line 341 + Found 2-bit comparator lessequal for signal created at line 341 + Found 5-bit comparator greater for signal created at line 530 + Found 5-bit comparator greater for signal created at line 543 + Found 4-bit comparator lessequal for signal created at line 549 + Found 32-bit comparator equal for signal created at line 581 + Found 5-bit comparator lessequal for signal created at line 673 + Summary: + inferred 1 Multiplier(s). + inferred 10 Adder/Subtractor(s). + inferred 351 D-type flip-flop(s). + inferred 13 Comparator(s). + inferred 163 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 11 | + | Inputs | 4 | + | Outputs | 27 | + | Clock | clk (rising_edge) | + | Reset | rst_oserdes (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit adder for signal created at line 310. + Found 4-bit adder for signal created at line 324. + Found 4-bit adder for signal created at line 331. + Found 4-bit adder for signal created at line 339. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 81 D-type flip-flop(s). + inferred 8 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 256-bit register for signal . + Summary: + inferred 288 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v". + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 5-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 3-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 42 | + | Inputs | 18 | + | Outputs | 18 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 10 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 6 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 15 | + | Inputs | 9 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 1284. + Found 6-bit subtractor for signal created at line 1297. + Found 6-bit subtractor for signal created at line 1395. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 4-bit adder for signal created at line 647. + Found 4-bit adder for signal created at line 707. + Found 12-bit adder for signal created at line 918. + Found 12-bit adder for signal created at line 946. + Found 3-bit adder for signal created at line 1025. + Found 5-bit adder for signal created at line 1046. + Found 31-bit adder for signal created at line 1284. + Found 6-bit adder for signal created at line 1290. + Found 32-bit adder for signal created at line 1297. + Found 3-bit adder for signal created at line 1343. + Found 5-bit adder for signal created at line 1413. + Found 7-bit adder for signal created at line 1480. + Found 32-bit adder for signal created at line 1541. + Found 6-bit adder for signal created at line 1543. + Found 3-bit adder for signal created at line 1650. + Found 5-bit adder for signal created at line 1784. + Found 3-bit adder for signal created at line 1880. + Found 5-bit adder for signal created at line 1974. + Found 2-bit adder for signal created at line 1984. + Found 3-bit adder for signal created at line 1996. + Found 3-bit adder for signal created at line 2037. + Found 5-bit subtractor for signal > created at line 1048. + Found 6-bit subtractor for signal > created at line 1293. + Found 6-bit subtractor for signal > created at line 1372. + Found 5-bit subtractor for signal > created at line 1479. + Found 5-bit subtractor for signal > created at line 1483. + Found 5-bit subtractor for signal > created at line 1497. + Found 5-bit subtractor for signal > created at line 1525. + Found 5-bit subtractor for signal > created at line 1809. + Found 5-bit subtractor for signal > created at line 2091. + Found 3x3-bit multiplier for signal created at line 599. + Found 30-bit shifter logical right for signal created at line 1996 + Found 3x3-bit multiplier for signal created at line 2021. + Found 3-bit 3-to-1 multiplexer for signal created at line 490. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 5-bit comparator lessequal for signal created at line 1289 + Found 6-bit comparator greater for signal created at line 1290 + Found 3-bit comparator greater for signal created at line 1336 + Found 6-bit comparator greater for signal created at line 1383 + Found 6-bit comparator lessequal for signal created at line 1478 + Found 7-bit comparator lessequal for signal created at line 1480 + Found 5-bit comparator lessequal for signal created at line 1756 + Found 3-bit comparator greater for signal created at line 1872 + Found 5-bit comparator lessequal for signal created at line 2013 + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 Multiplier(s). + inferred 44 Adder/Subtractor(s). + inferred 870 D-type flip-flop(s). + inferred 73 Comparator(s). + inferred 232 Multiplexer(s). + inferred 1 Combinational logic shifter(s). + inferred 3 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 9 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 416. + Found 6-bit adder for signal created at line 502. + Found 16-bit adder for signal created at line 536. + Found 16-bit adder for signal created at line 546. + Found 4-bit adder for signal created at line 593. + Found 4-bit subtractor for signal created at line 184. + Found 5-bit subtractor for signal > created at line 417. + Found 1-bit 16-to-1 multiplexer for signal created at line 203. + Found 1-bit 16-to-1 multiplexer for signal created at line 205. + Found 1-bit 16-to-1 multiplexer for signal created at line 232. + Found 1-bit 16-to-1 multiplexer for signal created at line 233. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 67 D-type flip-flop(s). + inferred 12 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 11 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v". + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 256-bit register for signal . + Found 5-bit subtractor for signal created at line 376. + Found 4-bit adder for signal created at line 232. + Found 4-bit adder for signal created at line 252. + Found 4-bit adder for signal created at line 283. + Found 5-bit adder for signal created at line 377. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 339 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal created at line 224. + Found 6-bit adder for signal created at line 183. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 11 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 2-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 41 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 177-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 356 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2048-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 128-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2183 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 294 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 106 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFlashWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" line 585: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 84 | + | Inputs | 8 | + | Outputs | 8 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_182_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 25 | + | Transitions | 299 | + | Inputs | 11 | + | Outputs | 25 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_182_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1425. + Found 2-bit subtractor for signal created at line 1562. + Found 2-bit adder for signal created at line 903. + Found 2-bit adder for signal created at line 1424. + Found 4x3-bit Read Only RAM for signal <_n0834> + Found 32-bit 7-to-1 multiplexer for signal <_n0857> created at line 507. + Found 2-bit comparator greater for signal created at line 527 + Found 1-bit comparator not equal for signal created at line 1427 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 3 Adder/Subtractor(s). + inferred 315 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 41-bit register for signal . + Found 41-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFMC150.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 820: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 891: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 956: Output port of the instance is unconnected or connected to loadless signal. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 33-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 5-bit subtractor for signal created at line 1185. + Found 6-bit subtractor for signal created at line 1188. + Found 3-bit subtractor for signal created at line 1194. + Found 3-bit subtractor for signal created at line 1196. + Found 18-bit subtractor for signal created at line 1400. + Found 2-bit subtractor for signal created at line 1698. + Found 5-bit subtractor for signal <_31_MINUS_spiCDC_dPos_29___d230> created at line 1855. + Found 2-bit subtractor for signal created at line 1920. + Found 5-bit subtractor for signal created at line 1922. + Found 18-bit adder for signal created at line 1183. + Found 2-bit adder for signal created at line 1213. + Found 2-bit adder for signal created at line 1697. + Found 18-bit shifter logical left for signal created at line 708 + Found 4x3-bit Read Only RAM for signal <_n0979> + Found 1-bit 18-to-1 multiplexer for signal created at line 1179. + Found 1-bit 8-to-1 multiplexer for signal created at line 1207. + Found 1-bit 28-to-1 multiplexer for signal created at line 1921. + Found 1-bit 4-to-1 multiplexer for signal <_n0993> created at line 701. + Found 1-bit 4-to-1 multiplexer for signal <_n1003> created at line 700. + Found 2-bit comparator greater for signal created at line 782 + Found 1-bit comparator equal for signal created at line 969 + Found 1-bit comparator equal for signal created at line 976 + Found 1-bit comparator equal for signal created at line 1056 + Found 1-bit comparator not equal for signal created at line 1700 + Found 1-bit comparator equal for signal created at line 1848 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 11 Adder/Subtractor(s). + inferred 367 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 39 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 106. + Found 3-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetEither.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncReset0.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 106. + Found 4-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGbeWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1447: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1459: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1503: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1517: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 22-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 16 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_217_o_equal_658_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1793. + Found 22-bit subtractor for signal created at line 2096. + Found 2-bit subtractor for signal created at line 2320. + Found 2-bit subtractor for signal created at line 2964. + Found 5-bit subtractor for signal created at line 2966. + Found 5-bit subtractor for signal created at line 2967. + Found 5-bit subtractor for signal created at line 2968. + Found 5-bit adder for signal created at line 1745. + Found 4-bit adder for signal created at line 1746. + Found 4-bit adder for signal created at line 1748. + Found 2-bit adder for signal created at line 1756. + Found 32-bit adder for signal created at line 2101. + Found 32-bit adder for signal created at line 2108. + Found 32-bit adder for signal created at line 2141. + Found 32-bit adder for signal created at line 2146. + Found 32-bit adder for signal created at line 2211. + Found 32-bit adder for signal created at line 2225. + Found 32-bit adder for signal created at line 2229. + Found 32-bit adder for signal created at line 2262. + Found 2-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2407. + Found 32-bit adder for signal created at line 2423. + Found 5-bit adder for signal created at line 2957. + Found 32-bit adder for signal created at line 2965. + Found 4x3-bit Read Only RAM for signal <_n2215> + Found 4x10-bit Read Only RAM for signal <_n2472> + Found 256x2-bit Read Only RAM for signal <_n2868> + Found 8-bit 15-to-1 multiplexer for signal created at line 3010. + Found 8-bit 15-to-1 multiplexer for signal created at line 3059. + Found 8-bit 15-to-1 multiplexer for signal <_n2345> created at line 3108. + Found 8-bit 15-to-1 multiplexer for signal <_n2374> created at line 1132. + Found 8-bit 15-to-1 multiplexer for signal <_n2406> created at line 1131. + Found 34-bit 32-to-1 multiplexer for signal <_n2485> created at line 1093. + Found 2-bit comparator greater for signal created at line 1245 + Found 4-bit comparator greater for signal created at line 1748 + Found 22-bit comparator greater for signal created at line 2098 + Found 32-bit comparator greater for signal created at line 2200 + Found 1-bit comparator not equal for signal created at line 2322 + Found 8-bit comparator greater for signal created at line 2782 + Found 8-bit comparator equal for signal created at line 2810 + Found 8-bit comparator equal for signal created at line 2875 + Found 8-bit comparator equal for signal created at line 2877 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 3 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 1539 D-type flip-flop(s). + inferred 9 Comparator(s). + inferred 100 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGMAC.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 5-bit subtractor for signal created at line 995. + Found 3-bit subtractor for signal created at line 1397. + Found 4-bit adder for signal created at line 971. + Found 12-bit adder for signal created at line 999. + Found 5-bit adder for signal created at line 1003. + Found 8-bit 4-to-1 multiplexer for signal <_n0420> created at line 518. + Found 32-bit comparator not equal for signal created at line 975 + Found 4-bit comparator greater for signal created at line 1136 + Found 12-bit comparator greater for signal created at line 1394 + Found 5-bit comparator greater for signal created at line 1396 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 Adder/Subtractor(s). + inferred 113 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCRC32.v". + Found 32-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator not equal for signal created at line 127 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 48 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 16x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 5-bit comparator not equal for signal created at line 126 + Found 5-bit comparator not equal for signal created at line 127 + Found 5-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 56 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal created at line 50 + Summary: + inferred 1 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 112-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 226 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkLCDController.v". + Found 2-bit register for signal . + Found 24-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 15 | + | Inputs | 12 | + | Outputs | 2 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_240_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 61 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_240_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 140 | + | Transitions | 4472 | + | Inputs | 18 | + | Outputs | 139 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_240_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_240_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_240_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 24-bit subtractor for signal created at line 1550. + Found 8-bit adder for signal created at line 1551. + Found 5-bit adder for signal created at line 1594. + Found 4-bit adder for signal created at line 1595. + Found 8-bit 16-to-1 multiplexer for signal <_n1472> created at line 443. + Found 8-bit 16-to-1 multiplexer for signal <_n1503> created at line 443. + Found 5-bit comparator greater for signal created at line 2925 + Found 4-bit comparator greater for signal created at line 2938 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 330 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 11 Multiplexer(s). + inferred 5 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x81-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 81-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 88 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v". + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 709: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 99. + Found 8-bit adder for signal created at line 100. + Found 8-bit adder for signal created at line 101. + Summary: + inferred 3 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 8 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" line 254: Output port of the instance is unconnected or connected to loadless signal. + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 4-bit subtractor for signal created at line 484. + Found 5-bit adder for signal created at line 464. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 20 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | drp_clk (rising_edge) | + | Reset | Reset_n (negative) | + | Reset type | synchronous | + | Reset State | 0011 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 180. + Found 16x32-bit Read Only RAM for signal <_n0098> + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 10 D-type flip-flop(s). + inferred 7 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v". + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 26 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 00001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 14 | + | Inputs | 7 | + | Outputs | 4 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 308. + Found 4-bit adder for signal created at line 328. + Found 4-bit adder for signal created at line 360. + Found 5-bit comparator greater for signal created at line 283 + Found 4-bit comparator lessequal for signal created at line 356 + Summary: + inferred 3 Adder/Subtractor(s). + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 7 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 21 | + | Transitions | 40 | + | Inputs | 10 | + | Outputs | 21 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0000000000000100000000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 179. + Found 8-bit adder for signal created at line 180. + Found 1-bit comparator equal for signal created at line 534 + Summary: + inferred 2 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 19 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x8-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 41 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v". + Summary: + no macro. +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 100 + 1024x32-bit dual-port RAM : 5 + 1024x32-bit single-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 16x256-bit single-port Read Only RAM : 1 + 16x32-bit single-port Read Only RAM : 4 + 2048x169-bit dual-port RAM : 2 + 2048x32-bit dual-port RAM : 8 + 256x2-bit single-port Read Only RAM : 1 + 2x128-bit dual-port RAM : 1 + 2x146-bit dual-port RAM : 2 + 2x169-bit dual-port RAM : 3 + 2x177-bit dual-port RAM : 1 + 2x32-bit dual-port RAM : 26 + 2x61-bit dual-port RAM : 2 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 11 + 3x81-bit dual-port RAM : 2 + 4x10-bit single-port Read Only RAM : 1 + 4x16-bit single-port Read Only RAM : 3 + 4x2-bit single-port Read Only RAM : 9 + 4x3-bit single-port Read Only RAM : 12 + 64x8-bit single-port Read Only RAM : 1 + 8x10-bit dual-port RAM : 1 + 8x8-bit dual-port RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 816 + 1-bit adder : 120 + 10-bit adder : 1 + 10-bit subtractor : 16 + 11-bit adder : 2 + 12-bit adder : 15 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 7 + 14-bit subtractor : 6 + 16-bit adder : 36 + 16-bit addsub : 8 + 16-bit subtractor : 6 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit adder : 1 + 18-bit subtractor : 1 + 2-bit adder : 43 + 2-bit addsub : 44 + 2-bit subtractor : 72 + 20-bit subtractor : 1 + 22-bit subtractor : 1 + 24-bit adder : 2 + 24-bit subtractor : 1 + 28-bit adder : 3 + 28-bit subtractor : 1 + 3-bit adder : 64 + 3-bit subtractor : 11 + 30-bit adder : 1 + 31-bit adder : 1 + 32-bit adder : 100 + 32-bit subtractor : 3 + 4-bit adder : 31 + 4-bit addsub : 26 + 4-bit subtractor : 35 + 5-bit adder : 46 + 5-bit addsub : 4 + 5-bit subtractor : 21 + 50-bit adder : 2 + 50-bit subtractor : 2 + 6-bit adder : 12 + 6-bit subtractor : 10 + 64-bit subtractor : 1 + 7-bit adder : 3 + 8-bit adder : 23 + 9-bit adder : 1 +# Registers : 5195 + 1-bit register : 3169 + 10-bit register : 17 + 11-bit register : 2 + 112-bit register : 3 + 113-bit register : 2 + 12-bit register : 26 + 128-bit register : 12 + 129-bit register : 4 + 13-bit register : 13 + 130-bit register : 12 + 131-bit register : 4 + 139-bit register : 4 + 14-bit register : 16 + 146-bit register : 10 + 15-bit register : 5 + 153-bit register : 28 + 16-bit register : 106 + 169-bit register : 13 + 17-bit register : 20 + 177-bit register : 3 + 18-bit register : 7 + 182-bit register : 2 + 2-bit register : 295 + 20-bit register : 2 + 2048-bit register : 1 + 22-bit register : 1 + 24-bit register : 4 + 2448-bit register : 22 + 256-bit register : 3 + 27-bit register : 4 + 28-bit register : 24 + 3-bit register : 162 + 30-bit register : 1 + 31-bit register : 1 + 32-bit register : 245 + 33-bit register : 22 + 34-bit register : 37 + 4-bit register : 393 + 40-bit register : 34 + 41-bit register : 2 + 45-bit register : 5 + 48-bit register : 2 + 5-bit register : 105 + 50-bit register : 5 + 52-bit register : 4 + 56-bit register : 2 + 57-bit register : 1 + 59-bit register : 12 + 6-bit register : 160 + 61-bit register : 8 + 64-bit register : 19 + 65-bit register : 1 + 67-bit register : 6 + 7-bit register : 5 + 72-bit register : 26 + 79-bit register : 2 + 8-bit register : 92 + 81-bit register : 2 + 82-bit register : 2 + 9-bit register : 5 +# Comparators : 505 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 73 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 9 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 3342 + 1-bit 16-to-1 multiplexer : 71 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 1365 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 24 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 43 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 16 + 128-bit 16-to-1 multiplexer : 1 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 16 + 15-bit 2-to-1 multiplexer : 1 + 153-bit 16-to-1 multiplexer : 22 + 16-bit 2-to-1 multiplexer : 56 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 16-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 101 + 20-bit 2-to-1 multiplexer : 13 + 22-bit 2-to-1 multiplexer : 1 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 131 + 3-bit 3-to-1 multiplexer : 1 + 30-bit 2-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 320 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 47 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 32-to-1 multiplexer : 1 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 76 + 4-bit 4-to-1 multiplexer : 144 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 146 + 5-bit 8-to-1 multiplexer : 1 + 50-bit 2-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 3 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 86 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 5 + 8-bit 16-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 128 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 7 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 32-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 169-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 169-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 146-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 146-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 81-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 81-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 177-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 177-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 128-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 128-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 8-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 10-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 64-word x 8-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 256-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 100 + 1024x32-bit dual-port block RAM : 5 + 1024x32-bit single-port block RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 16x256-bit single-port distributed Read Only RAM : 1 + 16x32-bit single-port distributed Read Only RAM : 4 + 2048x169-bit dual-port block RAM : 2 + 2048x32-bit dual-port block RAM : 8 + 256x2-bit single-port distributed Read Only RAM : 1 + 2x128-bit dual-port distributed RAM : 1 + 2x146-bit dual-port distributed RAM : 2 + 2x169-bit dual-port distributed RAM : 3 + 2x177-bit dual-port distributed RAM : 1 + 2x32-bit dual-port distributed RAM : 26 + 2x61-bit dual-port distributed RAM : 2 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 11 + 3x81-bit dual-port distributed RAM : 2 + 4x10-bit single-port distributed Read Only RAM : 1 + 4x16-bit single-port distributed Read Only RAM : 3 + 4x2-bit single-port distributed Read Only RAM : 9 + 4x3-bit single-port distributed Read Only RAM : 12 + 64x8-bit single-port distributed Read Only RAM : 1 + 8x10-bit dual-port distributed RAM : 1 + 8x8-bit dual-port distributed RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 414 + 1-bit adder : 101 + 10-bit subtractor : 15 + 11-bit adder : 2 + 12-bit adder : 4 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 5 + 14-bit subtractor : 4 + 16-bit adder : 13 + 16-bit subtractor : 4 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit subtractor : 1 + 2-bit adder : 20 + 2-bit adder carry in : 1 + 2-bit subtractor : 64 + 24-bit subtractor : 1 + 28-bit subtractor : 1 + 3-bit adder : 3 + 3-bit adder carry in : 1 + 3-bit subtractor : 8 + 32-bit adder : 40 + 32-bit subtractor : 3 + 4-bit adder : 5 + 4-bit subtractor : 30 + 5-bit adder : 4 + 5-bit addsub : 1 + 5-bit subtractor : 17 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 6 + 64-bit subtractor : 1 + 7-bit adder : 2 + 8-bit adder : 12 +# Adder Trees : 3 + 2-bit / 5-inputs adder tree : 1 + 5-bit / 9-inputs adder tree : 2 +# Counters : 392 + 1-bit up counter : 107 + 10-bit down counter : 1 + 10-bit up counter : 1 + 12-bit up counter : 9 + 16-bit down counter : 2 + 16-bit up counter : 23 + 16-bit updown counter : 8 + 18-bit up counter : 1 + 2-bit down counter : 8 + 2-bit up counter : 14 + 2-bit updown counter : 44 + 20-bit down counter : 1 + 22-bit down counter : 1 + 28-bit up counter : 3 + 3-bit down counter : 3 + 3-bit up counter : 15 + 30-bit up counter : 1 + 32-bit up counter : 57 + 4-bit down counter : 5 + 4-bit up counter : 26 + 4-bit updown counter : 26 + 5-bit down counter : 4 + 5-bit up counter : 12 + 5-bit updown counter : 3 + 6-bit down counter : 4 + 6-bit up counter : 2 + 7-bit up counter : 2 + 8-bit up counter : 8 + 9-bit up counter : 1 +# Accumulators : 40 + 12-bit up accumulator cin : 2 + 14-bit down loadable accumulator : 2 + 14-bit up accumulator : 5 + 16-bit up accumulator : 2 + 3-bit up accumulator cin : 22 + 32-bit up loadable accumulator : 1 + 4-bit up loadable accumulator : 1 + 50-bit up accumulator : 1 + 50-bit up loadable accumulator : 1 + 6-bit up accumulator : 1 + 8-bit up accumulator cin : 1 + 8-bit up loadable accumulator : 1 +# Registers : 38727 + Flip-Flops : 38727 +# Shift Registers : 3498 + 16-bit dynamic shift register : 3498 +# Comparators : 505 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 73 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 9 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 4614 + 1-bit 15-to-1 multiplexer : 24 + 1-bit 16-to-1 multiplexer : 87 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 2615 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 32-to-1 multiplexer : 34 + 1-bit 4-to-1 multiplexer : 312 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 38 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 15 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 14 + 15-bit 2-to-1 multiplexer : 1 + 16-bit 2-to-1 multiplexer : 40 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 89 + 20-bit 2-to-1 multiplexer : 13 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 122 + 3-bit 3-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 287 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 36 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 56 + 4-bit 4-to-1 multiplexer : 72 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 31 + 5-bit 8-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 2 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 84 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 122 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 6 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 00001 | 000 + 00010 | 001 + 00100 | 010 + 01000 | 011 + 10000 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0001 | 00 + 0010 | 01 + 0100 | 11 + 1000 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0011 | 000 + 0110 | 001 + 0111 | 011 + 0001 | 010 + 1000 | 110 + 1001 | 111 + 0010 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------- + State | Encoding +---------------------------------------------------- + 0000000000000100000000000 | 000000000000000000001 + 0010000000000000000000000 | 000000000000000000010 + 0000100000000000000000000 | 000000000000000000100 + 0100000000000000000000000 | 000000000000000001000 + 1000000000000000000000000 | 000000000000000010000 + 0000000010000000000000000 | 000000000000000100000 + 0000000100000000000000000 | 000000000000001000000 + 0000000000000000000000010 | 000000000000010000000 + 0000001000000000000000000 | 000000000000100000000 + 0000000000000000000000001 | 000000000001000000000 + 0000000000010000000000000 | 000000000010000000000 + 0000000000000000010000000 | 000000000100000000000 + 0000010000000000000000000 | 000000001000000000000 + 0000000000000000000000100 | 000000010000000000000 + 0000000000000000000001000 | 000000100000000000000 + 0000000000000000001000000 | 000001000000000000000 + 0000000000100000000000000 | 000010000000000000000 + 0001000000000000000000000 | 000100000000000000000 + 0000000000000000100000000 | 001000000000000000000 + 0000000000000001000000000 | 010000000000000000000 + 0000000000000010000000000 | 100000000000000000000 +---------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 10 | 01 + 01 | 11 +------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------ + State | Encoding +------------------------------------ + 00000 | 0000000000000000000000001 + 11000 | 0000000000000000000000010 + 00001 | 0000000000000000000000100 + 00010 | 0000000000000000000001000 + 00011 | 0000000000000000000010000 + 00100 | 0000000000000000000100000 + 00111 | 0000000000000000001000000 + 01000 | 0000000000000000010000000 + 01001 | 0000000000000000100000000 + 01010 | 0000000000000001000000000 + 01011 | 0000000000000010000000000 + 01100 | 0000000000000100000000000 + 01111 | 0000000000001000000000000 + 10000 | 0000000000010000000000000 + 10001 | 0000000000100000000000000 + 10010 | 0000000001000000000000000 + 10011 | 0000000010000000000000000 + 10100 | 0000000100000000000000000 + 10111 | 0000001000000000000000000 + 00101 | 0000010000000000000000000 + 00110 | 0000100000000000000000000 + 01101 | 0001000000000000000000000 + 01110 | 0010000000000000000000000 + 10101 | 0100000000000000000000000 + 10110 | 1000000000000000000000000 +------------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------- + State | Encoding +-------------------- + 0000 | 000000001 + 0111 | 000000010 + 0001 | 000000100 + 0010 | 000001000 + 0101 | 000010000 + 0110 | 000100000 + 0011 | 001000000 + 0100 | 010000000 + 1010 | 100000000 +-------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 0000001 + 001 | 0000010 + 010 | 0000100 + 011 | 0001000 + 100 | 0010000 + 101 | 0100000 + 110 | 1000000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------------- + State | Encoding +------------------------------------------------- + 000000 | 0000000000000000000000000000000000001 + 000001 | 0000000000000000000000000000000000010 + 000010 | 0000000000000000000000000000000000100 + 000011 | 0000000000000000000000000000000001000 + 000100 | 0000000000000000000000000000000010000 + 010110 | 0000000000000000000000000000000100000 + 000101 | 0000000000000000000000000000001000000 + 000110 | 0000000000000000000000000000010000000 + 000111 | 0000000000000000000000000000100000000 + 001000 | 0000000000000000000000000001000000000 + 001001 | 0000000000000000000000000010000000000 + 001010 | 0000000000000000000000000100000000000 + 001011 | 0000000000000000000000001000000000000 + 001100 | 0000000000000000000000010000000000000 + 001101 | 0000000000000000000000100000000000000 + 010101 | 0000000000000000000001000000000000000 + 011010 | 0000000000000000000010000000000000000 + 011001 | 0000000000000000000100000000000000000 + 001111 | 0000000000000000001000000000000000000 + 010010 | 0000000000000000010000000000000000000 + 010100 | 0000000000000000100000000000000000000 + 010011 | 0000000000000001000000000000000000000 + 010111 | 0000000000000010000000000000000000000 + 011111 | 0000000000000100000000000000000000000 + 011000 | 0000000000001000000000000000000000000 + 011011 | 0000000000010000000000000000000000000 + 011100 | 0000000000100000000000000000000000000 + 010001 | 0000000001000000000000000000000000000 + 101000 | 0000000010000000000000000000000000000 + 001110 | 0000000100000000000000000000000000000 + 100011 | 0000001000000000000000000000000000000 + 101010 | 0000010000000000000000000000000000000 + 010000 | 0000100000000000000000000000000000000 + 011110 | unreached + 100000 | 0001000000000000000000000000000000000 + 100001 | 0010000000000000000000000000000000000 + 100010 | 0100000000000000000000000000000000000 + 100101 | unreached + 100100 | unreached + 100111 | unreached + 011101 | unreached + 101001 | 1000000000000000000000000000000000000 +------------------------------------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0100 | 0100 + 0011 | 0011 + 1000 | 1000 + 0111 | 0111 + 0110 | 0110 + 0101 | 0101 + 0010 | 0010 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 110 | 011 + 100 | 100 + 101 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00000 | 00000 + 00001 | 00001 + 00010 | 00010 + 00011 | 00011 + 01100 | 01100 + 01011 | 01011 + 00100 | 00100 + 00111 | 00111 + 00101 | 00101 + 01101 | 01101 + 00110 | 00110 + 01000 | 01000 + 10010 | 10010 + 01010 | 01010 + 01111 | 01111 + 01110 | 01110 + 10000 | 10000 + 01001 | 01001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0010 | 0010 + 0011 | 0011 + 0100 | 0100 + 0110 | 0110 + 0101 | 0101 + 0111 | 0111 + 1000 | 1000 + 1001 | 1001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 011 | 011 + 100 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1010 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0100 | 00000100000 + 0101 | 00001000000 + 0110 | 00010000000 + 0111 | 00100000000 + 1000 | 01000000000 + 1001 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------------------------------------------------------------------------------------------------------------- + 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00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 01000001 | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 10101010 | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------------------------------------------------------------------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +INFO:Xst:1901 - Instance use_ramb36.ramb36 in unit use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 +INFO:Xst:1901 - Instance GEN2_LINK.pipe_clk_bufgmux in unit pcie_clocking_v6 of type BUFGMUX has been replaced by BUFGCTRL +INFO:Xst:1901 - Instance gmii_rxc_dly in unit mkGMAC of type IODELAY has been replaced by IODELAYE1 +INFO:Xst:1901 - Instance gmii_rx_clk in unit mkGMAC of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 3. +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 16-bit shift register was found for signal and currently occupies 16 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 33-bit shift register was found for signal and currently occupies 33 logic cells (16 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 31-bit shift register was found for signal and currently occupies 31 logic cells (15 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 3-bit shift register for signal . +Unit processed. + +Processing Unit : + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 3-bit shift register for signal . + Found 16-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 4-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 34086 + Flip-Flops : 34086 +# Shift Registers : 44 + 10-bit shift register : 2 + 16-bit shift register : 5 + 2-bit shift register : 34 + 3-bit shift register : 2 + 4-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : fpgaTop.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 47339 +# BUF : 102 +# GND : 219 +# INV : 1309 +# LUT1 : 2525 +# LUT2 : 3384 +# LUT3 : 4614 +# LUT4 : 4061 +# LUT5 : 7070 +# LUT6 : 13874 +# MULT_AND : 90 +# MUXCY : 4688 +# MUXF7 : 749 +# MUXF8 : 99 +# VCC : 187 +# XORCY : 4368 +# FlipFlops/Latches : 34146 +# FD : 7175 +# FD_1 : 432 +# FDC : 480 +# FDCE : 1342 +# FDE : 10806 +# FDP : 146 +# FDPE : 58 +# FDR : 2128 +# FDRE : 9405 +# FDS : 112 +# FDSE : 2050 +# ODDR : 12 +# RAMS : 826 +# RAM32M : 431 +# RAM32X1D : 66 +# RAM64X1D : 288 +# RAMB18E1 : 3 +# RAMB36E1 : 38 +# Shift Registers : 2977 +# SRL16E : 5 +# SRLC16E : 2970 +# SRLC32E : 2 +# Clock Buffers : 12 +# BUFG : 11 +# BUFGCTRL : 1 +# IO Buffers : 232 +# IBUF : 29 +# IBUFDS : 2 +# IBUFDS_GTXE1 : 2 +# IOBUF : 81 +# IOBUFDS_DIFF_OUT : 8 +# OBUF : 109 +# OBUFDS : 1 +# GigabitIOs : 4 +# GTXE1 : 4 +# Others : 302 +# BUFIODQS : 9 +# BUFR : 3 +# DNA_PORT : 1 +# IDELAYCTRL : 1 +# IODELAYE1 : 91 +# ISERDESE1 : 72 +# MMCM_ADV : 2 +# OSERDESE1 : 122 +# PCIE_2_0 : 1 + +Device utilization summary: +--------------------------- + +Selected Device : 6vlx240tff1156-1 + + +Slice Logic Utilization: + Number of Slice Registers: 34146 out of 301440 11% + Number of Slice LUTs: 42246 out of 150720 28% + Number used as Logic: 36837 out of 150720 24% + Number used as Memory: 5409 out of 58400 9% + Number used as RAM: 2432 + Number used as SRL: 2977 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 57190 + Number with an unused Flip Flop: 23044 out of 57190 40% + Number with an unused LUT: 14944 out of 57190 26% + Number of fully used LUT-FF pairs: 19202 out of 57190 33% + Number of unique control sets: 2265 + +IO Utilization: + Number of IOs: 242 + Number of bonded IOBs: 237 out of 600 39% + +Specific Feature Utilization: + Number of Block RAM/FIFO: 40 out of 416 9% + Number using Block RAM only: 40 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT0 | 550 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT1 | 27930 | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | BUFGCTRL | 418 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDWE | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i)| 1 | +sys1_clkp | IBUF+IBUFDS_GTXE1+BUFG | 119 | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | BUFR | 134 | +sys0_clkp | MMCM_ADV:CLKOUT1 | 6206 | +flp_cdc_clk_p | IBUFDS+BUFG | 20 | +ftop/fmc150/spiCDC_cd/cntr_2 | BUFG | 76 | +ftop/fmc150/spiDAC_cd/cntr_3 | BUFG | 31 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| BUFR | 928 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| BUFR | 1542 | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/ctop/app/appW2/wmiM0_MDataValid(ftop/ctop/app/appW2/XST_GND:G) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 4 | +ftop/ctop/app/appW4/wmiM0_MAddrSpace(ftop/ctop/app/appW4/XST_GND:G) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 4 | +ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4600_o(ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4600_o1_INV_0:O) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i) | 3 | +ftop/ctop/app/appW2/respF_pwEnqueue_whas(ftop/ctop/app/appW2/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/app/appW4/respF_pwEnqueue_whas(ftop/ctop/app/appW4/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/inf/cp/rom_memory/DO<16>(ftop/ctop/inf/cp/rom_memory/XST_GND:G) | NONE(ftop/ctop/inf/cp/rom_memory/Mram_RAM1) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/N0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/XST_VCC:P) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0:Q) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/gbe0/gmac/CLK_GATE_rxclkBnd(ftop/gbe0/gmac/XST_VCC:P) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +ftop/gbe0/gmac/txRS_txER(ftop/gbe0/gmac/XST_GND:G) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -1 + + Minimum period: 4.758ns (Maximum Frequency: 210.172MHz) + Minimum input arrival time before clock: 1.793ns + Maximum output required time after clock: 1.923ns + Maximum combinational path delay: 0.538ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Clock period: 4.178ns (frequency: 239.331MHz) + Total number of paths / destination ports: 11317618 / 78697 +------------------------------------------------------------------------- +Delay: 8.357ns (Levels of Logic = 13) + Source: ftop/ctop/inf/cp/cpReq_26 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_0 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/ctop/inf/cp/cpReq_26 to ftop/ctop/inf/cp/cpRespF/data1_reg_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 28 0.375 0.733 cpReq_26 (cpReq_26) + LUT3:I0->O 64 0.068 0.577 Msub_wn___1__h79049_xor<2>11 (wn___1__h79049<2>) + LUT6:I5->O 64 0.068 0.559 Mmux__theResult_____1__h7819031 (_theResult_____1__h78190<2>) + MUXF7:S->O 1 0.267 0.000 Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 (Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7) + MUXF8:I0->O 2 0.175 0.423 Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 (CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884) + LUT6:I5->O 108 0.068 0.586 _n13773<34>21 (_n13773<34>2) + LUT6:I5->O 27 0.068 0.929 WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T) + LUT6:I0->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead8 (WILL_FIRE_RL_completeWorkerRead8) + LUT5:I4->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead13 (WILL_FIRE_RL_completeWorkerRead13) + LUT5:I4->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead30_SW0 (N478) + LUT6:I5->O 19 0.068 0.536 WILL_FIRE_RL_completeWorkerRead31 (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 6 0.068 0.450 cpRespF_ENQ1 (cpRespF_ENQ) + begin scope: 'ftop/ctop/inf/cp/cpRespF:ENQ' + LUT2:I1->O 40 0.068 0.553 d1di1 (d1di) + FDE:CE 0.263 data1_reg_0 + ---------------------------------------- + Total 8.357ns (1.760ns logic, 6.597ns route) + (21.1% logic, 78.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125' + Clock period: 3.724ns (frequency: 268.528MHz) + Total number of paths / destination ports: 4781 / 823 +------------------------------------------------------------------------- +Delay: 3.724ns (Levels of Logic = 5) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + + Data Path: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 4 0.375 0.798 state_FSM_FFd5 (state_FSM_FFd5) + LUT6:I0->O 1 0.068 0.491 nextwaitcounter2<7>112 (nextwaitcounter2<7>112) + LUT6:I4->O 2 0.068 0.423 nextwaitcounter2<7>113 (nextwaitcounter2<7>11) + LUT4:I3->O 2 0.068 0.423 nextwaitcounter2<1>31 (nextwaitcounter2<1>3) + LUT6:I5->O 14 0.068 0.863 nextwaitcounter2<0>11 (nextwaitcounter2<0>1) + LUT6:I0->O 1 0.068 0.000 nextwaitcounter<4>1 (nextwaitcounter<4>) + FDR:D 0.011 waitcounter_4 + ---------------------------------------- + Total 3.724ns (0.726ns logic, 2.998ns route) + (19.5% logic, 80.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys1_clkp' + Clock period: 3.851ns (frequency: 259.673MHz) + Total number of paths / destination ports: 7036 / 281 +------------------------------------------------------------------------- +Delay: 3.851ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Source Clock: sys1_clkp rising + Destination Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 6 0.375 0.808 dNotEmptyReg (dNotEmptyReg) + end scope: 'ftop/gbe0/gmac/txRS_txF:dEMPTY_N' + LUT6:I1->O 21 0.068 0.547 WILL_FIRE_RL_txRS_egress_Body11 (WILL_FIRE_RL_txRS_egress_Body1) + LUT6:I5->O 11 0.068 0.483 MUX_txRS_crc_add_1__SEL_11 (MUX_txRS_crc_add_1__SEL_1) + LUT6:I5->O 15 0.068 0.870 Mmux_txRS_crc_add_data12 (txRS_crc_add_data<0>) + begin scope: 'ftop/gbe0/gmac/txRS_crc:add_data<0>' + LUT6:I0->O 1 0.068 0.417 rRemainder$D_IN<5>1 (rRemainder$D_IN<5>1) + LUT5:I4->O 1 0.068 0.000 rRemainder$D_IN<5>3 (rRemainder$D_IN<5>) + FDSE:D 0.011 rRemainder_5 + ---------------------------------------- + Total 3.851ns (0.726ns logic, 3.125ns route) + (18.9% logic, 81.1% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Clock period: 3.539ns (frequency: 282.553MHz) + Total number of paths / destination ports: 2257 / 314 +------------------------------------------------------------------------- +Delay: 3.539ns (Levels of Logic = 4) + Source: ftop/gbe0/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Source Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: ftop/gbe0/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 3 0.375 0.792 rxRS_rxAPipe_3 (rxRS_rxAPipe_3) + LUT6:I0->O 2 0.068 0.423 WILL_FIRE_RL_rxRS_ingress_noadvance_SW0 (N10) + LUT6:I5->O 44 0.068 0.572 WILL_FIRE_RL_rxRS_ingress_noadvance (WILL_FIRE_RL_rxRS_ingress_noadvance) + LUT4:I3->O 2 0.068 0.423 WILL_FIRE_RL_rxRS_end_frame1 (WILL_FIRE_RL_rxRS_end_frame) + LUT5:I4->O 4 0.068 0.419 _n0454_inv1 (_n0454_inv) + FDRE:CE 0.263 rxRS_preambleCnt_value_0 + ---------------------------------------- + Total 3.539ns (0.910ns logic, 2.629ns route) + (25.7% logic, 74.3% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 4.758ns (frequency: 210.172MHz) + Total number of paths / destination ports: 166446 / 12719 +------------------------------------------------------------------------- +Delay: 4.758ns (Levels of Logic = 13) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl (FF) + Source Clock: sys0_clkp rising + Destination Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.375 0.784 io_config_r_1 (io_config_r_1) + LUT6:I0->O 1 0.068 0.417 Mmux_io_config_ns41 (Mmux_io_config_ns4) + LUT6:I5->O 1 0.068 0.417 Mmux_io_config_ns42 (Mmux_io_config_ns41) + LUT5:I4->O 20 0.068 0.542 Mmux_io_config_ns43 (dfi_odt_nom1<0>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:io_config<1>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:io_config<1>' + LUT4:I3->O 4 0.068 0.511 inhbt_wr_config11 (inhbt_wr_config) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:inhbt_wr_config' + LUT6:I4->O 6 0.068 0.808 rtc (rtc) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:rtc' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:rtc' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:rtc<2>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0:rtc<2>' + LUT6:I1->O 1 0.068 0.417 io_config_valid_ns_norst2 (io_config_valid_ns_norst2) + LUT2:I1->O 1 0.068 0.000 io_config_valid_ns_norst3 (io_config_valid_ns_norst) + FDR:D 0.011 io_config_valid_r_lcl + ---------------------------------------- + Total 4.758ns (0.862ns logic, 3.896ns route) + (18.1% logic, 81.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'flp_cdc_clk_p' + Clock period: 4.676ns (frequency: 213.858MHz) + Total number of paths / destination ports: 12407 / 37 +------------------------------------------------------------------------- +Delay: 4.676ns (Levels of Logic = 7) + Source: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 (FF) + Destination: ftop/fmc150/fcCdc_grayCounter_rsCounter_0 (FF) + Source Clock: flp_cdc_clk_p rising + Destination Clock: flp_cdc_clk_p rising + + Data Path: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 to ftop/fmc150/fcCdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 5 0.375 0.802 fcCdc_grayCounter_rsCounter_16 (fcCdc_grayCounter_rsCounter_16) + LUT6:I1->O 3 0.068 0.595 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>2 (Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>1) + LUT3:I0->O 14 0.068 0.502 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>4 (fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454) + LUT6:I5->O 13 0.068 0.571 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d49014 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490<0>) + LUT6:I4->O 1 0.068 0.638 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o_91 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o_91) + LUT6:I2->O 1 0.068 0.000 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o_4 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o_4) + MUXF7:I0->O 18 0.245 0.529 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o_2_f7 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_180_o_Mux_53_o) + LUT6:I5->O 1 0.068 0.000 Mmux_MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_181 (MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_1<16>) + FDC:D 0.011 fcCdc_grayCounter_rsCounter_16 + ---------------------------------------- + Total 4.676ns (1.039ns logic, 3.637ns route) + (22.2% logic, 77.8% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Clock period: 3.708ns (frequency: 269.687MHz) + Total number of paths / destination ports: 745 / 184 +------------------------------------------------------------------------- +Delay: 3.708ns (Levels of Logic = 7) + Source: ftop/fmc150/spiCDC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiCDC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_slowReset/reset_hold_1 to ftop/fmc150/spiCDC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 9 0.375 0.470 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiCDC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiCDC_reqF_dInReset:RST' + INV:I->O 8 0.086 0.824 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiCDC_reqF_dInReset:VAL' + LUT6:I0->O 4 0.068 0.511 MUX_spiCDC_rcv_d_write_1__SEL_21 (MUX_spiCDC_rcv_d_write_1__SEL_2) + LUT4:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable91 (Reset_OR_DriverANDClockEnable9) + FDRE:R 0.434 spiCDC_reqF_head_wrapped + ---------------------------------------- + Total 3.708ns (1.099ns logic, 2.609ns route) + (29.6% logic, 70.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Clock period: 3.785ns (frequency: 264.201MHz) + Total number of paths / destination ports: 336 / 69 +------------------------------------------------------------------------- +Delay: 3.785ns (Levels of Logic = 8) + Source: ftop/fmc150/spiDAC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiDAC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_slowReset/reset_hold_1 to ftop/fmc150/spiDAC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 6 0.375 0.450 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiDAC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiDAC_reqF_dInReset:RST' + INV:I->O 5 0.086 0.444 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiDAC_reqF_dInReset:VAL' + LUT6:I5->O 13 0.068 0.497 WILL_FIRE_RL_spiDAC_doxcv_d1 (WILL_FIRE_RL_spiDAC_doxcv_d) + LUT5:I4->O 2 0.068 0.423 spiDAC_reqF_head_wrapped_EN1 (spiDAC_reqF_head_wrapped_EN) + LUT3:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable101 (Reset_OR_DriverANDClockEnable10) + FDRE:R 0.434 spiDAC_reqF_head_wrapped + ---------------------------------------- + Total 3.785ns (1.167ns logic, 2.618ns route) + (30.8% logic, 69.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 2069 / 1093 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 3439 / 1815 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 25 / 25 +------------------------------------------------------------------------- +Offset: 1.457ns (Levels of Logic = 4) + Source: pci0_reset_n (PAD) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 (FF) + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising + + Data Path: pci0_reset_n to ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 pci0_reset_n_IBUF (pci0_reset_n_IBUF) + begin scope: 'ftop:pci0_rstn' + begin scope: 'ftop/pciw_pci0_pcie_ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i:sys_reset_n' + INV:I->O 22 0.086 0.535 sys_reset_n_inv1_INV_0 (sys_reset_n_inv) + FDCE:CLR 0.434 reg_count_23_16_0 + ---------------------------------------- + Total 1.457ns (0.523ns logic, 0.934ns route) + (35.9% logic, 64.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0/gmac:gmii_rx_rxd_i<0>' + FD:D 0.011 rxRS_rxData_0 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 75 / 75 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: ppsExtIn (PAD) + Destination: ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 (FF) + Destination Clock: sys0_clkp rising + + Data Path: ppsExtIn to ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 ppsExtIn_IBUF (ppsExtIn_IBUF) + begin scope: 'ftop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf/cp:gps_ppsSyncIn_x' + FDR:D 0.011 timeServ_ppsExtSync_d1 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_cdc_sdi (PAD) + Destination: ftop/fmc150/spiCDC_sdiP (FF) + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 falling + + Data Path: flp_cdc_sdi to ftop/fmc150/spiCDC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_cdc_sdi_IBUF (flp_cdc_sdi_IBUF) + begin scope: 'ftop:flpCDC_sdi_arg' + begin scope: 'ftop/fmc150:padsCDC_sdi_arg' + FD:D 0.011 spiCDC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_dac_sdi (PAD) + Destination: ftop/fmc150/spiDAC_sdiP (FF) + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 falling + + Data Path: flp_dac_sdi to ftop/fmc150/spiDAC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_dac_sdi_IBUF (flp_dac_sdi_IBUF) + begin scope: 'ftop:flpDAC_sdi_arg' + begin scope: 'ftop/fmc150:padsDAC_sdi_arg' + FD:D 0.011 spiDAC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 1665 / 675 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 999 / 405 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 79 / 62 +------------------------------------------------------------------------- +Offset: 1.360ns (Levels of Logic = 4) + Source: ftop/flash0/flashC_tsOE (FF) + Destination: flash_io_dq<15> (PAD) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/flash0/flashC_tsOE to flash_io_dq<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.399 flashC_tsOE (flashC_tsOE) + begin scope: 'ftop/flash0/flashC_tsd:OE' + INV:I->O 16 0.086 0.497 OE_inv1_INV_0 (OE_inv) + IOBUF:T->IO 0.003 IO_15_IOBUF (IO<15>) + end scope: 'ftop/flash0/flashC_tsd:IO<15>' + end scope: 'ftop/flash0:flash_io_dq<15>' + end scope: 'ftop:flash_io_dq<15>' + ---------------------------------------- + Total 1.360ns (0.464ns logic, 0.896ns route) + (34.1% logic, 65.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys1_clkp' + Total number of paths / destination ports: 12 / 12 +------------------------------------------------------------------------- +Offset: 1.009ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Destination: gmii_txd<7> (PAD) + Source Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_iobTxData_7 to gmii_txd<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ODDR:C->Q 1 0.607 0.399 txRS_iobTxData_7 (gmii_tx_txd<7>) + end scope: 'ftop/gbe0/gmac:gmii_tx_txd<7>' + end scope: 'ftop/gbe0:gmii_tx_txd<7>' + end scope: 'ftop:gmii_tx_txd<7>' + OBUF:I->O 0.003 gmii_txd_7_OBUF (gmii_txd<7>) + ---------------------------------------- + Total 1.009ns (0.610ns logic, 0.399ns route) + (60.5% logic, 39.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 1228 / 1056 +------------------------------------------------------------------------- +Offset: 1.870ns (Levels of Logic = 5) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST (PAD) + Source Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDP:C->Q 3 0.375 0.413 rstdiv0_sync_r_32 (rstdiv0_sync_r_32) + end scope: 'ftop/dram0/memc_memc/u_infrastructure:rstdiv0' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top:rst' + BUF:I->O 10 0.086 0.458 rst_1 (rst_1) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0:rst' + BUF:I->O 9 0.086 0.452 rst_8 (rst_8) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob:rst' + OSERDESE1:RST 0.000 u_oserdes_ck_p + ---------------------------------------- + Total 1.870ns (0.547ns logic, 1.323ns route) + (29.3% logic, 70.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 5 / 4 +------------------------------------------------------------------------- +Offset: 1.923ns (Levels of Logic = 4) + Source: ftop/fmc150/spiCDC_csbR (FF) + Destination: flp_com_sclk (PAD) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_csbR to flp_com_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 2 0.375 0.405 spiCDC_csbR (spiCDC_csbR) + INV:I->O 2 0.086 0.587 spiCDC_csbR_inv1_INV_0 (padsCDC_sclkgate) + end scope: 'ftop/fmc150:padsCDC_sclkgate' + end scope: 'ftop:flpCDC_sclkgate' + LUT4:I1->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.923ns (0.532ns logic, 1.391ns route) + (27.7% logic, 72.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 1.336ns (Levels of Logic = 3) + Source: ftop/fmc150/spiDAC_sdoR (FF) + Destination: flp_com_sdc2m (PAD) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_sdoR to flp_com_sdc2m + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.491 spiDAC_sdoR (spiDAC_sdoR) + end scope: 'ftop/fmc150:padsDAC_sdo' + end scope: 'ftop:flpDAC_sdo' + LUT4:I2->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.336ns (0.446ns logic, 0.890ns route) + (33.4% logic, 66.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 250 / 250 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_39 (dlyval_dq_39) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 150 / 150 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_14 (dlyval_dq_14) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 596 / 532 +------------------------------------------------------------------------- +Delay: 0.538ns (Levels of Logic = 3) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB (PAD) + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BUFIODQS:O 9 0.000 0.000 gen_ck_cpt[7].u_bufio_cpt (clk_cpt<7>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen:clk_cpt<7>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob:clk_cpt' + INV:I->O 0 0.086 0.000 iserdes_clkb1_INV_0 (iserdes_clkb) + ISERDESE1:CLKB 0.000 u_iserdes_dqs_p + ---------------------------------------- + Total 0.538ns (0.538ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock flp_cdc_clk_p +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 4.676| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.824| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiCDC_cd/cntr_2 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiCDC_cd/cntr_2 | 3.708| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.854| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiDAC_cd/cntr_3 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiDAC_cd/cntr_3 | 3.785| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.951| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 3.539| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.860| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 0.857| | | | +ftop/fmc150/spiCDC_cd/cntr_2 | 5.230| | | | +ftop/fmc150/spiDAC_cd/cntr_3 | 5.350| | | | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 2.078| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 8.357| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | 2.324| | | | +sys0_clkp | 2.712| | | | +sys1_clkp | 1.727| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 +-------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +-------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125| 3.724| | | | +-------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 1.675| | | | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 1.675| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | 2.227| | | | +sys0_clkp | 4.758| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 2.078| | | | +sys1_clkp | 3.851| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 352.00 secs +Total CPU time to Xst completion: 350.51 secs + +--> + + +Total memory usage is 1414812 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2461 ( 0 filtered) +Number of infos : 408 ( 0 filtered) + diff --git a/logs/ml605-20140126_1604/fpgaTop.bld b/logs/ml605-20140126_1604/fpgaTop.bld new file mode 100644 index 00000000..88c8e073 --- /dev/null +++ b/logs/ml605-20140126_1604/fpgaTop.bld @@ -0,0 +1,5797 @@ +Release 14.7 ngdbuild P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: /home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_trn_v6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc ml605.ucf -p xc6vlx240t-ff1156-1 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-ml605/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "ml605.ucf" ... +WARNING:NgdBuild - The value of SIM_DEVICE on instance + 'ftop/gbe0/gmac/rxClk_BUFR' of type BUFR has been changed from 'VIRTEX4' to + 'VIRTEX6' to correct post-ngdbuild and timing simulation for this primitive. + In order for functional simulation to be correct, the value of SIM_DEVICE + should be changed in this same manner in the source netlist or constraint + file. +Resolving constraint associations... +Checking Constraint Associations... +WARNING:ConstraintSystem - Constraint + [ml605.ucf(46)] was not distributed to the output pin TXOUTCLK of block + GTXD[0].GTX because the signal path to this output pin depends upon block + attribute settings. Constraint distribution does not support attribute + dependent distribution. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(113)]: NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(113)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(113)]: + NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(125)]: NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(125)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(125)]: + NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(126)]: NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(126)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(126)]: + NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(127)]: NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(127)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(127)]: + NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(281)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(286)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(287)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(294)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:58 - Constraint [ml605.ucf(761)]: INST + "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon" does not match any + design objects. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(761)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(768)]: INST "ftop/dram0/memc/u_infrastructure/u_mmcm_adv" not + found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(768)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(769)]: INST + "ftop/dram0/memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_ge + n/u_mmcm_clk_base" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(769)]' could not be + found and so the Locate constraint will be removed. + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT1: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT2: + +Done... + +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N100' has no driver +WARNING:NgdBuild:452 - logical net 'N101' has no driver +WARNING:NgdBuild:452 - logical net 'N102' has no driver +WARNING:NgdBuild:452 - logical net 'N103' has no driver +WARNING:NgdBuild:452 - logical net 'N104' has no driver +WARNING:NgdBuild:452 - logical net 'N105' has no driver +WARNING:NgdBuild:452 - logical net 'N106' has no driver +WARNING:NgdBuild:452 - logical net 'N107' has no driver +WARNING:NgdBuild:452 - logical net 'N108' has no driver +WARNING:NgdBuild:452 - logical net 'N109' has no driver +WARNING:NgdBuild:452 - logical net 'N110' has no driver +WARNING:NgdBuild:452 - logical net 'N111' has no driver +WARNING:NgdBuild:452 - logical net 'N112' has no driver +WARNING:NgdBuild:452 - logical net 'N113' has no driver +WARNING:NgdBuild:452 - logical net 'N114' has no driver +WARNING:NgdBuild:452 - logical net 'N115' has no driver +WARNING:NgdBuild:452 - logical net 'N116' has no driver +WARNING:NgdBuild:452 - logical net 'N117' has no driver +WARNING:NgdBuild:452 - logical net 'N118' has no driver +WARNING:NgdBuild:452 - logical net 'N119' has no driver +WARNING:NgdBuild:452 - logical net 'N120' has no driver +WARNING:NgdBuild:452 - logical net 'N121' has no driver +WARNING:NgdBuild:452 - logical net 'N122' has no driver +WARNING:NgdBuild:452 - logical net 'N123' has no driver +WARNING:NgdBuild:452 - logical net 'N124' has no driver +WARNING:NgdBuild:452 - logical net 'N125' has no driver +WARNING:NgdBuild:452 - logical net 'N126' has no driver +WARNING:NgdBuild:452 - logical net 'N127' has no driver +WARNING:NgdBuild:452 - logical net 'N128' has no driver +WARNING:NgdBuild:452 - logical net 'N129' has no driver +WARNING:NgdBuild:452 - logical net 'N130' has no driver +WARNING:NgdBuild:452 - logical net 'N131' has no driver +WARNING:NgdBuild:452 - logical net 'N132' has no driver +WARNING:NgdBuild:452 - logical net 'N133' has no driver +WARNING:NgdBuild:452 - logical net 'N134' has no driver +WARNING:NgdBuild:452 - logical net 'N135' has no driver +WARNING:NgdBuild:452 - logical net 'N136' has no driver +WARNING:NgdBuild:452 - logical net 'N137' has no driver +WARNING:NgdBuild:452 - logical net 'N138' has no driver +WARNING:NgdBuild:452 - logical net 'N139' has no driver +WARNING:NgdBuild:452 - logical net 'N140' has no driver +WARNING:NgdBuild:452 - logical net 'N141' has no driver +WARNING:NgdBuild:452 - logical net 'N142' has no driver +WARNING:NgdBuild:452 - logical net 'N143' has no driver +WARNING:NgdBuild:452 - logical net 'N144' has no driver +WARNING:NgdBuild:452 - logical net 'N145' has no driver +WARNING:NgdBuild:452 - logical net 'N146' has no driver +WARNING:NgdBuild:452 - logical net 'N147' has no driver +WARNING:NgdBuild:452 - logical net 'N148' has no driver +WARNING:NgdBuild:452 - logical net 'N149' has no driver +WARNING:NgdBuild:452 - logical net 'N150' has no driver +WARNING:NgdBuild:452 - logical net 'N151' has no driver +WARNING:NgdBuild:452 - logical net 'N152' has no driver +WARNING:NgdBuild:452 - logical net 'N153' has no driver +WARNING:NgdBuild:452 - logical net 'N154' has no driver +WARNING:NgdBuild:452 - logical net 'N155' has no driver +WARNING:NgdBuild:452 - logical net 'N156' has no driver +WARNING:NgdBuild:452 - logical net 'N157' has no driver +WARNING:NgdBuild:452 - logical net 'N158' has no driver +WARNING:NgdBuild:452 - logical net 'N159' has no driver +WARNING:NgdBuild:452 - logical net 'N160' has no driver +WARNING:NgdBuild:452 - logical net 'N161' has no driver +WARNING:NgdBuild:452 - logical net 'N162' has no driver +WARNING:NgdBuild:452 - logical net 'N163' has no driver +WARNING:NgdBuild:452 - logical net 'N164' has no driver +WARNING:NgdBuild:452 - logical net 'N165' has no driver +WARNING:NgdBuild:452 - logical net 'N166' has no driver +WARNING:NgdBuild:452 - logical net 'N167' has no driver +WARNING:NgdBuild:452 - logical net 'N168' has no driver +WARNING:NgdBuild:452 - logical net 'N169' has no driver +WARNING:NgdBuild:452 - logical net 'N170' has no driver +WARNING:NgdBuild:452 - logical net 'N171' has no driver +WARNING:NgdBuild:452 - logical net 'N172' has no driver +WARNING:NgdBuild:452 - logical net 'N173' has no driver +WARNING:NgdBuild:452 - logical net 'N174' has no driver +WARNING:NgdBuild:452 - logical net 'N175' has no driver +WARNING:NgdBuild:452 - logical net 'N176' has no driver +WARNING:NgdBuild:452 - logical net 'N177' has no driver +WARNING:NgdBuild:452 - logical net 'N178' has no driver +WARNING:NgdBuild:452 - logical net 'N179' has no driver +WARNING:NgdBuild:452 - logical net 'N180' has no driver +WARNING:NgdBuild:452 - logical net 'N181' has no driver +WARNING:NgdBuild:452 - logical net 'N182' has no driver +WARNING:NgdBuild:452 - logical net 'N183' has no driver +WARNING:NgdBuild:452 - logical net 'N184' has no driver +WARNING:NgdBuild:452 - logical net 'N185' has no driver +WARNING:NgdBuild:452 - logical net 'N186' has no driver +WARNING:NgdBuild:452 - logical net 'N187' has no driver +WARNING:NgdBuild:452 - logical net 'N188' has no driver +WARNING:NgdBuild:452 - logical net 'N189' has no driver +WARNING:NgdBuild:452 - logical net 'N190' has no driver +WARNING:NgdBuild:452 - logical net 'N191' has no driver +WARNING:NgdBuild:452 - logical net 'N192' has no driver +WARNING:NgdBuild:452 - logical net 'N193' has no driver +WARNING:NgdBuild:452 - logical net 'N194' has no driver +WARNING:NgdBuild:452 - logical net 'N195' has no driver +WARNING:NgdBuild:452 - logical net 'N196' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/upads_cts_arg' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_led' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0_wmemiS0_SRespLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<15>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<14>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<13>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<12>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<11>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<10>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_to_turnoff_n' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/pipe_tx_swing_o' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<42>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<0>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<21>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<20>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<19>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<18>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<154>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<28>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<161>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_ra' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_a<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/io_config_ns<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/m + aintenance_request.maint_grant_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<0> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<1> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<2> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<3> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/low_idle_cnt_r + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/was_priority' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd0_col' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd1_row' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<15>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<14>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<13>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<12>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<11>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<10>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<9>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<23>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<22>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<21>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<20>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<19>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<18>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<17>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<31>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<30>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<29>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<28>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<27>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<26>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<25>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<0>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<39>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<38>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<37>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<36>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<35>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<34>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<33>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<32>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<31>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<30>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<29>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<28>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<27>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<26>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<25>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<24>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<23>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<22>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<21>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<20>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<19>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<18>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<17>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<16>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<15>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<14>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<13>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<12>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<11>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<10>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<9>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<8>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/pd_prech_req' has no + driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 2508 + +Total memory usage is 832296 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 47 sec +Total CPU time to NGDBUILD completion: 47 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/ml605-20140126_1604/fpgaTop.par b/logs/ml605-20140126_1604/fpgaTop.par new file mode 100644 index 00000000..862698ac --- /dev/null +++ b/logs/ml605-20140126_1604/fpgaTop.par @@ -0,0 +1,1217 @@ +Release 14.7 par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +ar-cms520:: Sun Jan 26 15:53:32 2014 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '6vlx240t.nph' in environment /home/shep/ISE/14.7/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) + + +Device speed data version: "PRODUCTION 1.17 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 33,948 out of 301,440 11% + Number used as Flip Flops: 33,941 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 42,307 out of 150,720 28% + Number used as logic: 36,455 out of 150,720 24% + Number using O6 output only: 32,879 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,166 + Number used as ROM: 0 + Number used as Memory: 5,075 out of 58,400 8% + Number used as Dual Port RAM: 2,098 + Number using O6 output only: 106 + Number using O5 output only: 53 + Number using O5 and O6: 1,939 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 777 + Number with same-slice register load: 646 + Number with same-slice carry load: 129 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,628 out of 37,680 44% + Number of LUT Flip Flop pairs used: 50,165 + Number with an unused Flip Flop: 17,229 out of 50,165 34% + Number with an unused LUT: 7,858 out of 50,165 15% + Number of fully used LUT-FF pairs: 25,078 out of 50,165 49% + Number of slice register sites lost + to control set restrictions: 0 out of 301,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + + +Overall effort level (-ol): Standard +Router effort level (-rl): High + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +Starting initial Timing Analysis. REAL time: 39 secs +Finished initial Timing Analysis. REAL time: 41 secs + +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal upads_cts_arg_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMB_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<29> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<31> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<145> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<173> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<7> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem27_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<19> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<17> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMB_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/txRS_txF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +Starting Router + + +Phase 1 : 255859 unrouted; REAL time: 46 secs + +Phase 2 : 219053 unrouted; REAL time: 1 mins 2 secs + +Phase 3 : 71679 unrouted; REAL time: 1 mins 55 secs + +Phase 4 : 72086 unrouted; (Setup:12067, Hold:29862, Component Switching Limit:0) REAL time: 2 mins 13 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:36370, Hold:28250, Component Switching Limit:0) REAL time: 4 mins + +Phase 6 : 0 unrouted; (Setup:21011, Hold:28250, Component Switching Limit:0) REAL time: 5 mins 14 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 7 : 0 unrouted; (Setup:21011, Hold:28250, Component Switching Limit:0) REAL time: 6 mins 34 secs + +Phase 8 : 0 unrouted; (Setup:21011, Hold:28250, Component Switching Limit:0) REAL time: 6 mins 34 secs + +Phase 9 : 0 unrouted; (Setup:21011, Hold:28250, Component Switching Limit:0) REAL time: 6 mins 34 secs + +Phase 10 : 0 unrouted; (Setup:21011, Hold:55, Component Switching Limit:0) REAL time: 6 mins 40 secs + +Phase 11 : 0 unrouted; (Setup:19394, Hold:55, Component Switching Limit:0) REAL time: 6 mins 52 secs +Total REAL time to Router completion: 6 mins 52 secs +Total CPU time to Router completion: 7 mins 18 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/p125clk |BUFGCTRL_X0Y29| No | 7936 | 0.466 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| _tb_clk |BUFGCTRL_X0Y25| No | 2132 | 0.354 | 1.953 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/rxclkBnd | Regional Clk| No | 48 | 0.128 | 0.987 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/sys0_clk_O_BUFG | | | | | | +| | BUFGCTRL_X0Y1| No | 232 | 0.365 | 1.953 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep_trn_clk |BUFGCTRL_X0Y28| No | 234 | 0.183 | 1.787 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1_clk_O |BUFGCTRL_X0Y24| No | 55 | 0.229 | 1.953 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/pipe_clk |BUFGCTRL_X0Y30| No | 181 | 0.418 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<1> | Regional Clk|Yes | 450 | 0.282 | 1.125 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<0> | Regional Clk|Yes | 263 | 0.155 | 0.993 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpDAC_sclk | BUFGCTRL_X0Y3| No | 17 | 0.048 | 1.650 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpCDC_sclk | BUFGCTRL_X0Y2| No | 27 | 0.073 | 1.653 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flp_clk_O_BUFG | BUFGCTRL_X0Y0| No | 9 | 0.021 | 1.658 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/TxOutClk_bufg |BUFGCTRL_X0Y31| No | 6 | 0.010 | 1.633 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_mem |BUFGCTRL_X0Y26| No | 186 | 0.164 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/ctop/inf/cp/dna | | | | | | +| _cnt<0> | Local| | 11 | 0.000 | 2.127 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_I1 | Local| | 3 | 0.000 | 1.348 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_309_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.277 | 0.513 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| I1 | Local| | 3 | 0.000 | 1.965 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| OUT | Local| | 2 | 0.000 | 0.469 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_OUT | Local| | 2 | 0.000 | 0.477 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<7> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_wr_i | Local| | 10 | 0.402 | 1.403 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<6> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<2> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<3> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<4> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<5> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<0> | Local| | 18 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_clk_O | | | | | | +| | Local| | 8 | 0.000 | 2.396 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<1> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_301_ML_NE | | | | | | +| W_CLK | Local| | 2 | 0.000 | 0.594 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 19449 (Setup: 19394, Hold: 55, Component Switching Limit: 0) + +WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. + + Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options + are set in the tools for timing closure. + + Increase the PAR Effort Level setting to "high" + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + + Visit the Xilinx technical support web at http://support.xilinx.com and go to + either "Troubleshoot->Tech Tips->Timing & Constraints" or " + TechXclusives->Timing Closure" for tips and suggestions for meeting timing + in your design. + +Number of Timing Constraints that were not applied: 13 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- +* TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | -0.784ns| 8.784ns| 90| 18463 + PCICLK / 2 HIGH 50% PRIORITY 100 | HOLD | -0.055ns| | 1| 55 +---------------------------------------------------------------------------------------------------------- +* TS_ftop_dram0_memc_memc_u_infrastructure_ | SETUP | -0.130ns| 5.130ns| 5| 539 + clk_pll = PERIOD TIMEGRP "ftop_dr | HOLD | 0.051ns| | 0| 0 + am0_memc_memc_u_infrastructure_clk_pll" T | | | | | + S_SYS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- +* TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | SETUP | -0.049ns| 4.049ns| 8| 392 + PCICLK HIGH 50% PRIORITY 1 | HOLD | 0.000ns| | 0| 0 + | MINPERIOD | 0.000ns| 4.000ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + Pin to Pin Skew Constraint | MAXDELAY | 0.108ns| 0.450ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 | SETUP | 0.119ns| 4.881ns| 0| 0 + MHz HIGH 50% | HOLD | 0.072ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VAL | SETUP | 0.688ns| -0.188ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.637ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VAL | SETUP | 0.724ns| -0.224ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.553ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VAL | SETUP | 0.730ns| -0.230ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.549ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALI | SETUP | 0.754ns| -0.254ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.524ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VAL | SETUP | 0.783ns| -0.283ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.462ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VAL | SETUP | 0.790ns| -0.290ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.442ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VAL | SETUP | 0.844ns| -0.344ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.385ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VAL | SETUP | 0.879ns| -0.379ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.351ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VAL | SETUP | 0.884ns| -0.384ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.287ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALI | SETUP | 0.932ns| -0.432ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.263ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GT | SETUP | 1.030ns| 6.970ns| 0| 0 + X_CLK" 125 MHz HIGH 50% | HOLD | 0.063ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | MINPERIOD | 1.071ns| 1.429ns| 0| 0 + clk_mem_pll = PERIOD TIMEGRP "fto | | | | | + p_dram0_memc_memc_u_infrastructure_clk_me | | | | | + m_pll" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 M | MINPERIOD | 2.462ns| 1.538ns| 0| 0 + Hz HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP | 3.335ns| 4.665ns| 0| 0 + CLK" 125 MHz HIGH 50% | HOLD | 0.090ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD | N/A | N/A| N/A| N/A| N/A + TIMEGRP "ftop_dram0_memc_memc_cl | | | | | + k_wr_i" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.881ns| 5.130ns| 0| 5| 91995| 75760| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.130ns| N/A| 5| 0| 75760| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.392ns| 0| 99| 0| 12130285| +| TS_CLK_125 | 8.000ns| 8.784ns| N/A| 91| 0| 12110988| 0| +| TS_CLK_250 | 4.000ns| 4.049ns| N/A| 8| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 533 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 7 mins 9 secs +Total CPU time to PAR completion: 7 mins 35 secs + +Peak Memory Usage: 2246 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 104 errors found. + +Number of error messages: 0 +Number of warning messages: 556 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/ml605-20140126_1604/fpgaTop.twr b/logs/ml605-20140126_1604/fpgaTop.twr new file mode 100644 index 00000000..86258296 --- /dev/null +++ b/logs/ml605-20140126_1604/fpgaTop.twr @@ -0,0 +1,10712 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +/home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc6vlx240t,ff1156,C,-1 (PRODUCTION 1.17 2013-10-13, STEPPING level 0) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 91995 paths analyzed, 3686 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.881ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_27 (FF) + Requirement: 5.000ns + Data Path Delay: 4.932ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + ------------------------------------------------- --------------------------- + Total 4.932ns (0.723ns logic, 4.209ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_26 (FF) + Requirement: 5.000ns + Data Path Delay: 4.932ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + ------------------------------------------------- --------------------------- + Total 4.932ns (0.723ns logic, 4.209ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_25 (FF) + Requirement: 5.000ns + Data Path Delay: 4.932ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + ------------------------------------------------- --------------------------- + Total 4.932ns (0.723ns logic, 4.209ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_24 (FF) + Requirement: 5.000ns + Data Path Delay: 4.932ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + ------------------------------------------------- --------------------------- + Total 4.932ns (0.723ns logic, 4.209ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.159ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_27 (FF) + Requirement: 5.000ns + Data Path Delay: 4.892ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + ------------------------------------------------- --------------------------- + Total 4.892ns (0.683ns logic, 4.209ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.159ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_24 (FF) + Requirement: 5.000ns + Data Path Delay: 4.892ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_24 + ------------------------------------------------- --------------------------- + Total 4.892ns (0.683ns logic, 4.209ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.159ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_26 (FF) + Requirement: 5.000ns + Data Path Delay: 4.892ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_26 + ------------------------------------------------- --------------------------- + Total 4.892ns (0.683ns logic, 4.209ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.159ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_25 (FF) + Requirement: 5.000ns + Data Path Delay: 4.892ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y36.CE net (fanout=28) 1.578 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y36.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_25 + ------------------------------------------------- --------------------------- + Total 4.892ns (0.683ns logic, 4.209ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_21 (FF) + Requirement: 5.000ns + Data Path Delay: 4.814ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSpan_21 + ------------------------------------------------- --------------------------- + Total 4.814ns (0.723ns logic, 4.091ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_23 (FF) + Requirement: 5.000ns + Data Path Delay: 4.814ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSpan_23 + ------------------------------------------------- --------------------------- + Total 4.814ns (0.723ns logic, 4.091ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_20 (FF) + Requirement: 5.000ns + Data Path Delay: 4.814ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSpan_20 + ------------------------------------------------- --------------------------- + Total 4.814ns (0.723ns logic, 4.091ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_22 (FF) + Requirement: 5.000ns + Data Path Delay: 4.814ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSpan_22 + ------------------------------------------------- --------------------------- + Total 4.814ns (0.723ns logic, 4.091ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_20 (FF) + Requirement: 5.000ns + Data Path Delay: 4.774ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSamp_20 + ------------------------------------------------- --------------------------- + Total 4.774ns (0.683ns logic, 4.091ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_21 (FF) + Requirement: 5.000ns + Data Path Delay: 4.774ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSamp_21 + ------------------------------------------------- --------------------------- + Total 4.774ns (0.683ns logic, 4.091ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_22 (FF) + Requirement: 5.000ns + Data Path Delay: 4.774ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSamp_22 + ------------------------------------------------- --------------------------- + Total 4.774ns (0.683ns logic, 4.091ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_23 (FF) + Requirement: 5.000ns + Data Path Delay: 4.774ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y35.CE net (fanout=28) 1.460 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y35.CLK Tceck 0.278 ftop/ctop/inf/cp/timeServ_refFreeSpan<23> + ftop/ctop/inf/cp/timeServ_refFreeSamp_23 + ------------------------------------------------- --------------------------- + Total 4.774ns (0.683ns logic, 4.091ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.359ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_16 (FF) + Requirement: 5.000ns + Data Path Delay: 4.692ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y34.CE net (fanout=28) 1.338 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y34.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<19> + ftop/ctop/inf/cp/timeServ_refFreeSpan_16 + ------------------------------------------------- --------------------------- + Total 4.692ns (0.723ns logic, 3.969ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.359ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_19 (FF) + Requirement: 5.000ns + Data Path Delay: 4.692ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y34.CE net (fanout=28) 1.338 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y34.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<19> + ftop/ctop/inf/cp/timeServ_refFreeSpan_19 + ------------------------------------------------- --------------------------- + Total 4.692ns (0.723ns logic, 3.969ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.359ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_17 (FF) + Requirement: 5.000ns + Data Path Delay: 4.692ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y34.CE net (fanout=28) 1.338 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y34.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<19> + ftop/ctop/inf/cp/timeServ_refFreeSpan_17 + ------------------------------------------------- --------------------------- + Total 4.692ns (0.723ns logic, 3.969ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.359ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_18 (FF) + Requirement: 5.000ns + Data Path Delay: 4.692ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.629 - 1.543) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 to ftop/ctop/inf/cp/timeServ_refFreeSpan_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y58.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A4 net (fanout=11) 2.631 ftop/ctop/inf/cp/timeServ_ppsExtSync_d2 + SLICE_X65Y27.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<11> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X58Y34.CE net (fanout=28) 1.338 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X58Y34.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<19> + ftop/ctop/inf/cp/timeServ_refFreeSpan_18 + ------------------------------------------------- --------------------------- + Total 4.692ns (0.723ns logic, 3.969ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_46 (FF) + Requirement: 0.000ns + Data Path Delay: 0.179ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.798 - 0.691) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 to ftop/ctop/inf/cp/timeServ_jamFracVal_46 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y40.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 + SLICE_X64Y35.CX net (fanout=1) 0.153 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<30> + SLICE_X64Y35.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_46 + ------------------------------------------------- --------------------------- + Total 0.179ns (0.026ns logic, 0.153ns route) + (14.5% logic, 85.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_45 (FF) + Requirement: 0.000ns + Data Path Delay: 0.179ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.798 - 0.691) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 to ftop/ctop/inf/cp/timeServ_jamFracVal_45 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y40.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 + SLICE_X64Y35.BX net (fanout=1) 0.153 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<29> + SLICE_X64Y35.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_45 + ------------------------------------------------- --------------------------- + Total 0.179ns (0.026ns logic, 0.153ns route) + (14.5% logic, 85.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.073ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_47 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.798 - 0.691) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 to ftop/ctop/inf/cp/timeServ_jamFracVal_47 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y40.DQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 + SLICE_X64Y35.DX net (fanout=1) 0.154 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + SLICE_X64Y35.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_47 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.026ns logic, 0.154ns route) + (14.4% logic, 85.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.073ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_44 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.798 - 0.691) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 to ftop/ctop/inf/cp/timeServ_jamFracVal_44 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y40.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 + SLICE_X64Y35.AX net (fanout=1) 0.154 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<28> + SLICE_X64Y35.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_44 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.026ns logic, 0.154ns route) + (14.4% logic, 85.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_36 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_36 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.529 - 0.494) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_36 to ftop/ctop/inf/cp/timeServ_lastSecond_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y30.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_fracSeconds<39> + ftop/ctop/inf/cp/timeServ_fracSeconds_36 + SLICE_X68Y30.AX net (fanout=6) 0.108 ftop/ctop/inf/cp/timeServ_fracSeconds<36> + SLICE_X68Y30.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_lastSecond<39> + ftop/ctop/inf/cp/timeServ_lastSecond_36 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.009ns logic, 0.108ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.083ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_34 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_34 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.528 - 0.493) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_34 to ftop/ctop/inf/cp/timeServ_lastSecond_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y29.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_fracSeconds<35> + ftop/ctop/inf/cp/timeServ_fracSeconds_34 + SLICE_X68Y29.BX net (fanout=6) 0.109 ftop/ctop/inf/cp/timeServ_fracSeconds<34> + SLICE_X68Y29.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_lastSecond<32> + ftop/ctop/inf/cp/timeServ_lastSecond_34 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.009ns logic, 0.109ns route) + (7.6% logic, 92.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.084ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.519 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_1 to ftop/ctop/inf/cp/timeServ_jamFracVal_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X75Y21.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<3> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_1 + SLICE_X73Y21.BX net (fanout=1) 0.096 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<1> + SLICE_X73Y21.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<19> + ftop/ctop/inf/cp/timeServ_jamFracVal_17 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.084ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_38 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_38 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.529 - 0.494) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_38 to ftop/ctop/inf/cp/timeServ_lastSecond_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y30.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_fracSeconds<39> + ftop/ctop/inf/cp/timeServ_fracSeconds_38 + SLICE_X68Y30.CX net (fanout=6) 0.110 ftop/ctop/inf/cp/timeServ_fracSeconds<38> + SLICE_X68Y30.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_lastSecond<39> + ftop/ctop/inf/cp/timeServ_lastSecond_38 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.009ns logic, 0.110ns route) + (7.6% logic, 92.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.084ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.519 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_3 to ftop/ctop/inf/cp/timeServ_jamFracVal_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X75Y21.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<3> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_3 + SLICE_X73Y21.DX net (fanout=1) 0.096 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<3> + SLICE_X73Y21.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<19> + ftop/ctop/inf/cp/timeServ_jamFracVal_19 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.090ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_18 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_18 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_18 to ftop/ctop/inf/itc1/now/sDataSyncIn_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y40.CQ Tcko 0.098 ftop/ctop/cpNow<19> + ftop/ctop/inf/cp/timeServ_now_18 + SLICE_X91Y40.CX net (fanout=2) 0.105 ftop/ctop/cpNow<18> + SLICE_X91Y40.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/itc1/now/sDataSyncIn<19> + ftop/ctop/inf/itc1/now/sDataSyncIn_18 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.022ns logic, 0.105ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.090ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_17 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_17 to ftop/ctop/inf/itc1/now/sDataSyncIn_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y40.BQ Tcko 0.098 ftop/ctop/cpNow<19> + ftop/ctop/inf/cp/timeServ_now_17 + SLICE_X91Y40.BX net (fanout=2) 0.105 ftop/ctop/cpNow<17> + SLICE_X91Y40.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/itc1/now/sDataSyncIn<19> + ftop/ctop/inf/itc1/now/sDataSyncIn_17 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.022ns logic, 0.105ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_2 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.519 - 0.483) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_2 to ftop/ctop/inf/itc1/now/sDataSyncIn_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y32.CQ Tcko 0.098 ftop/ctop/cpNow<3> + ftop/ctop/inf/cp/timeServ_now_2 + SLICE_X91Y32.CX net (fanout=2) 0.105 ftop/ctop/cpNow<2> + SLICE_X91Y32.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/itc1/now/sDataSyncIn<3> + ftop/ctop/inf/itc1/now/sDataSyncIn_2 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.022ns logic, 0.105ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.517 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_6 to ftop/ctop/inf/cp/timeServ_jamFracVal_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X72Y21.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_6 + SLICE_X71Y20.CX net (fanout=1) 0.102 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<6> + SLICE_X71Y20.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_22 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.022ns logic, 0.102ns route) + (17.7% logic, 82.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_4 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_20 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.517 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_4 to ftop/ctop/inf/cp/timeServ_jamFracVal_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X72Y21.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_4 + SLICE_X71Y20.AX net (fanout=1) 0.102 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + SLICE_X71Y20.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_20 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.022ns logic, 0.102ns route) + (17.7% logic, 82.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.517 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 to ftop/ctop/inf/cp/timeServ_jamFracVal_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X72Y21.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 + SLICE_X71Y20.DX net (fanout=1) 0.103 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<7> + SLICE_X71Y20.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_23 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.022ns logic, 0.103ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refSecCount_7 (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_39 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.529 - 0.493) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refSecCount_7 to ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y51.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refSecCount<7> + ftop/ctop/inf/cp/timeServ_refSecCount_7 + SLICE_X77Y51.DX net (fanout=3) 0.107 ftop/ctop/inf/cp/timeServ_refSecCount<7> + SLICE_X77Y51.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn<39> + ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_39 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.022ns logic, 0.107ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refPerCount_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsDrive (FF) + Requirement: 0.000ns + Data Path Delay: 0.104ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refPerCount_23 to ftop/ctop/inf/cp/timeServ_ppsDrive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y30.DQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_refPerCount<23> + ftop/ctop/inf/cp/timeServ_refPerCount_23 + SLICE_X53Y30.B6 net (fanout=2) 0.046 ftop/ctop/inf/cp/timeServ_refPerCount<23> + SLICE_X53Y30.CLK Tah (-Th) 0.057 ftop/ctop/inf/cp/timeServ_ppsDrive + ftop/ctop/inf/cp/timeServ_ppsDrive_D_IN34 + ftop/ctop/inf/cp/timeServ_ppsDrive + ------------------------------------------------- --------------------------- + Total 0.104ns (0.058ns logic, 0.046ns route) + (55.8% logic, 44.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refSecCount_5 (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_37 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.529 - 0.493) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refSecCount_5 to ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y51.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refSecCount<7> + ftop/ctop/inf/cp/timeServ_refSecCount_5 + SLICE_X77Y51.BX net (fanout=3) 0.107 ftop/ctop/inf/cp/timeServ_refSecCount<5> + SLICE_X77Y51.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn<39> + ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_37 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.022ns logic, 0.107ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refSecCount_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_35 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.530 - 0.494) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refSecCount_3 to ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_35 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y50.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refSecCount<3> + ftop/ctop/inf/cp/timeServ_refSecCount_3 + SLICE_X77Y50.DX net (fanout=3) 0.107 ftop/ctop/inf/cp/timeServ_refSecCount<3> + SLICE_X77Y50.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn<35> + ftop/ctop/inf/cp/timeServ_nowInCC/sDataSyncIn_35 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.022ns logic, 0.107ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.517 - 0.485) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 to ftop/ctop/inf/cp/timeServ_jamFracVal_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X72Y21.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 + SLICE_X71Y20.BX net (fanout=1) 0.103 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<5> + SLICE_X71Y20.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_21 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.022ns logic, 0.103ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Location pin: IDELAYCTRL_X1Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Location pin: IDELAYCTRL_X1Y4.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Location pin: IDELAYCTRL_X2Y1.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Location pin: IDELAYCTRL_X2Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Location pin: MMCM_ADV_X0Y6.CLKOUT0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Location pin: MMCM_ADV_X0Y6.CLKOUT2 + Clock network: ftop/dram0/memc_memc/clk_wr_i +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.571ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys0_clk_O_BUFG/I0 + Logical resource: ftop/sys0_clk_O_BUFG/I0 + Location pin: BUFGCTRL_X0Y1.I0 + Clock network: ftop/sys0_clk_O +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKIN(Finmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKFBOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Location pin: MMCM_ADV_X0Y6.CLKFBOUT + Clock network: ftop/dram0/memc_memc/u_infrastructure/clkfbout_pll +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Location pin: MMCM_ADV_X0Y6.CLKOUT1 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_pll +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg1/SR + Location pin: SLICE_X44Y32.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Location pin: SLICE_X44Y32.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dLastState/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dLastState/SR + Location pin: SLICE_X47Y32.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS_dD_OUT/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/dD_OUT_0/SR + Location pin: SLICE_X49Y34.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/dram0/memc_rst_stretch_n/reset_hold<3>/SR + Logical resource: ftop/dram0/memc_rst_stretch_n/reset_hold_4/SR + Location pin: SLICE_X49Y110.SR + Clock network: ftop/dram0/memc_rst_stretch_n/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/dram0/memc_rst_stretch_n/reset_hold<3>/SR + Logical resource: ftop/dram0/memc_rst_stretch_n/reset_hold_0/SR + Location pin: SLICE_X49Y110.SR + Clock network: ftop/dram0/memc_rst_stretch_n/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/dram0/memc_rst_stretch_n/reset_hold<3>/SR + Logical resource: ftop/dram0/memc_rst_stretch_n/reset_hold_5/SR + Location pin: SLICE_X49Y110.SR + Clock network: ftop/dram0/memc_rst_stretch_n/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/dram0/memc_rst_stretch_n/reset_hold<3>/SR + Logical resource: ftop/dram0/memc_rst_stretch_n/reset_hold_1/SR + Location pin: SLICE_X49Y110.SR + Clock network: ftop/dram0/memc_rst_stretch_n/IN_RST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.538ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% +PRIORITY 100; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 12110988 paths analyzed, 136893 endpoints analyzed, 91 failing endpoints + 91 timing errors detected. (90 setup errors, 1 hold error, 0 component switching limit errors) + Minimum period is 8.784ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.784ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.473ns (Levels of Logic = 8) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y74.CQ Tcko 0.337 ftop/ctop/inf/cp/wci_14_reqF_cntr_r + ftop/ctop/inf/cp/wci_14_reqF_cntr_r + SLICE_X56Y76.B4 net (fanout=57) 1.223 ftop/ctop/inf/cp/wci_14_reqF_cntr_r + SLICE_X56Y76.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_402 + ftop/ctop/inf/cp/NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033_REPLICA_332 + SLICE_X69Y86.A5 net (fanout=3) 1.122 ftop/ctop/inf/cp/NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033_REPLICA_332 + SLICE_X69Y86.BMUX Topab 0.395 ftop/ctop/inf/cp/cpReq<20>_REPLICA_19 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_2_f8 + SLICE_X68Y86.B4 net (fanout=1) 0.393 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 + SLICE_X68Y86.B Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<22> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F1 + SLICE_X71Y84.D1 net (fanout=7) 0.719 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.473ns (1.526ns logic, 6.947ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.768ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.457ns (Levels of Logic = 10) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<22> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X70Y76.C1 net (fanout=175) 0.889 ftop/ctop/inf/cp/cpReq<21> + SLICE_X70Y76.C Tilo 0.068 ftop/ctop/inf/cp/wci_14_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819021 + SLICE_X72Y76.B4 net (fanout=100) 0.466 ftop/ctop/inf/cp/_theResult_____1__h78190<1> + SLICE_X72Y76.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.457ns (1.656ns logic, 6.801ns route) + (19.6% logic, 80.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.767ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_3_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.457ns (Levels of Logic = 10) + Clock Path Skew: -0.241ns (1.515 - 1.756) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_3_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y74.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_3_busy + ftop/ctop/inf/cp/wci_3_busy + SLICE_X69Y76.A5 net (fanout=41) 0.465 ftop/ctop/inf/cp/wci_3_busy + SLICE_X69Y76.A Tilo 0.068 ftop/ctop/inf/cp/wci_10_pageWindow<11> + ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o1 + SLICE_X72Y76.D2 net (fanout=2) 0.871 ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o + SLICE_X72Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.457ns (1.675ns logic, 6.782ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.760ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_2_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.452ns (Levels of Logic = 9) + Clock Path Skew: -0.239ns (1.515 - 1.754) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_2_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X68Y75.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_2_busy + ftop/ctop/inf/cp/wci_2_busy + SLICE_X58Y78.D5 net (fanout=41) 1.000 ftop/ctop/inf/cp/wci_2_busy + SLICE_X58Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_reqF_q_0<69> + ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.D3 net (fanout=3) 1.259 ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.452ns (1.651ns logic, 6.801ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.753ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_9_wReset_n (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.446ns (Levels of Logic = 9) + Clock Path Skew: -0.238ns (1.515 - 1.753) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_9_wReset_n to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y73.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_9_wReset_n + ftop/ctop/inf/cp/wci_9_wReset_n + SLICE_X56Y75.D3 net (fanout=32) 1.121 ftop/ctop/inf/cp/wci_9_wReset_n + SLICE_X56Y75.D Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + SLICE_X70Y86.B6 net (fanout=3) 1.195 ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + SLICE_X70Y86.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.446ns (1.588ns logic, 6.858ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.751ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_6_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.440ns (Levels of Logic = 8) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_6_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y76.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_6_busy + ftop/ctop/inf/cp/wci_6_busy + SLICE_X59Y80.D4 net (fanout=33) 1.111 ftop/ctop/inf/cp/wci_6_busy + SLICE_X59Y80.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_respF_D_OUT<30> + ftop/ctop/inf/cp/NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985_REPLICA_195 + SLICE_X69Y86.C2 net (fanout=4) 1.184 ftop/ctop/inf/cp/NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985_REPLICA_195 + SLICE_X69Y86.BMUX Topcb 0.412 ftop/ctop/inf/cp/cpReq<20>_REPLICA_19 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f72 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_2_f8 + SLICE_X68Y86.B4 net (fanout=1) 0.393 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 + SLICE_X68Y86.B Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<22> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F1 + SLICE_X71Y84.D1 net (fanout=7) 0.719 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.440ns (1.543ns logic, 6.897ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.743ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.432ns (Levels of Logic = 10) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<22> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X70Y76.C1 net (fanout=175) 0.889 ftop/ctop/inf/cp/cpReq<21> + SLICE_X70Y76.C Tilo 0.068 ftop/ctop/inf/cp/wci_14_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819021 + SLICE_X72Y76.C6 net (fanout=100) 0.418 ftop/ctop/inf/cp/_theResult_____1__h78190<1> + SLICE_X72Y76.BMUX Topcb 0.412 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_51 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.432ns (1.679ns logic, 6.753ns route) + (19.9% logic, 80.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.741ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_5_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.431ns (Levels of Logic = 8) + Clock Path Skew: -0.241ns (1.515 - 1.756) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_5_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X77Y73.CQ Tcko 0.337 ftop/ctop/inf/cp/wci_5_busy + ftop/ctop/inf/cp/wci_5_busy + SLICE_X61Y77.C2 net (fanout=31) 1.310 ftop/ctop/inf/cp/wci_5_busy + SLICE_X61Y77.C Tilo 0.068 flash_addr_22_OBUF + ftop/ctop/inf/cp/NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979_REPLICA_176 + SLICE_X69Y86.C5 net (fanout=5) 0.976 ftop/ctop/inf/cp/NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979_REPLICA_176 + SLICE_X69Y86.BMUX Topcb 0.412 ftop/ctop/inf/cp/cpReq<20>_REPLICA_19 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f72 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_2_f8 + SLICE_X68Y86.B4 net (fanout=1) 0.393 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 + SLICE_X68Y86.B Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<22> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F1 + SLICE_X71Y84.D1 net (fanout=7) 0.719 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.431ns (1.543ns logic, 6.888ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.740ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.433ns (Levels of Logic = 8) + Clock Path Skew: -0.238ns (1.519 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y74.CQ Tcko 0.337 ftop/ctop/inf/cp/wci_14_reqF_cntr_r + ftop/ctop/inf/cp/wci_14_reqF_cntr_r + SLICE_X56Y76.B4 net (fanout=57) 1.223 ftop/ctop/inf/cp/wci_14_reqF_cntr_r + SLICE_X56Y76.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_402 + ftop/ctop/inf/cp/NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033_REPLICA_332 + SLICE_X69Y86.A5 net (fanout=3) 1.122 ftop/ctop/inf/cp/NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033_REPLICA_332 + SLICE_X69Y86.BMUX Topab 0.395 ftop/ctop/inf/cp/cpReq<20>_REPLICA_19 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_2_f8 + SLICE_X68Y86.B4 net (fanout=1) 0.393 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 + SLICE_X68Y86.B Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<22> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F1 + SLICE_X71Y84.D1 net (fanout=7) 0.719 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.433ns (1.526ns logic, 6.907ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.739ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_8_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.433ns (Levels of Logic = 9) + Clock Path Skew: -0.237ns (1.515 - 1.752) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_8_respF/empty_reg to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y75.BQ Tcko 0.337 ftop/ctop/inf/cp/wci_8_respF_EMPTY_N + ftop/ctop/inf/cp/wci_8_respF/empty_reg + SLICE_X57Y75.B3 net (fanout=39) 1.006 ftop/ctop/inf/cp/wci_8_respF_EMPTY_N + SLICE_X57Y75.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_375 + ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_406 + SLICE_X70Y86.B4 net (fanout=3) 1.297 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_406 + SLICE_X70Y86.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.433ns (1.588ns logic, 6.845ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.729ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_2_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.423ns (Levels of Logic = 9) + Clock Path Skew: -0.237ns (1.515 - 1.752) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_2_respF/empty_reg to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y74.BQ Tcko 0.381 ftop/ctop/inf/cp/wci_2_respF_EMPTY_N + ftop/ctop/inf/cp/wci_2_respF/empty_reg + SLICE_X58Y78.D3 net (fanout=42) 0.971 ftop/ctop/inf/cp/wci_2_respF_EMPTY_N + SLICE_X58Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_reqF_q_0<69> + ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.D3 net (fanout=3) 1.259 ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.423ns (1.651ns logic, 6.772ns route) + (19.6% logic, 80.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.728ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_3_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.421ns (Levels of Logic = 10) + Clock Path Skew: -0.238ns (1.515 - 1.753) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_3_respF/empty_reg to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y72.BQ Tcko 0.337 ftop/ctop/inf/cp/wci_3_respF_EMPTY_N + ftop/ctop/inf/cp/wci_3_respF/empty_reg + SLICE_X69Y76.A6 net (fanout=42) 0.429 ftop/ctop/inf/cp/wci_3_respF_EMPTY_N + SLICE_X69Y76.A Tilo 0.068 ftop/ctop/inf/cp/wci_10_pageWindow<11> + ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o1 + SLICE_X72Y76.D2 net (fanout=2) 0.871 ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o + SLICE_X72Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.421ns (1.675ns logic, 6.746ns route) + (19.9% logic, 80.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.727ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_8_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.420ns (Levels of Logic = 8) + Clock Path Skew: -0.238ns (1.515 - 1.753) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_8_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y73.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_8_reqF_cntr_r + ftop/ctop/inf/cp/wci_8_reqF_cntr_r + SLICE_X56Y76.D3 net (fanout=63) 1.136 ftop/ctop/inf/cp/wci_8_reqF_cntr_r + SLICE_X56Y76.D Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_402 + ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_402 + SLICE_X75Y77.B5 net (fanout=4) 0.974 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_402 + SLICE_X75Y77.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536_2_f8 + SLICE_X71Y89.D6 net (fanout=2) 0.804 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 + SLICE_X71Y89.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_reqF_q_0<69> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T1 + SLICE_X71Y84.D5 net (fanout=52) 0.496 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.420ns (1.520ns logic, 6.900ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.724ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.417ns (Levels of Logic = 10) + Clock Path Skew: -0.238ns (1.519 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<22> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X70Y76.C1 net (fanout=175) 0.889 ftop/ctop/inf/cp/cpReq<21> + SLICE_X70Y76.C Tilo 0.068 ftop/ctop/inf/cp/wci_14_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819021 + SLICE_X72Y76.B4 net (fanout=100) 0.466 ftop/ctop/inf/cp/_theResult_____1__h78190<1> + SLICE_X72Y76.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.417ns (1.656ns logic, 6.761ns route) + (19.7% logic, 80.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.723ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_3_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.417ns (Levels of Logic = 10) + Clock Path Skew: -0.237ns (1.519 - 1.756) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_3_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y74.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_3_busy + ftop/ctop/inf/cp/wci_3_busy + SLICE_X69Y76.A5 net (fanout=41) 0.465 ftop/ctop/inf/cp/wci_3_busy + SLICE_X69Y76.A Tilo 0.068 ftop/ctop/inf/cp/wci_10_pageWindow<11> + ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o1 + SLICE_X72Y76.D2 net (fanout=2) 0.871 ftop/ctop/inf/cp/wci_3_busy_wci_3_respF_FULL_N_AND_4275_o + SLICE_X72Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.417ns (1.675ns logic, 6.742ns route) + (19.9% logic, 80.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.716ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_2_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.412ns (Levels of Logic = 9) + Clock Path Skew: -0.235ns (1.519 - 1.754) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_2_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X68Y75.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_2_busy + ftop/ctop/inf/cp/wci_2_busy + SLICE_X58Y78.D5 net (fanout=41) 1.000 ftop/ctop/inf/cp/wci_2_busy + SLICE_X58Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_reqF_q_0<69> + ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.D3 net (fanout=3) 1.259 ftop/ctop/inf/cp/NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961_REPLICA_250 + SLICE_X70Y86.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.412ns (1.651ns logic, 6.761ns route) + (19.6% logic, 80.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.709ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_9_wReset_n (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.406ns (Levels of Logic = 9) + Clock Path Skew: -0.234ns (1.519 - 1.753) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_9_wReset_n to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y73.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_9_wReset_n + ftop/ctop/inf/cp/wci_9_wReset_n + SLICE_X56Y75.D3 net (fanout=32) 1.121 ftop/ctop/inf/cp/wci_9_wReset_n + SLICE_X56Y75.D Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + SLICE_X70Y86.B6 net (fanout=3) 1.195 ftop/ctop/inf/cp/NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003_REPLICA_387 + SLICE_X70Y86.BMUX Topbb 0.389 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802_2_f8 + SLICE_X70Y83.C6 net (fanout=2) 0.370 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 + SLICE_X70Y83.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F1 + SLICE_X71Y81.D2 net (fanout=6) 0.739 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + SLICE_X71Y81.D Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C3 net (fanout=1) 0.481 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead15 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.406ns (1.588ns logic, 6.818ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.707ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_6_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.400ns (Levels of Logic = 8) + Clock Path Skew: -0.238ns (1.519 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_6_busy to ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y76.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_6_busy + ftop/ctop/inf/cp/wci_6_busy + SLICE_X59Y80.D4 net (fanout=33) 1.111 ftop/ctop/inf/cp/wci_6_busy + SLICE_X59Y80.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_respF_D_OUT<30> + ftop/ctop/inf/cp/NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985_REPLICA_195 + SLICE_X69Y86.C2 net (fanout=4) 1.184 ftop/ctop/inf/cp/NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985_REPLICA_195 + SLICE_X69Y86.BMUX Topcb 0.412 ftop/ctop/inf/cp/cpReq<20>_REPLICA_19 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f72 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547_2_f8 + SLICE_X68Y86.B4 net (fanout=1) 0.393 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 + SLICE_X68Y86.B Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<22> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F1 + SLICE_X71Y84.D1 net (fanout=7) 0.719 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F + SLICE_X71Y84.D Tilo 0.068 ftop/ctop/inf/cp/wci_12_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D5 net (fanout=1) 0.764 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite23 + SLICE_X63Y80.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C4 net (fanout=1) 0.651 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite24 + SLICE_X65Y81.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_8 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite30 + SLICE_X83Y78.D5 net (fanout=18) 0.838 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X63Y83.CE net (fanout=35) 1.082 ftop/ctop/inf/cp/cpReq_EN + SLICE_X63Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18 + ------------------------------------------------- --------------------------- + Total 8.400ns (1.543ns logic, 6.857ns route) + (18.4% logic, 81.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.706ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_25 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.395ns (Levels of Logic = 11) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_25 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y78.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<22> + ftop/ctop/inf/cp/cpReq_25 + SLICE_X76Y79.D5 net (fanout=26) 0.493 ftop/ctop/inf/cp/cpReq<25> + SLICE_X76Y79.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_380_BITS_27_TO_4_466_ULT_0x100___d24672111 + SLICE_X72Y75.D4 net (fanout=6) 0.585 ftop/ctop/inf/cp/cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467211 + SLICE_X72Y75.D Tilo 0.068 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X72Y76.BX net (fanout=32) 0.300 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X72Y76.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.395ns (1.571ns logic, 6.824ns route) + (18.7% logic, 81.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.706ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 (FF) + Requirement: 8.000ns + Data Path Delay: 8.395ns (Levels of Logic = 10) + Clock Path Skew: -0.242ns (1.515 - 1.757) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<22> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X70Y76.C1 net (fanout=175) 0.889 ftop/ctop/inf/cp/cpReq<21> + SLICE_X70Y76.C Tilo 0.068 ftop/ctop/inf/cp/wci_14_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819021 + SLICE_X72Y76.D5 net (fanout=100) 0.385 ftop/ctop/inf/cp/_theResult_____1__h78190<1> + SLICE_X72Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X62Y82.C6 net (fanout=16) 0.871 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X62Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T1 + ftop/ctop/inf/cp/_n13773<34>21 + SLICE_X64Y85.C6 net (fanout=75) 0.732 ftop/ctop/inf/cp/_n13773<34>2 + SLICE_X64Y85.C Tilo 0.068 ftop/ctop/inf/cp/N134 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T1 + SLICE_X66Y82.D2 net (fanout=12) 0.770 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + SLICE_X66Y82.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C6 net (fanout=1) 0.121 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + SLICE_X66Y82.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17_SW0 + SLICE_X66Y83.D5 net (fanout=1) 0.442 ftop/ctop/inf/cp/N464 + SLICE_X66Y83.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30_SW0 + SLICE_X66Y83.C2 net (fanout=1) 0.470 ftop/ctop/inf/cp/N478 + SLICE_X66Y83.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<20>_REPLICA_16 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X83Y78.D6 net (fanout=20) 0.803 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X83Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/wci_0_respF_DEQ11 + SLICE_X83Y78.C6 net (fanout=2) 0.115 ftop/ctop/inf/cp/wci_0_respF_DEQ1 + SLICE_X83Y78.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/cpReq_EN3 + SLICE_X61Y82.CE net (fanout=35) 1.122 ftop/ctop/inf/cp/cpReq_EN + SLICE_X61Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11 + ------------------------------------------------- --------------------------- + Total 8.395ns (1.675ns logic, 6.720ns route) + (20.0% logic, 80.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack (hold path): -0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pAF_head_wrapped (FF) + Destination: ftop/pciw_i2pAF_tail_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.212ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.153 - 1.075) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pAF_head_wrapped to ftop/pciw_i2pAF_tail_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y130.AQ Tcko 0.098 ftop/pciw_i2pAF_head_wrapped + ftop/pciw_i2pAF_head_wrapped + SLICE_X135Y124.A6 net (fanout=7) 0.169 ftop/pciw_i2pAF_head_wrapped + SLICE_X135Y124.CLK Tah (-Th) 0.055 ftop/pciw_i2pAF_tail_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_enq_update_tail11 + ftop/pciw_i2pAF_tail_wrapped + ------------------------------------------------- --------------------------- + Total 0.212ns (0.043ns logic, 0.169ns route) + (20.3% logic, 79.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_67 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_67_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.262ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.170 - 1.097) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_67 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_67_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X160Y152.DQ Tcko 0.098 ftop/pciw_p2iS<67> + ftop/pciw_p2iS_67 + SLICE_X152Y152.DX net (fanout=1) 0.202 ftop/pciw_p2iS<67> + SLICE_X152Y152.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<67> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_67_0 + ------------------------------------------------- --------------------------- + Total 0.262ns (0.060ns logic, 0.202ns route) + (22.9% logic, 77.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_12 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_12_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.272ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (1.173 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_12 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_12_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y154.AQ Tcko 0.098 ftop/pciw_p2iS<15> + ftop/pciw_p2iS_12 + SLICE_X158Y159.AX net (fanout=1) 0.210 ftop/pciw_p2iS<12> + SLICE_X158Y159.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<15> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_12_0 + ------------------------------------------------- --------------------------- + Total 0.272ns (0.062ns logic, 0.210ns route) + (22.8% logic, 77.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_65 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_65_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.170 - 1.097) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_65 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_65_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X160Y152.BQ Tcko 0.098 ftop/pciw_p2iS<67> + ftop/pciw_p2iS_65 + SLICE_X152Y152.BX net (fanout=1) 0.197 ftop/pciw_p2iS<65> + SLICE_X152Y152.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<67> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_65_0 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.071ns logic, 0.197ns route) + (26.5% logic, 73.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.008ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_7 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_7_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.328ns (Levels of Logic = 0) + Clock Path Skew: 0.131ns (1.227 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_7 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_7_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X157Y158.DQ Tcko 0.098 ftop/pciw_p2iS<7> + ftop/pciw_p2iS_7 + SLICE_X158Y169.DX net (fanout=1) 0.268 ftop/pciw_p2iS<7> + SLICE_X158Y169.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<7> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_7_0 + ------------------------------------------------- --------------------------- + Total 0.328ns (0.060ns logic, 0.268ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.013ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_69 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_69_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.276ns (Levels of Logic = 0) + Clock Path Skew: 0.074ns (1.171 - 1.097) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_69 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_69_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X160Y153.BQ Tcko 0.098 ftop/pciw_p2iS<71> + ftop/pciw_p2iS_69 + SLICE_X152Y153.BX net (fanout=1) 0.205 ftop/pciw_p2iS<69> + SLICE_X152Y153.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<71> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_69_0 + ------------------------------------------------- --------------------------- + Total 0.276ns (0.071ns logic, 0.205ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_13 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_13 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.066ns (1.143 - 1.077) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_13 to ftop/pciw_pciDevice/dD_OUT_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X138Y135.BMUX Tshcko 0.148 ftop/pciw_pciDevice/sDataSyncIn<11> + ftop/pciw_pciDevice/sDataSyncIn_13 + SLICE_X135Y136.BX net (fanout=1) 0.198 ftop/pciw_pciDevice/sDataSyncIn<13> + SLICE_X135Y136.CLK Tckdi (-Th) 0.076 ftop/pciw_pciDevice_dD_OUT<15> + ftop/pciw_pciDevice/dD_OUT_13 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.072ns logic, 0.198ns route) + (26.7% logic, 73.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_57 (FF) + Destination: ftop/ctop/inf/dp1/dmaStartTime_57 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.751 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_57 to ftop/ctop/inf/dp1/dmaStartTime_57 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.BQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_57 + SLICE_X126Y39.BX net (fanout=3) 0.097 ftop/ctop/inf/dp1/wti_nowReq<57> + SLICE_X126Y39.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/dp1/dmaStartTime<59> + ftop/ctop/inf/dp1/dmaStartTime_57 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.026ns logic, 0.097ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_59 (FF) + Destination: ftop/ctop/inf/dp1/dmaStartTime_59 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.751 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_59 to ftop/ctop/inf/dp1/dmaStartTime_59 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.DQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_59 + SLICE_X126Y39.DX net (fanout=3) 0.098 ftop/ctop/inf/dp1/wti_nowReq<59> + SLICE_X126Y39.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/dp1/dmaStartTime<59> + ftop/ctop/inf/dp1/dmaStartTime_59 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_56 (FF) + Destination: ftop/ctop/inf/dp1/dmaStartTime_56 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.751 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_56 to ftop/ctop/inf/dp1/dmaStartTime_56 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.AQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_56 + SLICE_X126Y39.AX net (fanout=3) 0.098 ftop/ctop/inf/dp1/wti_nowReq<56> + SLICE_X126Y39.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/dp1/dmaStartTime<59> + ftop/ctop/inf/dp1/dmaStartTime_56 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_58 (FF) + Destination: ftop/ctop/inf/dp1/dmaStartTime_58 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.751 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_58 to ftop/ctop/inf/dp1/dmaStartTime_58 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.CQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_58 + SLICE_X126Y39.CX net (fanout=3) 0.099 ftop/ctop/inf/dp1/wti_nowReq<58> + SLICE_X126Y39.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/dp1/dmaStartTime<59> + ftop/ctop/inf/dp1/dmaStartTime_58 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.026ns logic, 0.099ns route) + (20.8% logic, 79.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/app/appW2/wsiM_reqFifo_q_1_105 (FF) + Destination: ftop/ctop/app/appW2/wsiM_reqFifo_q_0_105 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.765 - 0.658) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/app/appW2/wsiM_reqFifo_q_1_105 to ftop/ctop/app/appW2/wsiM_reqFifo_q_0_105 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y80.DQ Tcko 0.098 ftop/ctop/app/appW2/wsiM_reqFifo_q_1<105> + ftop/ctop/app/appW2/wsiM_reqFifo_q_1_105 + SLICE_X11Y79.C6 net (fanout=1) 0.082 ftop/ctop/app/appW2/wsiM_reqFifo_q_1<105> + SLICE_X11Y79.CLK Tah (-Th) 0.056 ftop/ctop/app/appW2_wsiM0_MData<82> + ftop/ctop/app/appW2/wsiM_reqFifo_q_0_D_IN<105> + ftop/ctop/app/appW2/wsiM_reqFifo_q_0_105 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.042ns logic, 0.082ns route) + (33.9% logic, 66.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_5 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_5_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.339ns (Levels of Logic = 0) + Clock Path Skew: 0.131ns (1.227 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_5 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_5_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X157Y158.BQ Tcko 0.098 ftop/pciw_p2iS<7> + ftop/pciw_p2iS_5 + SLICE_X158Y169.BX net (fanout=1) 0.268 ftop/pciw_p2iS<5> + SLICE_X158Y169.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<7> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_5_0 + ------------------------------------------------- --------------------------- + Total 0.339ns (0.071ns logic, 0.268ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_49 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_49_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.284ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.173 - 1.097) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_49 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_49_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X159Y156.BQ Tcko 0.098 ftop/pciw_p2iS<51> + ftop/pciw_p2iS_49 + SLICE_X158Y156.BX net (fanout=1) 0.213 ftop/pciw_p2iS<49> + SLICE_X158Y156.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<51> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_49_0 + ------------------------------------------------- --------------------------- + Total 0.284ns (0.071ns logic, 0.213ns route) + (25.0% logic, 75.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_29 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_29_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.284ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.172 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_29 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_29_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X159Y155.BQ Tcko 0.098 ftop/pciw_p2iS<31> + ftop/pciw_p2iS_29 + SLICE_X158Y155.BX net (fanout=1) 0.213 ftop/pciw_p2iS<29> + SLICE_X158Y155.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<31> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_29_0 + ------------------------------------------------- --------------------------- + Total 0.284ns (0.071ns logic, 0.213ns route) + (25.0% logic, 75.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iAF_tail_wrapped (FF) + Destination: ftop/pciw_p2iAF_head_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (1.162 - 1.092) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iAF_tail_wrapped to ftop/pciw_p2iAF_head_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y150.AQ Tcko 0.115 ftop/pciw_p2iAF_tail_wrapped + ftop/pciw_p2iAF_tail_wrapped + SLICE_X153Y144.A6 net (fanout=7) 0.219 ftop/pciw_p2iAF_tail_wrapped + SLICE_X153Y144.CLK Tah (-Th) 0.055 ftop/pciw_p2iAF_head_wrapped + ftop/WILL_FIRE_RL_pciw_p2iAF_deq_update_head11 + ftop/pciw_p2iAF_head_wrapped + ------------------------------------------------- --------------------------- + Total 0.279ns (0.060ns logic, 0.219ns route) + (21.5% logic, 78.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.040ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_57 (FF) + Destination: ftop/ctop/inf/dp1/dmaDoneTime_57 (FF) + Requirement: 0.000ns + Data Path Delay: 0.146ns (Levels of Logic = 0) + Clock Path Skew: 0.106ns (0.749 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_57 to ftop/ctop/inf/dp1/dmaDoneTime_57 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.BQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_57 + SLICE_X129Y39.BX net (fanout=3) 0.107 ftop/ctop/inf/dp1/wti_nowReq<57> + SLICE_X129Y39.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/dp1/dmaDoneTime<59> + ftop/ctop/inf/dp1/dmaDoneTime_57 + ------------------------------------------------- --------------------------- + Total 0.146ns (0.039ns logic, 0.107ns route) + (26.7% logic, 73.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.041ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_59 (FF) + Destination: ftop/ctop/inf/dp1/dmaDoneTime_59 (FF) + Requirement: 0.000ns + Data Path Delay: 0.147ns (Levels of Logic = 0) + Clock Path Skew: 0.106ns (0.749 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_59 to ftop/ctop/inf/dp1/dmaDoneTime_59 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.DQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_59 + SLICE_X129Y39.DX net (fanout=3) 0.108 ftop/ctop/inf/dp1/wti_nowReq<59> + SLICE_X129Y39.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/dp1/dmaDoneTime<59> + ftop/ctop/inf/dp1/dmaDoneTime_59 + ------------------------------------------------- --------------------------- + Total 0.147ns (0.039ns logic, 0.108ns route) + (26.5% logic, 73.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.041ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/wti_nowReq_56 (FF) + Destination: ftop/ctop/inf/dp1/dmaDoneTime_56 (FF) + Requirement: 0.000ns + Data Path Delay: 0.147ns (Levels of Logic = 0) + Clock Path Skew: 0.106ns (0.749 - 0.643) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/wti_nowReq_56 to ftop/ctop/inf/dp1/dmaDoneTime_56 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y40.AQ Tcko 0.115 ftop/ctop/inf/dp1/wti_nowReq<59> + ftop/ctop/inf/dp1/wti_nowReq_56 + SLICE_X129Y39.AX net (fanout=3) 0.108 ftop/ctop/inf/dp1/wti_nowReq<56> + SLICE_X129Y39.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/dp1/dmaDoneTime<59> + ftop/ctop/inf/dp1/dmaDoneTime_56 + ------------------------------------------------- --------------------------- + Total 0.147ns (0.039ns logic, 0.108ns route) + (26.5% logic, 73.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.044ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_14 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_14_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.311ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (1.173 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_14 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_14_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y154.CQ Tcko 0.098 ftop/pciw_p2iS<15> + ftop/pciw_p2iS_14 + SLICE_X158Y159.CX net (fanout=1) 0.243 ftop/pciw_p2iS<14> + SLICE_X158Y159.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<15> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_55_o_dat[15][152]_wide_mux_5_OUT_14_0 + ------------------------------------------------- --------------------------- + Total 0.311ns (0.068ns logic, 0.243ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Location pin: GTXE1_X0Y15.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Location pin: GTXE1_X0Y14.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Location pin: GTXE1_X0Y13.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Location pin: GTXE1_X0Y12.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% +PRIORITY 1; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 19297 paths analyzed, 6214 endpoints analyzed, 8 failing endpoints + 8 timing errors detected. (8 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.049ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMD + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMC + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMB + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Skew: -0.135ns (0.955 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X134Y127.CE net (fanout=13) 0.671 ftop/pciw_fI2P/BUS_0003 + SLICE_X134Y127.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMA + ------------------------------------------------- --------------------------- + Total 3.851ns (1.108ns logic, 2.743ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMA + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMB + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMC + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr10_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 3.742ns (Levels of Logic = 2) + Clock Path Skew: -0.167ns (0.923 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr10_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X130Y139.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X130Y139.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<59> + ftop/pciw_fI2P/Mram_arr10_RAMD + ------------------------------------------------- --------------------------- + Total 3.742ns (1.108ns logic, 2.634ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.753ns (Levels of Logic = 2) + Clock Path Skew: -0.155ns (0.935 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y130.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y130.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA + ------------------------------------------------- --------------------------- + Total 3.753ns (1.108ns logic, 2.645ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.753ns (Levels of Logic = 2) + Clock Path Skew: -0.155ns (0.935 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y130.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y130.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 3.753ns (1.108ns logic, 2.645ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.753ns (Levels of Logic = 2) + Clock Path Skew: -0.155ns (0.935 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y130.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y130.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 3.753ns (1.108ns logic, 2.645ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 3.753ns (Levels of Logic = 2) + Clock Path Skew: -0.155ns (0.935 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X135Y132.A6 net (fanout=69) 1.515 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X135Y132.A Tilo 0.068 ftop/pciw_pciDevice_dD_OUT<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X130Y133.D5 net (fanout=93) 0.557 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X130Y133.D Tilo 0.068 ftop/ctop/inf/dp0/tlp_lastMetaV_3<15> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y130.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y130.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB + ------------------------------------------------- --------------------------- + Total 3.753ns (1.108ns logic, 2.645ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_62 (FF) + Requirement: 0.000ns + Data Path Delay: 0.265ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.146 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_62 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X126Y120.C2 net (fanout=80) 0.243 ftop/pciw_i2pS<134> + SLICE_X126Y120.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN591 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_62 + ------------------------------------------------- --------------------------- + Total 0.265ns (0.022ns logic, 0.243ns route) + (8.3% logic, 91.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 (FF) + Requirement: 0.000ns + Data Path Delay: 0.267ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.146 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X126Y120.B2 net (fanout=80) 0.246 ftop/pciw_i2pS<134> + SLICE_X126Y120.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN581 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 + ------------------------------------------------- --------------------------- + Total 0.267ns (0.021ns logic, 0.246ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_56 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_56 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X131Y119.A6 net (fanout=79) 0.227 ftop/pciw_i2pS<135> + SLICE_X131Y119.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN521 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_56 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.043ns logic, 0.227ns route) + (15.9% logic, 84.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X130Y118.C5 net (fanout=79) 0.248 ftop/pciw_i2pS<135> + SLICE_X130Y118.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN671 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.022ns logic, 0.248ns route) + (8.1% logic, 91.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.007ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X131Y119.D6 net (fanout=79) 0.230 ftop/pciw_i2pS<135> + SLICE_X131Y119.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN551 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.041ns logic, 0.230ns route) + (15.1% logic, 84.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.007ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X130Y118.B5 net (fanout=79) 0.250 ftop/pciw_i2pS<135> + SLICE_X130Y118.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN561 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.021ns logic, 0.250ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.007ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 (FF) + Requirement: 0.000ns + Data Path Delay: 0.272ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.146 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X126Y120.D2 net (fanout=79) 0.251 ftop/pciw_i2pS<135> + SLICE_X126Y120.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN601 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 + ------------------------------------------------- --------------------------- + Total 0.272ns (0.021ns logic, 0.251ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.008ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.273ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.146 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X127Y116.B6 net (fanout=79) 0.232 ftop/pciw_i2pS<135> + SLICE_X127Y116.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<23> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN141 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 + ------------------------------------------------- --------------------------- + Total 0.273ns (0.041ns logic, 0.232ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.009ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_59 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 (FF) + Requirement: 0.000ns + Data Path Delay: 0.277ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.145 - 1.066) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_59 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y115.DQ Tcko 0.115 ftop/pciw_i2pS<59> + ftop/pciw_i2pS_59 + SLICE_X131Y119.D3 net (fanout=1) 0.219 ftop/pciw_i2pS<59> + SLICE_X131Y119.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN551 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + ------------------------------------------------- --------------------------- + Total 0.277ns (0.058ns logic, 0.219ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.009ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_60 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.146 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_60 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X126Y120.A1 net (fanout=79) 0.252 ftop/pciw_i2pS<135> + SLICE_X126Y120.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN571 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_60 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.022ns logic, 0.252ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.009ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pAF_tail_wrapped (FF) + Destination: ftop/pciw_i2pAF_head_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (1.150 - 1.077) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pAF_tail_wrapped to ftop/pciw_i2pAF_head_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y124.AQ Tcko 0.098 ftop/pciw_i2pAF_tail_wrapped + ftop/pciw_i2pAF_tail_wrapped + SLICE_X135Y130.A5 net (fanout=7) 0.228 ftop/pciw_i2pAF_tail_wrapped + SLICE_X135Y130.CLK Tah (-Th) 0.055 ftop/pciw_i2pAF_head_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_deq_update_head1 + ftop/pciw_i2pAF_head_wrapped + ------------------------------------------------- --------------------------- + Total 0.271ns (0.043ns logic, 0.228ns route) + (15.9% logic, 84.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_57 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_57 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.145 - 1.066) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_57 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_57 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y115.BQ Tcko 0.115 ftop/pciw_i2pS<59> + ftop/pciw_i2pS_57 + SLICE_X131Y119.B3 net (fanout=1) 0.220 ftop/pciw_i2pS<57> + SLICE_X131Y119.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN531 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_57 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.058ns logic, 0.220ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X130Y119.A5 net (fanout=79) 0.256 ftop/pciw_i2pS<135> + SLICE_X130Y119.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN82 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.022ns logic, 0.256ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X130Y118.A5 net (fanout=80) 0.256 ftop/pciw_i2pS<134> + SLICE_X130Y118.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN451 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.022ns logic, 0.256ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_66 (FF) + Requirement: 0.000ns + Data Path Delay: 0.280ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_66 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X130Y122.C6 net (fanout=79) 0.258 ftop/pciw_i2pS<135> + SLICE_X130Y122.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<67> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN631 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_66 + ------------------------------------------------- --------------------------- + Total 0.280ns (0.022ns logic, 0.258ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_21 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 1) + Clock Path Skew: 0.068ns (1.146 - 1.078) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_21 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X116Y115.BQ Tcko 0.115 ftop/pciw_i2pS<23> + ftop/pciw_i2pS_21 + SLICE_X127Y116.B4 net (fanout=1) 0.216 ftop/pciw_i2pS<21> + SLICE_X127Y116.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<23> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN141 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_21 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.058ns logic, 0.216ns route) + (21.2% logic, 78.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.281ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X130Y119.D5 net (fanout=79) 0.260 ftop/pciw_i2pS<135> + SLICE_X130Y119.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN111 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 + ------------------------------------------------- --------------------------- + Total 0.281ns (0.021ns logic, 0.260ns route) + (7.5% logic, 92.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.281ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X130Y118.D5 net (fanout=80) 0.260 ftop/pciw_i2pS<134> + SLICE_X130Y118.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN781 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 + ------------------------------------------------- --------------------------- + Total 0.281ns (0.021ns logic, 0.260ns route) + (7.5% logic, 92.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_38 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 (FF) + Requirement: 0.000ns + Data Path Delay: 0.289ns (Levels of Logic = 1) + Clock Path Skew: 0.077ns (1.145 - 1.068) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_38 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y111.CQ Tcko 0.115 ftop/pciw_i2pS<39> + ftop/pciw_i2pS_38 + SLICE_X127Y115.C4 net (fanout=1) 0.230 ftop/pciw_i2pS<38> + SLICE_X127Y115.CLK Tah (-Th) 0.056 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<39> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN321 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 + ------------------------------------------------- --------------------------- + Total 0.289ns (0.059ns logic, 0.230ns route) + (20.4% logic, 79.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.024ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 (FF) + Requirement: 0.000ns + Data Path Delay: 0.288ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (1.145 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y120.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X131Y120.A5 net (fanout=79) 0.245 ftop/pciw_i2pS<135> + SLICE_X131Y120.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN481 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + ------------------------------------------------- --------------------------- + Total 0.288ns (0.043ns logic, 0.245ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tpciper_PIPECLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Location pin: PCIE_X0Y1.PIPECLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X7Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Location pin: RAMB36_X7Y26.CLKBWRCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X6Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2549 paths analyzed, 537 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.665ns. +-------------------------------------------------------------------------------- +Slack (setup path): 3.335ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.652ns (Levels of Logic = 2) + Clock Path Skew: 0.022ns (0.682 - 0.660) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_4 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_4 + SLICE_X91Y9.B1 net (fanout=2) 1.199 ftop/gbe0/gmac/rxRS_rxPipe<4> + SLICE_X91Y9.CMUX Topbc 0.558 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.652ns (1.440ns logic, 3.212ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.378ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_27 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.564ns (Levels of Logic = 4) + Clock Path Skew: -0.023ns (0.682 - 0.705) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_27 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y6.CQ Tcko 0.381 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_27 + SLICE_X91Y7.B2 net (fanout=15) 0.886 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + SLICE_X91Y7.COUT Topcyb 0.404 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<1> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.564ns (1.665ns logic, 2.899ns route) + (36.5% logic, 63.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.383ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.612ns (Levels of Logic = 2) + Clock Path Skew: 0.030ns (0.682 - 0.652) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_3 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y18.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/rxRS_rxPipe_3 + SLICE_X91Y9.B2 net (fanout=2) 1.115 ftop/gbe0/gmac/rxRS_rxPipe<3> + SLICE_X91Y9.CMUX Topbc 0.558 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.612ns (1.484ns logic, 3.128ns route) + (32.2% logic, 67.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.384ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.611ns (Levels of Logic = 2) + Clock Path Skew: 0.030ns (0.682 - 0.652) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y18.AQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/rxRS_rxPipe_0 + SLICE_X91Y9.A1 net (fanout=2) 1.106 ftop/gbe0/gmac/rxRS_rxPipe<0> + SLICE_X91Y9.CMUX Topac 0.566 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<8> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.611ns (1.492ns logic, 3.119ns route) + (32.4% logic, 67.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.388ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_26 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.554ns (Levels of Logic = 4) + Clock Path Skew: -0.023ns (0.682 - 0.705) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_26 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y6.AQ Tcko 0.381 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_26 + SLICE_X91Y7.B1 net (fanout=15) 0.876 ftop/gbe0/gmac/rxRS_crc/rRemainder<26> + SLICE_X91Y7.COUT Topcyb 0.404 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<1> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.554ns (1.665ns logic, 2.889ns route) + (36.6% logic, 63.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.466ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_24 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.469ns (Levels of Logic = 4) + Clock Path Skew: -0.030ns (0.682 - 0.712) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_24 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y7.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_crc/rRemainder<25> + ftop/gbe0/gmac/rxRS_crc/rRemainder_24 + SLICE_X91Y7.C1 net (fanout=14) 0.901 ftop/gbe0/gmac/rxRS_crc/rRemainder<24> + SLICE_X91Y7.COUT Topcyc 0.338 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<2> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.469ns (1.555ns logic, 2.914ns route) + (34.8% logic, 65.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.484ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_30 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.452ns (Levels of Logic = 4) + Clock Path Skew: -0.029ns (0.682 - 0.711) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_30 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.CQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_30 + SLICE_X91Y7.C2 net (fanout=16) 0.884 ftop/gbe0/gmac/rxRS_rxPipe<30> + SLICE_X91Y7.COUT Topcyc 0.338 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<2> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.452ns (1.555ns logic, 2.897ns route) + (34.9% logic, 65.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.486ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_7 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.501ns (Levels of Logic = 2) + Clock Path Skew: 0.022ns (0.682 - 0.660) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_7 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_7 + SLICE_X91Y9.C3 net (fanout=2) 1.224 ftop/gbe0/gmac/rxRS_rxPipe<7> + SLICE_X91Y9.CMUX Topcc 0.382 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<10> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.501ns (1.264ns logic, 3.237ns route) + (28.1% logic, 71.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.508ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.487ns (Levels of Logic = 2) + Clock Path Skew: 0.030ns (0.682 - 0.652) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y18.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/rxRS_rxPipe_1 + SLICE_X91Y9.A3 net (fanout=2) 0.982 ftop/gbe0/gmac/rxRS_rxPipe<1> + SLICE_X91Y9.CMUX Topac 0.566 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<8> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.487ns (1.492ns logic, 2.995ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.510ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_6 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.477ns (Levels of Logic = 2) + Clock Path Skew: 0.022ns (0.682 - 0.660) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_6 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.CQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_6 + SLICE_X91Y9.C2 net (fanout=2) 1.200 ftop/gbe0/gmac/rxRS_rxPipe<6> + SLICE_X91Y9.CMUX Topcc 0.382 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<10> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.477ns (1.264ns logic, 3.213ns route) + (28.2% logic, 71.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.511ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_31 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.425ns (Levels of Logic = 4) + Clock Path Skew: -0.029ns (0.682 - 0.711) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_31 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_31 + SLICE_X91Y7.C3 net (fanout=15) 0.857 ftop/gbe0/gmac/rxRS_rxPipe<31> + SLICE_X91Y7.COUT Topcyc 0.338 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<2> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.425ns (1.555ns logic, 2.870ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.541ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_28 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.395ns (Levels of Logic = 4) + Clock Path Skew: -0.029ns (0.682 - 0.711) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_28 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_28 + SLICE_X91Y7.B3 net (fanout=16) 0.761 ftop/gbe0/gmac/rxRS_rxPipe<28> + SLICE_X91Y7.COUT Topcyb 0.404 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<1> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.395ns (1.621ns logic, 2.774ns route) + (36.9% logic, 63.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.562ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.433ns (Levels of Logic = 2) + Clock Path Skew: 0.030ns (0.682 - 0.652) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y18.CQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/rxRS_rxPipe_2 + SLICE_X91Y9.A4 net (fanout=2) 0.928 ftop/gbe0/gmac/rxRS_rxPipe<2> + SLICE_X91Y9.CMUX Topac 0.566 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<8> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.433ns (1.492ns logic, 2.941ns route) + (33.7% logic, 66.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.610ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_29 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.326ns (Levels of Logic = 4) + Clock Path Skew: -0.029ns (0.682 - 0.711) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_29 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_29 + SLICE_X91Y7.B4 net (fanout=16) 0.692 ftop/gbe0/gmac/rxRS_rxPipe<29> + SLICE_X91Y7.COUT Topcyb 0.404 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<1> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.326ns (1.621ns logic, 2.705ns route) + (37.5% logic, 62.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.616ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_8 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.326ns (Levels of Logic = 3) + Clock Path Skew: -0.023ns (0.682 - 0.705) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_8 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y6.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_crc/rRemainder<8> + ftop/gbe0/gmac/rxRS_crc/rRemainder_8 + SLICE_X91Y8.D1 net (fanout=2) 0.855 ftop/gbe0/gmac/rxRS_crc/rRemainder<8> + SLICE_X91Y8.COUT Topcyd 0.319 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.326ns (1.458ns logic, 2.868ns route) + (33.7% logic, 66.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.617ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_5 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.370ns (Levels of Logic = 2) + Clock Path Skew: 0.022ns (0.682 - 0.660) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_5 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_5 + SLICE_X91Y9.B5 net (fanout=2) 0.917 ftop/gbe0/gmac/rxRS_rxPipe<5> + SLICE_X91Y9.CMUX Topbc 0.558 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.370ns (1.440ns logic, 2.930ns route) + (33.0% logic, 67.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.619ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_9 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.323ns (Levels of Logic = 3) + Clock Path Skew: -0.023ns (0.682 - 0.705) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_9 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y7.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_crc/rRemainder<10> + ftop/gbe0/gmac/rxRS_crc/rRemainder_9 + SLICE_X91Y8.D2 net (fanout=2) 0.852 ftop/gbe0/gmac/rxRS_crc/rRemainder<9> + SLICE_X91Y8.COUT Topcyd 0.319 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.323ns (1.458ns logic, 2.865ns route) + (33.7% logic, 66.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.636ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_18 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.305ns (Levels of Logic = 3) + Clock Path Skew: -0.024ns (0.682 - 0.706) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_18 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y5.AQ Tcko 0.381 ftop/gbe0/gmac/rxRS_crc/rRemainder<20> + ftop/gbe0/gmac/rxRS_crc/rRemainder_18 + SLICE_X91Y8.A4 net (fanout=2) 0.700 ftop/gbe0/gmac/rxRS_crc/rRemainder<18> + SLICE_X91Y8.COUT Topcya 0.409 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<4> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.305ns (1.592ns logic, 2.713ns route) + (37.0% logic, 63.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.636ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.351ns (Levels of Logic = 2) + Clock Path Skew: 0.022ns (0.682 - 0.660) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_4 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_4 + SLICE_X91Y9.B1 net (fanout=2) 1.199 ftop/gbe0/gmac/rxRS_rxPipe<4> + SLICE_X91Y9.CMUX Topbc 0.558 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.176 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + ------------------------------------------------- --------------------------- + Total 4.351ns (1.139ns logic, 3.212ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.675ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_26 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.306ns (Levels of Logic = 4) + Clock Path Skew: 0.016ns (0.682 - 0.666) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_26 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y8.CQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<27> + ftop/gbe0/gmac/rxRS_rxPipe_26 + SLICE_X91Y7.A1 net (fanout=16) 0.623 ftop/gbe0/gmac/rxRS_rxPipe<26> + SLICE_X91Y7.COUT Topcya 0.409 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_lut<0> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<3> + SLICE_X91Y8.COUT Tbyp 0.078 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CIN net (fanout=1) 0.000 ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<7> + SLICE_X91Y9.CMUX Tcinc 0.257 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF_enq_1__VAL_1<9>_cy<10> + SLICE_X99Y25.A4 net (fanout=1) 1.320 ftop/gbe0/gmac/MUX_rxRS_rxF_enq_1__VAL_1<9> + SLICE_X99Y25.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF_sD_IN101 + SLICE_X100Y30.BI net (fanout=1) 0.693 ftop/gbe0/gmac/rxRS_rxF_sD_IN<9> + SLICE_X100Y30.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.306ns (1.670ns logic, 2.636ns route) + (38.8% logic, 61.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.090ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.101ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.060 - 0.049) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y27.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + SLICE_X90Y27.DX net (fanout=4) 0.105 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + SLICE_X90Y27.CLK Tckdi (-Th) 0.102 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.101ns (-0.004ns logic, 0.105ns route) + (-4.0% logic, 104.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.106ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_14 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_14 to ftop/gbe0/gmac/rxRS_rxPipe_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y9.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/rxRS_rxPipe_14 + SLICE_X90Y8.CX net (fanout=2) 0.096 ftop/gbe0/gmac/rxRS_rxPipe<14> + SLICE_X90Y8.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe_22 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.107ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_13 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_13 to ftop/gbe0/gmac/rxRS_rxPipe_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y9.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/rxRS_rxPipe_13 + SLICE_X90Y8.BX net (fanout=2) 0.097 ftop/gbe0/gmac/rxRS_rxPipe<13> + SLICE_X90Y8.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe_21 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.108ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_12 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_20 (FF) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_12 to ftop/gbe0/gmac/rxRS_rxPipe_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/rxRS_rxPipe_12 + SLICE_X90Y8.AX net (fanout=2) 0.098 ftop/gbe0/gmac/rxRS_rxPipe<12> + SLICE_X90Y8.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe_20 + ------------------------------------------------- --------------------------- + Total 0.120ns (0.022ns logic, 0.098ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.110ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_15 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.122ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_15 to ftop/gbe0/gmac/rxRS_rxPipe_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y9.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/rxRS_rxPipe_15 + SLICE_X90Y8.DX net (fanout=2) 0.100 ftop/gbe0/gmac/rxRS_rxPipe<15> + SLICE_X90Y8.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe_23 + ------------------------------------------------- --------------------------- + Total 0.122ns (0.022ns logic, 0.100ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y27.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + SLICE_X91Y27.A5 net (fanout=4) 0.070 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + SLICE_X91Y27.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_3_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.043ns logic, 0.070ns route) + (38.1% logic, 61.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y30.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + SLICE_X89Y30.C5 net (fanout=3) 0.071 ftop/gbe0/gmac/rxRS_preambleCnt_value<2> + SLICE_X89Y30.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Result<2>1 + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.042ns logic, 0.071ns route) + (37.2% logic, 62.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.123ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y30.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + SLICE_X89Y30.A5 net (fanout=5) 0.080 ftop/gbe0/gmac/rxRS_preambleCnt_value<0> + SLICE_X89Y30.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_rxRS_preambleCnt_value_xor<0>11_INV_0 + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.043ns logic, 0.080ns route) + (35.0% logic, 65.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.127ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_10 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_18 (FF) + Requirement: 0.000ns + Data Path Delay: 0.140ns (Levels of Logic = 1) + Clock Path Skew: 0.013ns (0.064 - 0.051) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_10 to ftop/gbe0/gmac/rxRS_rxPipe_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y10.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<11> + ftop/gbe0/gmac/rxRS_rxPipe_10 + SLICE_X90Y8.C5 net (fanout=2) 0.124 ftop/gbe0/gmac/rxRS_rxPipe<10> + SLICE_X90Y8.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe<10>_rt + ftop/gbe0/gmac/rxRS_rxPipe_18 + ------------------------------------------------- --------------------------- + Total 0.140ns (0.016ns logic, 0.124ns route) + (11.4% logic, 88.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.127ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 to ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y30.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + SLICE_X89Y30.D5 net (fanout=5) 0.086 ftop/gbe0/gmac/rxRS_preambleCnt_value<0> + SLICE_X89Y30.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Result<3>1 + ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.041ns logic, 0.086ns route) + (32.3% logic, 67.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.127ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.140ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.062 - 0.049) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y27.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 + SLICE_X90Y29.BX net (fanout=7) 0.118 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<1> + SLICE_X90Y29.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.140ns (0.022ns logic, 0.118ns route) + (15.7% logic, 84.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.129ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y27.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + SLICE_X90Y27.C5 net (fanout=6) 0.087 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<2> + SLICE_X90Y27.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_1_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.042ns logic, 0.087ns route) + (32.6% logic, 67.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.130ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_8 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.143ns (Levels of Logic = 1) + Clock Path Skew: 0.013ns (0.064 - 0.051) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_8 to ftop/gbe0/gmac/rxRS_rxPipe_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y10.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<11> + ftop/gbe0/gmac/rxRS_rxPipe_8 + SLICE_X90Y8.A5 net (fanout=2) 0.127 ftop/gbe0/gmac/rxRS_rxPipe<8> + SLICE_X90Y8.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe<8>_rt + ftop/gbe0/gmac/rxRS_rxPipe_16 + ------------------------------------------------- --------------------------- + Total 0.143ns (0.016ns logic, 0.127ns route) + (11.2% logic, 88.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.132ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_30 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.144ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_30 to ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_30 + SLICE_X95Y6.C6 net (fanout=16) 0.102 ftop/gbe0/gmac/rxRS_rxPipe<30> + SLICE_X95Y6.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_crc/rRemainder<1> + ftop/gbe0/gmac/rxRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 0.144ns (0.042ns logic, 0.102ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y27.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 + SLICE_X90Y27.D5 net (fanout=6) 0.096 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<0> + SLICE_X90Y27.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_2_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.138ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_34 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_42 (FF) + Requirement: 0.000ns + Data Path Delay: 0.148ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_34 to ftop/gbe0/gmac/rxRS_rxPipe_42 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y25.CMUX Tshcko 0.128 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_34 + SLICE_X90Y25.CX net (fanout=2) 0.096 ftop/gbe0/gmac/rxRS_rxPipe<34> + SLICE_X90Y25.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<43> + ftop/gbe0/gmac/rxRS_rxPipe_42 + ------------------------------------------------- --------------------------- + Total 0.148ns (0.052ns logic, 0.096ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.141ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.141ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y27.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 + SLICE_X90Y27.A5 net (fanout=6) 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<0> + SLICE_X90Y27.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1[0]_INV_4029_o1_INV_0 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 + ------------------------------------------------- --------------------------- + Total 0.141ns (0.043ns logic, 0.098ns route) + (30.5% logic, 69.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.142ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_29 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_10 (FF) + Requirement: 0.000ns + Data Path Delay: 0.175ns (Levels of Logic = 1) + Clock Path Skew: 0.033ns (0.313 - 0.280) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_29 to ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y8.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/rxRS_rxPipe_29 + SLICE_X93Y7.C5 net (fanout=16) 0.133 ftop/gbe0/gmac/rxRS_rxPipe<29> + SLICE_X93Y7.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_crc/rRemainder<10> + ftop/gbe0/gmac/rxRS_crc/rRemainder$D_IN<10> + ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 0.175ns (0.042ns logic, 0.133ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.145ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.145ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y27.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 + SLICE_X90Y27.D4 net (fanout=4) 0.104 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + SLICE_X90Y27.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_2_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.145ns (0.041ns logic, 0.104ns route) + (28.3% logic, 71.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.146ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.146ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 to ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y30.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + SLICE_X89Y30.B4 net (fanout=4) 0.105 ftop/gbe0/gmac/rxRS_preambleCnt_value<1> + SLICE_X89Y30.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_rxRS_preambleCnt_value_xor<1>11 + ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + ------------------------------------------------- --------------------------- + Total 0.146ns (0.041ns logic, 0.105ns route) + (28.1% logic, 71.9% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 4.668ns (period - min period limit) + Period: 8.000ns + Min period limit: 3.332ns (300.120MHz) (Tbrper_I) + Physical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Logical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Location pin: BUFR_X2Y3.I + Clock network: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X100Y29.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X100Y30.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X100Y30.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X100Y30.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 7035 paths analyzed, 691 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 6.970ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.886ns (Levels of Logic = 3) + Clock Path Skew: -0.049ns (0.942 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y63.CE net (fanout=3) 1.330 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y63.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 6.886ns (0.869ns logic, 6.017ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.081ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Requirement: 8.000ns + Data Path Delay: 6.884ns (Levels of Logic = 3) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B6 net (fanout=3) 0.234 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X126Y64.CE net (fanout=2) 1.420 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X126Y64.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + ------------------------------------------------- --------------------------- + Total 6.884ns (0.869ns logic, 6.015ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.081ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Requirement: 8.000ns + Data Path Delay: 6.884ns (Levels of Logic = 3) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B6 net (fanout=3) 0.234 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X126Y64.CE net (fanout=2) 1.420 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X126Y64.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + ------------------------------------------------- --------------------------- + Total 6.884ns (0.869ns logic, 6.015ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.767ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 6.767ns (0.869ns logic, 5.898ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.767ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 6.767ns (0.869ns logic, 5.898ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.767ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 6.767ns (0.869ns logic, 5.898ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 8.000ns + Data Path Delay: 6.767ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 6.767ns (0.869ns logic, 5.898ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.185ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 (FF) + Requirement: 8.000ns + Data Path Delay: 6.729ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.246 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + ------------------------------------------------- --------------------------- + Total 6.729ns (0.831ns logic, 5.898ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.185ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 (FF) + Requirement: 8.000ns + Data Path Delay: 6.729ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.246 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 6.729ns (0.831ns logic, 5.898ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.210ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Requirement: 8.000ns + Data Path Delay: 6.438ns (Levels of Logic = 4) + Clock Path Skew: -0.317ns (1.443 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B6 net (fanout=3) 0.234 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X126Y64.CE net (fanout=2) 1.420 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X126Y64.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + ------------------------------------------------- --------------------------- + Total 6.438ns (0.893ns logic, 5.545ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.210ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Requirement: 8.000ns + Data Path Delay: 6.438ns (Levels of Logic = 4) + Clock Path Skew: -0.317ns (1.443 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B6 net (fanout=3) 0.234 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X103Y55.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X126Y64.CE net (fanout=2) 1.420 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X126Y64.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + ------------------------------------------------- --------------------------- + Total 6.438ns (0.893ns logic, 5.545ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.220ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.440ns (Levels of Logic = 4) + Clock Path Skew: -0.305ns (1.455 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y63.CE net (fanout=3) 1.330 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y63.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 6.440ns (0.893ns logic, 5.547ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.225ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 8.000ns + Data Path Delay: 6.689ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X121Y62.CE net (fanout=3) 1.099 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X121Y62.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 6.689ns (0.903ns logic, 5.786ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.225ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Requirement: 8.000ns + Data Path Delay: 6.689ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X121Y62.CE net (fanout=3) 1.099 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X121Y62.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + ------------------------------------------------- --------------------------- + Total 6.689ns (0.903ns logic, 5.786ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.225ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 8.000ns + Data Path Delay: 6.689ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X121Y62.CE net (fanout=3) 1.099 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X121Y62.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 6.689ns (0.903ns logic, 5.786ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.225ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Requirement: 8.000ns + Data Path Delay: 6.689ns (Levels of Logic = 3) + Clock Path Skew: -0.051ns (0.940 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X88Y43.B2 net (fanout=21) 2.989 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X121Y62.CE net (fanout=3) 1.099 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X121Y62.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + ------------------------------------------------- --------------------------- + Total 6.689ns (0.903ns logic, 5.786ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.333ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.583ns (Levels of Logic = 4) + Clock Path Skew: -0.049ns (0.942 - 0.991) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y64.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X95Y51.A6 net (fanout=1) 1.655 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y63.CE net (fanout=3) 1.330 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y63.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 6.583ns (0.937ns logic, 5.646ns route) + (14.2% logic, 85.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 8.000ns + Data Path Delay: 6.321ns (Levels of Logic = 4) + Clock Path Skew: -0.307ns (1.453 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 6.321ns (0.893ns logic, 5.428ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.321ns (Levels of Logic = 4) + Clock Path Skew: -0.307ns (1.453 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 6.321ns (0.893ns logic, 5.428ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.321ns (Levels of Logic = 4) + Clock Path Skew: -0.307ns (1.453 - 1.760) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X95Y51.A2 net (fanout=27) 1.556 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X95Y51.A Tilo 0.068 ftop/gbe0/wci_wslv_reqF/_n0137_inv + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X88Y43.B6 net (fanout=21) 0.963 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X88Y43.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X103Y55.A6 net (fanout=11) 1.372 ftop/gbe0/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X103Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A5 net (fanout=3) 0.326 ftop/gbe0/gmac/txRS_txF_dDEQ + SLICE_X105Y55.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o1 + SLICE_X120Y62.CE net (fanout=3) 1.211 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_205_o_MUX_11490_o + SLICE_X120Y62.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 6.321ns (0.893ns logic, 5.428ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.063ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.072ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y62.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X120Y62.B6 net (fanout=4) 0.051 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X120Y62.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.072ns (0.021ns logic, 0.051ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_1 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_1 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X85Y37.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/txRS_ifgCnt_value_1 + SLICE_X84Y37.A6 net (fanout=4) 0.059 ftop/gbe0/gmac/txRS_ifgCnt_value<1> + SLICE_X84Y37.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.081ns (0.022ns logic, 0.059ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y62.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + SLICE_X120Y62.A6 net (fanout=6) 0.059 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<1> + SLICE_X120Y62.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.081ns (0.022ns logic, 0.059ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.083ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_14 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 1) + Clock Path Skew: 0.037ns (0.520 - 0.483) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_14 to ftop/gbe0/gmac/txRS_crc/rRemainder_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y34.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<16> + ftop/gbe0/gmac/txRS_crc/rRemainder_14 + SLICE_X84Y34.B6 net (fanout=2) 0.099 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + SLICE_X84Y34.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_crc/rRemainder<24> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<22>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_22 + ------------------------------------------------- --------------------------- + Total 0.120ns (0.021ns logic, 0.099ns route) + (17.5% logic, 82.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.084ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.457 - 0.418) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y65.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 + SLICE_X125Y65.DX net (fanout=1) 0.101 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + SLICE_X125Y65.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.022ns logic, 0.101ns route) + (17.9% logic, 82.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.084ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.457 - 0.418) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y65.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 + SLICE_X125Y65.BX net (fanout=1) 0.101 ftop/gbe0/gmac/txRS_txF/dSyncReg1<1> + SLICE_X125Y65.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.022ns logic, 0.101ns route) + (17.9% logic, 82.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.106ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 (FF) + Destination: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 to ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y38.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X91Y38.AX net (fanout=1) 0.096 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X91Y38.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.107ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_11 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.143ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.534 - 0.498) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_11 to ftop/gbe0/gmac/txRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X82Y37.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<11> + ftop/gbe0/gmac/txRS_crc/rRemainder_11 + SLICE_X80Y37.C6 net (fanout=2) 0.101 ftop/gbe0/gmac/txRS_crc/rRemainder<11> + SLICE_X80Y37.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_crc/rRemainder<19> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<19>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 0.143ns (0.042ns logic, 0.101ns route) + (29.4% logic, 70.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.108ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_21 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_29 (FF) + Requirement: 0.000ns + Data Path Delay: 0.144ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.520 - 0.484) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_21 to ftop/gbe0/gmac/txRS_crc/rRemainder_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y36.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder_21 + SLICE_X84Y35.C5 net (fanout=2) 0.122 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + SLICE_X84Y35.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<29> + ftop/gbe0/gmac/txRS_crc/rRemainder_29 + ------------------------------------------------- --------------------------- + Total 0.144ns (0.022ns logic, 0.122ns route) + (15.3% logic, 84.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X120Y62.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X120Y62.A5 net (fanout=2) 0.072 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X120Y62.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_3 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y37.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + SLICE_X84Y37.A5 net (fanout=2) 0.072 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + SLICE_X84Y37.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X85Y37.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + SLICE_X85Y37.C5 net (fanout=3) 0.071 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + SLICE_X85Y37.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.042ns logic, 0.071ns route) + (37.2% logic, 62.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y62.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X120Y62.CX net (fanout=4) 0.114 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X120Y62.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.009ns logic, 0.114ns route) + (7.3% logic, 92.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.055 - 0.044) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X120Y62.BQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + SLICE_X120Y63.BX net (fanout=2) 0.100 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + SLICE_X120Y63.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.118ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/txRS_ifgCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X85Y37.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + SLICE_X85Y37.A5 net (fanout=5) 0.075 ftop/gbe0/gmac/txRS_ifgCnt_value<0> + SLICE_X85Y37.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<0>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.043ns logic, 0.075ns route) + (36.4% logic, 63.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.118ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_26 to ftop/gbe0/gmac/txRS_crc/rRemainder_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X81Y39.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<27> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + SLICE_X81Y39.B5 net (fanout=15) 0.077 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + SLICE_X81Y39.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_crc/rRemainder<27> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<25>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_25 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.041ns logic, 0.077ns route) + (34.7% logic, 65.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.118ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y62.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + SLICE_X121Y62.C5 net (fanout=5) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<2> + SLICE_X121Y62.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_1_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.042ns logic, 0.076ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_2 to ftop/gbe0/gmac/txRS_emitFCS_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y40.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_2 + SLICE_X95Y40.C5 net (fanout=32) 0.077 ftop/gbe0/gmac/txRS_emitFCS<2> + SLICE_X95Y40.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN31 + ftop/gbe0/gmac/txRS_emitFCS_2 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.042ns logic, 0.077ns route) + (35.3% logic, 64.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_13 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.159ns (Levels of Logic = 1) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_13 to ftop/gbe0/gmac/txRS_crc/rRemainder_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y36.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_crc/rRemainder<13> + ftop/gbe0/gmac/txRS_crc/rRemainder_13 + SLICE_X86Y36.C6 net (fanout=2) 0.100 ftop/gbe0/gmac/txRS_crc/rRemainder<13> + SLICE_X86Y36.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<21>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_21 + ------------------------------------------------- --------------------------- + Total 0.159ns (0.059ns logic, 0.100ns route) + (37.1% logic, 62.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X82Y35.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + SLICE_X82Y35.C5 net (fanout=4) 0.082 ftop/gbe0/gmac/txRS_preambleCnt_value<2> + SLICE_X82Y35.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.042ns logic, 0.082ns route) + (33.9% logic, 66.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 6.571ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys1_clk/I0 + Logical resource: ftop/sys1_clk/I0 + Location pin: BUFGCTRL_X0Y24.I0 + Clock network: ftop/sys1_clki_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_en_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxEna/CK + Location pin: OLOGIC_X2Y63.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_er_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxErr/CK + Location pin: OLOGIC_X2Y62.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_0_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData/CK + Location pin: OLOGIC_X2Y64.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_1_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_1/CK + Location pin: OLOGIC_X2Y65.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_2_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_2/CK + Location pin: OLOGIC_X2Y66.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_3_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_3/CK + Location pin: OLOGIC_X2Y67.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_4_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_4/CK + Location pin: OLOGIC_X2Y68.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_5_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_5/CK + Location pin: OLOGIC_X2Y69.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_6_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_6/CK + Location pin: OLOGIC_X2Y70.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_7_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_7/CK + Location pin: OLOGIC_X2Y71.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_gtx_clk_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxClk/CK + Location pin: OLOGIC_X2Y46.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_0/SR + Location pin: SLICE_X82Y43.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst_OUT_RST/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_1/SR + Location pin: SLICE_X83Y43.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: gmii_rstn_OBUF/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_0/SR + Location pin: SLICE_X85Y40.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: gmii_rstn_OBUF/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_1/SR + Location pin: SLICE_X85Y40.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Location pin: SLICE_X90Y38.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2/SR + Location pin: SLICE_X91Y38.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Location pin: SLICE_X94Y52.SR + Clock network: ftop/gbe0/gmac/txRS_unfBit/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF_dEMPTY_N/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg/SR + Location pin: SLICE_X105Y55.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD +TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 75760 paths analyzed, 22658 endpoints analyzed, 5 failing endpoints + 5 timing errors detected. (5 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.130ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.130ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.865ns (Levels of Logic = 3) + Clock Path Skew: -0.207ns (1.516 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A6 net (fanout=8) 1.333 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.AX net (fanout=8) 0.906 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.865ns (0.619ns logic, 4.246ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.129ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.864ns (Levels of Logic = 3) + Clock Path Skew: -0.207ns (1.516 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A6 net (fanout=8) 1.333 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.BX net (fanout=8) 0.905 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.864ns (0.619ns logic, 4.245ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.108ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.843ns (Levels of Logic = 3) + Clock Path Skew: -0.207ns (1.516 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A6 net (fanout=8) 1.333 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.AX net (fanout=8) 0.906 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y129.CLK Tdick 0.012 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.843ns (0.597ns logic, 4.246ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.090ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.844ns (Levels of Logic = 3) + Clock Path Skew: -0.188ns (1.535 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A6 net (fanout=8) 1.333 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X69Y128.AX net (fanout=8) 0.885 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X69Y128.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.844ns (0.619ns logic, 4.225ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.082ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.815ns (Levels of Logic = 3) + Clock Path Skew: -0.209ns (1.514 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A6 net (fanout=8) 1.333 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X65Y141.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y131.DX net (fanout=8) 0.856 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X62Y131.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.815ns (0.619ns logic, 4.196ns route) + (12.9% logic, 87.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_6 (FF) + Requirement: 5.000ns + Data Path Delay: 4.608ns (Levels of Logic = 1) + Clock Path Skew: -0.325ns (1.535 - 1.860) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y212.CQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 + SLICE_X64Y199.C6 net (fanout=1) 0.791 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + SLICE_X64Y199.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[32].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o1 + SLICE_X65Y154.SR net (fanout=21) 2.855 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o + SLICE_X65Y154.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<24> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_6 + ------------------------------------------------- --------------------------- + Total 4.608ns (0.962ns logic, 3.646ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_5 (FF) + Requirement: 5.000ns + Data Path Delay: 4.608ns (Levels of Logic = 1) + Clock Path Skew: -0.325ns (1.535 - 1.860) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y212.CQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 + SLICE_X64Y199.C6 net (fanout=1) 0.791 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + SLICE_X64Y199.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[32].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o1 + SLICE_X65Y154.SR net (fanout=21) 2.855 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o + SLICE_X65Y154.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<24> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_5 + ------------------------------------------------- --------------------------- + Total 4.608ns (0.962ns logic, 3.646ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d2_6 (FF) + Requirement: 5.000ns + Data Path Delay: 4.608ns (Levels of Logic = 1) + Clock Path Skew: -0.325ns (1.535 - 1.860) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d2_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y212.CQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed_7 + SLICE_X64Y199.C6 net (fanout=1) 0.791 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed<7> + SLICE_X64Y199.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[32].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o1 + SLICE_X65Y154.SR net (fanout=21) 2.855 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_delayed[7]_wrlvl_active_r1_OR_6006_o + SLICE_X65Y154.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<24> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d2_6 + ------------------------------------------------- --------------------------- + Total 4.608ns (0.962ns logic, 3.646ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.612ns (Levels of Logic = 3) + Clock Path Skew: -0.321ns (1.549 - 1.870) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y201.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel + SLICE_X67Y177.B6 net (fanout=347) 1.792 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + SLICE_X67Y177.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wrdata_en_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_mux_wrdata_en11 + SLICE_X71Y153.D6 net (fanout=24) 1.639 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/mux_wrdata_en + SLICE_X71Y153.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[1]_wrdata_en_r2_Mux_9_o11 + SLICE_X71Y153.C6 net (fanout=1) 0.110 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[1]_wrdata_en_r2_Mux_9_o1 + SLICE_X71Y153.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[1]_wrdata_en_r2_Mux_9_o12 + SLICE_X85Y152.DX net (fanout=1) 0.496 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[1]_wrdata_en_r2_Mux_9_o + SLICE_X85Y152.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d4_0 + ------------------------------------------------- --------------------------- + Total 4.612ns (0.575ns logic, 4.037ns route) + (12.5% logic, 87.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.011ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_5 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq1_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.726ns (Levels of Logic = 2) + Clock Path Skew: -0.205ns (1.548 - 1.753) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_5 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y200.DQ Tcko 0.381 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_5 + SLICE_X80Y162.B3 net (fanout=44) 3.185 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<5> + SLICE_X80Y162.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o11 + SLICE_X80Y162.A2 net (fanout=1) 0.474 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o1 + SLICE_X80Y162.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o14 + SLICE_X73Y161.BX net (fanout=1) 0.516 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[5]_wrdata_en_r3_Mux_24_o + SLICE_X73Y161.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq1_2 + ------------------------------------------------- --------------------------- + Total 4.726ns (0.551ns logic, 4.175ns route) + (11.7% logic, 88.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.019ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.713ns (Levels of Logic = 3) + Clock Path Skew: -0.210ns (1.513 - 1.723) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C6 net (fanout=10) 1.707 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X69Y167.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[0].rst_dm_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X69Y141.B6 net (fanout=8) 1.171 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X69Y141.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_3 + SLICE_X63Y146.DX net (fanout=9) 0.916 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_3 + SLICE_X63Y146.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.713ns (0.619ns logic, 4.094ns route) + (13.1% logic, 86.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.023ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_7 (FF) + Requirement: 5.000ns + Data Path Delay: 4.574ns (Levels of Logic = 3) + Clock Path Skew: -0.345ns (1.525 - 1.870) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y201.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel + SLICE_X67Y177.B6 net (fanout=347) 1.792 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + SLICE_X67Y177.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wrdata_en_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_mux_wrdata_en11 + SLICE_X64Y144.D6 net (fanout=24) 1.838 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/mux_wrdata_en + SLICE_X64Y144.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<31> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[15]_wrdata_en_r2_Mux_72_o11 + SLICE_X64Y144.C6 net (fanout=1) 0.123 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[15]_wrdata_en_r2_Mux_72_o1 + SLICE_X64Y144.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<31> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[15]_wrdata_en_r2_Mux_72_o12 + SLICE_X65Y143.DX net (fanout=1) 0.246 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[15]_wrdata_en_r2_Mux_72_o + SLICE_X65Y143.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<31> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_7 + ------------------------------------------------- --------------------------- + Total 4.574ns (0.575ns logic, 3.999ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_32 (FF) + Requirement: 5.000ns + Data Path Delay: 4.894ns (Levels of Logic = 4) + Clock Path Skew: -0.024ns (1.584 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_32 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C6 net (fanout=8) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_valid_r_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A6 net (fanout=5) 1.118 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv1 + SLICE_X15Y228.CE net (fanout=11) 0.432 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + SLICE_X15Y228.CLK Tceck 0.318 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_32 + ------------------------------------------------- --------------------------- + Total 4.894ns (0.971ns logic, 3.923ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 (FF) + Requirement: 5.000ns + Data Path Delay: 4.894ns (Levels of Logic = 4) + Clock Path Skew: -0.024ns (1.584 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C6 net (fanout=8) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_valid_r_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A6 net (fanout=5) 1.118 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv1 + SLICE_X15Y228.CE net (fanout=11) 0.432 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + SLICE_X15Y228.CLK Tceck 0.318 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 + ------------------------------------------------- --------------------------- + Total 4.894ns (0.971ns logic, 3.923ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_31 (FF) + Requirement: 5.000ns + Data Path Delay: 4.894ns (Levels of Logic = 4) + Clock Path Skew: -0.024ns (1.584 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C6 net (fanout=8) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_valid_r_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A6 net (fanout=5) 1.118 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv1 + SLICE_X15Y228.CE net (fanout=11) 0.432 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + SLICE_X15Y228.CLK Tceck 0.318 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_33 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_31 + ------------------------------------------------- --------------------------- + Total 4.894ns (0.971ns logic, 3.923ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_8 (FF) + Requirement: 5.000ns + Data Path Delay: 4.849ns (Levels of Logic = 4) + Clock Path Skew: -0.066ns (1.542 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A6 net (fanout=8) 0.848 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_en_dqs_skew_r_inv1_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A5 net (fanout=8) 0.649 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y228.SR net (fanout=6) 0.627 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y228.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_8 + ------------------------------------------------- --------------------------- + Total 4.849ns (1.166ns logic, 3.683ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_11 (FF) + Requirement: 5.000ns + Data Path Delay: 4.849ns (Levels of Logic = 4) + Clock Path Skew: -0.066ns (1.542 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A6 net (fanout=8) 0.848 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_en_dqs_skew_r_inv1_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A5 net (fanout=8) 0.649 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y228.SR net (fanout=6) 0.627 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y228.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_11 + ------------------------------------------------- --------------------------- + Total 4.849ns (1.166ns logic, 3.683ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_5 (FF) + Requirement: 5.000ns + Data Path Delay: 4.874ns (Levels of Logic = 4) + Clock Path Skew: -0.041ns (1.567 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C6 net (fanout=8) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X35Y217.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_valid_r_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A6 net (fanout=5) 1.118 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_18 + SLICE_X19Y228.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv1 + SLICE_X23Y228.CE net (fanout=11) 0.412 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/_n3773_inv + SLICE_X23Y228.CLK Tceck 0.318 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_5 + ------------------------------------------------- --------------------------- + Total 4.874ns (0.971ns logic, 3.903ns route) + (19.9% logic, 80.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_9 (FF) + Requirement: 5.000ns + Data Path Delay: 4.849ns (Levels of Logic = 4) + Clock Path Skew: -0.066ns (1.542 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A6 net (fanout=8) 0.848 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_en_dqs_skew_r_inv1_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A5 net (fanout=8) 0.649 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y228.SR net (fanout=6) 0.627 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y228.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_9 + ------------------------------------------------- --------------------------- + Total 4.849ns (1.166ns logic, 3.683ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_10 (FF) + Requirement: 5.000ns + Data Path Delay: 4.849ns (Levels of Logic = 4) + Clock Path Skew: -0.066ns (1.542 - 1.608) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y194.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X55Y194.A6 net (fanout=296) 0.300 ftop/dram0/memc_memc/rst + SLICE_X55Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].u_iob_dq/iserdes_q_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C6 net (fanout=10) 1.259 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X39Y207.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A6 net (fanout=8) 0.848 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X31Y218.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_en_dqs_skew_r_inv1_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A5 net (fanout=8) 0.649 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X33Y225.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y228.SR net (fanout=6) 0.627 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y228.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt1_r_10 + ------------------------------------------------- --------------------------- + Total 4.849ns (1.166ns logic, 3.683ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.051ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_136 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.060ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_136 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y176.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<139> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_136 + SLICE_X92Y176.AI net (fanout=1) 0.049 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<136> + SLICE_X92Y176.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<133> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.060ns (0.011ns logic, 0.049ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.058ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise0_r_17 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise0_r_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.067ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise0_r_17 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise0_r_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y215.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise0_r_17 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise0_r_17 + SLICE_X12Y215.D6 net (fanout=1) 0.046 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise0_r_17 + SLICE_X12Y215.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r[7][1]_old_sr_rise0_r[7][1]_equal_319_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise0_r_7 + ------------------------------------------------- --------------------------- + Total 0.067ns (0.021ns logic, 0.046ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.058ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.165ns (Levels of Logic = 2) + Clock Path Skew: 0.107ns (0.756 - 0.649) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y199.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 + SLICE_X121Y199.BX net (fanout=2) 0.053 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<39> + SLICE_X121Y199.COUT Tbxcy 0.083 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CIN net (fanout=1) 0.000 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CLK Tckcin (-Th) 0.069 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<45> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_4 + ------------------------------------------------- --------------------------- + Total 0.165ns (0.112ns logic, 0.053ns route) + (67.9% logic, 32.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.077ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.050 - 0.041) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y219.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + SLICE_X10Y219.B6 net (fanout=5) 0.056 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + SLICE_X10Y219.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r[5][1]_pat_fall0[1][1]_equal_563_o<1>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 + ------------------------------------------------- --------------------------- + Total 0.077ns (0.021ns logic, 0.056ns route) + (27.3% logic, 72.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.079ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.058 - 0.048) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y213.BMUX Tshcko 0.129 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 + SLICE_X12Y213.DX net (fanout=5) 0.063 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 + SLICE_X12Y213.CLK Tckdi (-Th) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_17 + ------------------------------------------------- --------------------------- + Total 0.079ns (0.016ns logic, 0.063ns route) + (20.3% logic, 79.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y201.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<73> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 + SLICE_X96Y201.A6 net (fanout=5) 0.059 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<71> + SLICE_X96Y201.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done_next<3>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + ------------------------------------------------- --------------------------- + Total 0.081ns (0.022ns logic, 0.059ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.080ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.061 - 0.050) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X51Y228.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r<0> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_0 + SLICE_X50Y228.D6 net (fanout=5) 0.059 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r<0> + SLICE_X50Y228.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/Mcount_periodic_rd_generation.periodic_rd_timer_r_xor<1>11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_timer_r_1 + ------------------------------------------------- --------------------------- + Total 0.080ns (0.021ns logic, 0.059ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_16 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.058 - 0.048) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_16 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y213.AMUX Tshcko 0.130 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_16 + SLICE_X12Y213.CX net (fanout=5) 0.064 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_16 + SLICE_X12Y213.CLK Tckdi (-Th) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_16 + ------------------------------------------------- --------------------------- + Total 0.081ns (0.017ns logic, 0.064ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.531 - 0.494) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X67Y200.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_4 + SLICE_X64Y200.CX net (fanout=2) 0.100 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r<4> + SLICE_X64Y200.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.009ns logic, 0.100ns route) + (8.3% logic, 91.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.531 - 0.494) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X67Y200.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r_2 + SLICE_X64Y200.AX net (fanout=2) 0.100 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r<2> + SLICE_X64Y200.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_2 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.009ns logic, 0.100ns route) + (8.3% logic, 91.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.073ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_30 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.524 - 0.490) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_30 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y186.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<91> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_30 + SLICE_X68Y186.AI net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<30> + SLICE_X68Y186.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<27> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.107ns (0.011ns logic, 0.096ns route) + (10.3% logic, 89.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.073ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 2) + Clock Path Skew: 0.107ns (0.756 - 0.649) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y199.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 + SLICE_X121Y199.BX net (fanout=2) 0.053 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<39> + SLICE_X121Y199.COUT Tbxcy 0.083 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CIN net (fanout=1) 0.000 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CLK Tckcin (-Th) 0.054 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<45> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_6 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.127ns logic, 0.053ns route) + (70.6% logic, 29.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.074ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_206 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.508 - 0.474) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_206 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y182.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<207> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_206 + SLICE_X88Y182.BI net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<206> + SLICE_X88Y182.CLK Tdh (-Th) 0.086 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<205> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMB + ------------------------------------------------- --------------------------- + Total 0.108ns (0.012ns logic, 0.096ns route) + (11.1% logic, 88.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.074ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.511 - 0.477) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y184.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<15> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_14 + SLICE_X88Y184.BI net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<14> + SLICE_X88Y184.CLK Tdh (-Th) 0.086 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<13> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMB + ------------------------------------------------- --------------------------- + Total 0.108ns (0.012ns logic, 0.096ns route) + (11.1% logic, 88.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_16 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.112ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.511 - 0.477) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_16 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y185.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<19> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_16 + SLICE_X88Y184.AI net (fanout=1) 0.101 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<16> + SLICE_X88Y184.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<13> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.112ns (0.011ns logic, 0.101ns route) + (9.8% logic, 90.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.090ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y206.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 + SLICE_X64Y206.A6 net (fanout=7) 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt<1> + SLICE_X64Y206.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/Mcount_enable_wrlvl_cnt_xor<4>11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_4 + ------------------------------------------------- --------------------------- + Total 0.090ns (0.022ns logic, 0.068ns route) + (24.4% logic, 75.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_18 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.513 - 0.477) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_18 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y185.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<19> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_18 + SLICE_X88Y186.CI net (fanout=1) 0.101 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<18> + SLICE_X88Y186.CLK Tdh (-Th) 0.085 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<19> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMC + ------------------------------------------------- --------------------------- + Total 0.114ns (0.013ns logic, 0.101ns route) + (11.4% logic, 88.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.080ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_r (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.453 - 0.415) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_r to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X33Y219.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<24> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_r + SLICE_X34Y218.DX net (fanout=3) 0.109 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<24> + SLICE_X34Y218.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ------------------------------------------------- --------------------------- + Total 0.118ns (0.009ns logic, 0.109ns route) + (7.6% logic, 92.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.080ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.187ns (Levels of Logic = 2) + Clock Path Skew: 0.107ns (0.756 - 0.649) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y199.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_1 + SLICE_X121Y199.BX net (fanout=2) 0.053 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<39> + SLICE_X121Y199.COUT Tbxcy 0.083 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<41> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CIN net (fanout=1) 0.000 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<3> + SLICE_X121Y200.CLK Tckcin (-Th) 0.047 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<45> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/Maccum_high_cy<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/high_5 + ------------------------------------------------- --------------------------- + Total 0.187ns (0.134ns logic, 0.053ns route) + (71.7% logic, 28.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl (FF) + Requirement: 0.000ns + Data Path Delay: 0.082ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y227.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r + SLICE_X63Y227.A5 net (fanout=2) 0.066 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r + SLICE_X63Y227.CLK Tah (-Th) 0.082 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.new_maint_rank_r_rt + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl + ------------------------------------------------- --------------------------- + Total 0.082ns (0.016ns logic, 0.066ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1/CLK + Location pin: SLICE_X4Y170.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA/CLK + Location pin: SLICE_X4Y172.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA/CLK + Location pin: SLICE_X4Y172.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA_D1/CLK + Location pin: SLICE_X4Y172.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA_D1/CLK + Location pin: SLICE_X4Y172.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = +PERIOD TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" +TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.429ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" TS_SYS0CLK * 2 + HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.071ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 997.500ns (max period limit - period) + Period: 2.500ns + Max period limit: 1000.000ns (1.000MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD TIMEGRP +"ftop_dram0_memc_memc_clk_wr_i" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.230ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.730ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.995ns (Levels of Logic = 1) + Clock Path Delay: 1.250ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.369 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X91Y41.DX net (fanout=1) 0.622 gmii_rxd_7_IBUF + SLICE_X91Y41.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 0.995ns (0.373ns logic, 0.622ns route) + (37.5% logic, 62.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.335 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.250ns (0.774ns logic, 0.476ns route) + (61.9% logic, 38.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.549ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.544ns (Levels of Logic = 1) + Clock Path Delay: 2.470ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.669 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X91Y41.DX net (fanout=1) 1.014 gmii_rxd_7_IBUF + SLICE_X91Y41.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.544ns (0.530ns logic, 1.014ns route) + (34.3% logic, 65.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.859 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.470ns (1.227ns logic, 1.243ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.188ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.688ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.037ns (Levels of Logic = 1) + Clock Path Delay: 1.250ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.374 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X91Y41.CX net (fanout=1) 0.659 gmii_rxd_6_IBUF + SLICE_X91Y41.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.037ns (0.378ns logic, 0.659ns route) + (36.5% logic, 63.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.335 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.250ns (0.774ns logic, 0.476ns route) + (61.9% logic, 38.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.637ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.632ns (Levels of Logic = 1) + Clock Path Delay: 2.470ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.672 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X91Y41.CX net (fanout=1) 1.099 gmii_rxd_6_IBUF + SLICE_X91Y41.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.632ns (0.533ns logic, 1.099ns route) + (32.7% logic, 67.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.859 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.470ns (1.227ns logic, 1.243ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.224ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.724ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.001ns (Levels of Logic = 1) + Clock Path Delay: 1.250ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.390 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X91Y41.BX net (fanout=1) 0.607 gmii_rxd_5_IBUF + SLICE_X91Y41.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.001ns (0.394ns logic, 0.607ns route) + (39.4% logic, 60.6% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.335 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.250ns (0.774ns logic, 0.476ns route) + (61.9% logic, 38.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.553ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.548ns (Levels of Logic = 1) + Clock Path Delay: 2.470ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.686 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X91Y41.BX net (fanout=1) 1.001 gmii_rxd_5_IBUF + SLICE_X91Y41.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.548ns (0.547ns logic, 1.001ns route) + (35.3% logic, 64.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.859 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.470ns (1.227ns logic, 1.243ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.290ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.790ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.935ns (Levels of Logic = 1) + Clock Path Delay: 1.250ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.433 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X91Y41.AX net (fanout=1) 0.498 gmii_rxd_4_IBUF + SLICE_X91Y41.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 0.935ns (0.437ns logic, 0.498ns route) + (46.7% logic, 53.3% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.335 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.250ns (0.774ns logic, 0.476ns route) + (61.9% logic, 38.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.442ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.437ns (Levels of Logic = 1) + Clock Path Delay: 2.470ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.723 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X91Y41.AX net (fanout=1) 0.853 gmii_rxd_4_IBUF + SLICE_X91Y41.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.437ns (0.584ns logic, 0.853ns route) + (40.6% logic, 59.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y41.CLK net (fanout=48) 0.859 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.470ns (1.227ns logic, 1.243ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.283ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.783ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.988ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.435 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X88Y38.DX net (fanout=1) 0.558 gmii_rxd_3_IBUF + SLICE_X88Y38.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 0.988ns (0.430ns logic, 0.558ns route) + (43.5% logic, 56.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.462ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.509ns (Levels of Logic = 1) + Clock Path Delay: 2.522ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.725 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X88Y38.DX net (fanout=1) 0.952 gmii_rxd_3_IBUF + SLICE_X88Y38.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.509ns (0.557ns logic, 0.952ns route) + (36.9% logic, 63.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.911 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.522ns (1.227ns logic, 1.295ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.379ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.879ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.892ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.375 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X88Y38.CX net (fanout=1) 0.522 gmii_rxd_2_IBUF + SLICE_X88Y38.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 0.892ns (0.370ns logic, 0.522ns route) + (41.5% logic, 58.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.351ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.398ns (Levels of Logic = 1) + Clock Path Delay: 2.522ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.673 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X88Y38.CX net (fanout=1) 0.893 gmii_rxd_2_IBUF + SLICE_X88Y38.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.398ns (0.505ns logic, 0.893ns route) + (36.1% logic, 63.9% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.911 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.522ns (1.227ns logic, 1.295ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.344ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.844ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.927ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.381 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X88Y38.BX net (fanout=1) 0.551 gmii_rxd_1_IBUF + SLICE_X88Y38.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 0.927ns (0.376ns logic, 0.551ns route) + (40.6% logic, 59.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.385ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.432ns (Levels of Logic = 1) + Clock Path Delay: 2.522ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.678 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X88Y38.BX net (fanout=1) 0.922 gmii_rxd_1_IBUF + SLICE_X88Y38.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.432ns (0.510ns logic, 0.922ns route) + (35.6% logic, 64.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.911 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.522ns (1.227ns logic, 1.295ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.384ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.884ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.887ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.435 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X88Y38.AX net (fanout=1) 0.457 gmii_rxd_0_IBUF + SLICE_X88Y38.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 0.887ns (0.430ns logic, 0.457ns route) + (48.5% logic, 51.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.287ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.334ns (Levels of Logic = 1) + Clock Path Delay: 2.522ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.725 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X88Y38.AX net (fanout=1) 0.777 gmii_rxd_0_IBUF + SLICE_X88Y38.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.334ns (0.557ns logic, 0.777ns route) + (41.8% logic, 58.2% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X88Y38.CLK net (fanout=48) 0.911 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.522ns (1.227ns logic, 1.295ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.254ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.754ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.016ns (Levels of Logic = 1) + Clock Path Delay: 1.295ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.425 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X89Y31.AX net (fanout=1) 0.587 gmii_rx_dv_IBUF + SLICE_X89Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.016ns (0.429ns logic, 0.587ns route) + (42.2% logic, 57.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X89Y31.CLK net (fanout=48) 0.380 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.295ns (0.774ns logic, 0.521ns route) + (59.8% logic, 40.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.524ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.568ns (Levels of Logic = 1) + Clock Path Delay: 2.519ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.716 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X89Y31.AX net (fanout=1) 0.991 gmii_rx_dv_IBUF + SLICE_X89Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.568ns (0.577ns logic, 0.991ns route) + (36.8% logic, 63.2% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X89Y31.CLK net (fanout=48) 0.908 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.519ns (1.227ns logic, 1.292ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.432ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.932ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.839ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.393 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X91Y37.DX net (fanout=1) 0.442 gmii_rx_er_IBUF + SLICE_X91Y37.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 0.839ns (0.397ns logic, 0.442ns route) + (47.3% logic, 52.7% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y37.CLK net (fanout=48) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.263ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.311ns (Levels of Logic = 1) + Clock Path Delay: 2.523ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.689 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X91Y37.DX net (fanout=1) 0.761 gmii_rx_er_IBUF + SLICE_X91Y37.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 1.311ns (0.550ns logic, 0.761ns route) + (42.0% logic, 58.0% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X91Y37.CLK net (fanout=48) 0.912 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.523ns (1.227ns logic, 1.296ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Pin to Pin Skew Constraint; + + 1 path analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- +Slack: 0.108ns (maxskew - uncertainty - (arrival1 - arrival2)) + Max skew: 0.450ns + Arrival 1: 2.658ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Arrival 2: 2.505ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/USERCLK + Clock Uncertainty: 0.189ns + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.881ns| 5.130ns| 0| 5| 91995| 75760| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.130ns| N/A| 5| 0| 75760| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.392ns| 0| 99| 0| 12130285| +| TS_CLK_125 | 8.000ns| 8.784ns| N/A| 91| 0| 12110988| 0| +| TS_CLK_250 | 4.000ns| 4.049ns| N/A| 8| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock gmii_rx_clk +------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +------------+------------+------------+------------+------------+------------------+--------+ +gmii_rx_dv | -0.254(R)| FAST | 0.976(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rx_er | -0.432(R)| FAST | 1.237(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<0> | -0.384(R)| FAST | 1.213(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<1> | -0.344(R)| FAST | 1.115(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<2> | -0.379(R)| FAST | 1.149(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<3> | -0.283(R)| FAST | 1.038(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<4> | -0.290(R)| FAST | 1.058(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<5> | -0.224(R)| FAST | 0.947(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<6> | -0.188(R)| FAST | 0.863(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<7> | -0.230(R)| FAST | 0.951(R)| SLOW |ftop/rxclkBnd | 0.000| +------------+------------+------------+------------+------------+------------------+--------+ + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 4.665| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.130| | | | +sys0_clkp | 5.130| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.130| | | | +sys0_clkp | 5.130| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 6.970| | | | +sys1_clkp | 6.970| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 6.970| | | | +sys1_clkp | 6.970| | | | +---------------+---------+---------+---------+---------+ + +COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.721; Ideal Clock Offset To Actual Clock 0.410; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<7> | -0.230(R)| FAST | 0.951(R)| SLOW | 0.730| 1.549| -0.410| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.230| - | 0.951| - | 0.730| 1.549| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.675; Ideal Clock Offset To Actual Clock 0.475; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<6> | -0.188(R)| FAST | 0.863(R)| SLOW | 0.688| 1.637| -0.475| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.188| - | 0.863| - | 0.688| 1.637| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.723; Ideal Clock Offset To Actual Clock 0.415; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<5> | -0.224(R)| FAST | 0.947(R)| SLOW | 0.724| 1.553| -0.415| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.224| - | 0.947| - | 0.724| 1.553| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.768; Ideal Clock Offset To Actual Clock 0.326; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<4> | -0.290(R)| FAST | 1.058(R)| SLOW | 0.790| 1.442| -0.326| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.290| - | 1.058| - | 0.790| 1.442| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.755; Ideal Clock Offset To Actual Clock 0.339; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<3> | -0.283(R)| FAST | 1.038(R)| SLOW | 0.783| 1.462| -0.339| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.283| - | 1.038| - | 0.783| 1.462| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.770; Ideal Clock Offset To Actual Clock 0.236; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<2> | -0.379(R)| FAST | 1.149(R)| SLOW | 0.879| 1.351| -0.236| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.379| - | 1.149| - | 0.879| 1.351| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.771; Ideal Clock Offset To Actual Clock 0.271; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<1> | -0.344(R)| FAST | 1.115(R)| SLOW | 0.844| 1.385| -0.271| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.344| - | 1.115| - | 0.844| 1.385| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.829; Ideal Clock Offset To Actual Clock 0.201; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<0> | -0.384(R)| FAST | 1.213(R)| SLOW | 0.884| 1.287| -0.201| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.384| - | 1.213| - | 0.884| 1.287| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.722; Ideal Clock Offset To Actual Clock 0.385; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_dv | -0.254(R)| FAST | 0.976(R)| SLOW | 0.754| 1.524| -0.385| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.254| - | 0.976| - | 0.754| 1.524| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.805; Ideal Clock Offset To Actual Clock 0.165; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_er | -0.432(R)| FAST | 1.237(R)| SLOW | 0.932| 1.263| -0.165| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.432| - | 1.237| - | 0.932| 1.263| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + + +Timing summary: +--------------- + +Timing errors: 104 Score: 19449 (Setup/Max: 19394, Hold: 55) + +Constraints cover 12307634 paths, 0 nets, and 214068 connections + +Design statistics: + Minimum period: 8.784ns{1} (Maximum frequency: 113.843MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Sun Jan 26 16:01:54 2014 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 1653 MB + + + diff --git a/logs/ml605-20140126_1604/fpgaTop_map.mrp b/logs/ml605-20140126_1604/fpgaTop_map.mrp new file mode 100644 index 00000000..f6f81210 --- /dev/null +++ b/logs/ml605-20140126_1604/fpgaTop_map.mrp @@ -0,0 +1,8344 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc6vlx240t-ff1156-1 -w -logic_opt on -xe n -mt on -t 1 -register_duplication on -ir off -pr off +-lc off -power off -o fpgaTop_map.ncd fpgaTop.ngd fpgaTop.pcf +Target Device : xc6vlx240t +Target Package : ff1156 +Target Speed : -1 +Mapper Version : virtex6 -- $Revision: 1.55 $ +Mapped Date : Sun Jan 26 15:36:05 2014 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 599 +Slice Logic Utilization: + Number of Slice Registers: 33,948 out of 301,440 11% + Number used as Flip Flops: 33,941 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 42,307 out of 150,720 28% + Number used as logic: 36,455 out of 150,720 24% + Number using O6 output only: 32,879 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,166 + Number used as ROM: 0 + Number used as Memory: 5,075 out of 58,400 8% + Number used as Dual Port RAM: 2,098 + Number using O6 output only: 106 + Number using O5 output only: 53 + Number using O5 and O6: 1,939 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 777 + Number with same-slice register load: 646 + Number with same-slice carry load: 129 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,628 out of 37,680 44% + Number of LUT Flip Flop pairs used: 50,165 + Number with an unused Flip Flop: 17,229 out of 50,165 34% + Number with an unused LUT: 7,858 out of 50,165 15% + Number of fully used LUT-FF pairs: 25,078 out of 50,165 49% + Number of unique control sets: 1,980 + Number of slice register sites lost + to control set restrictions: 9,539 out of 301,440 3% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + +Average Fanout of Non-Clock Nets: 4.07 + +Peak Memory Usage: 2436 MB +Total REAL time to MAP completion: 17 mins 26 secs +Total CPU time to MAP completion (all processors): 18 mins 8 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_10_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_11_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_12_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_13_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_14_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_15_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_0_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_1_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_2_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_3_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_4_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_5_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_6_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_7_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_8_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_9_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. + The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:2045 - The MMCM_ADV block has CLKOUT pins + that do not drive the same kind of BUFFER load. Routing from the different buffer types will not be phase aligned. + +Section 3 - Informational +------------------------- +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network N100 has no load. +INFO:LIT:395 - The above info message is repeated 4269 more times for the + following (max. 5 shown): + N101, + N102, + N103, + N104, + N105 + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to + 1.050 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_7) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_8) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_9" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_9) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_10" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_10) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_11" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_11) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_12" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_12) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_13" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_13) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_14" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_14) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_15" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_15) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_16" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_16) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_17" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_17) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_18" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_19" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_19) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_20) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_21) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_22) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_23) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_24" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_24) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_25" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_25) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_26" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_26) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 378 block(s) removed + 418 block(s) optimized away +1789 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +Loadless block "ftop/ctop/inf/cpTlp/Msub_byteCount__h207611" (ROM) removed. +Loadless block "ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block "ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram +[0].RAM32M0" (RAM32M) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<4>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<3>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<2>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<1>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<0>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_0" (FF) removed. +Loadless block "ftop/gbe0/gmac/gmii_rx_clk" (BUFIODQS) removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<31>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<30>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<29>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<28>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<27>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<26>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<25>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<24>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<23>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<22>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<21>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<20>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<19>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<18>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<17>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<16>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<7>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<6>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<5>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<4>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<3>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<2>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tcfg_req_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_terr_drop_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rsrc_dsc_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rerrfwd_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_rd_wr_done_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_err_cpl_rdy_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_rdy_n" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msienable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixenable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixfm" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_en" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_status" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_gen2_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_partner_gen2_supported" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_upcfg_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_received_hot_rst" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCCHECKEN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCGENEN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGERRAERHEADERLOGSETN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRCOR" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRNONFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMASNAK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETO" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETOACK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMPME" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDSETSLOTPOWERLIMIT" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDUNLOCK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVASREQL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL23N" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVREQACKN" is sourceless +and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGSLOTCONTROLELECTROMECHILCTLPULSE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTION" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONTYPE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRA" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRB" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRC" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRD" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRE" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRF" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRG" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRH" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRI" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRJ" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRK" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDRDY" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/LNKCLKEN" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRESET" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLPHYLNKUPN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/RECEIVEDFUNCLVLRSTN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNRECRCERRN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNTDLLPDSTRDYN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<15>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<14>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<13>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<12>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<11>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<10>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<9>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<8>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<7>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<0>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<31>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<30>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<29>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<28>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<27>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<26>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<25>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<24>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<23>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<22>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<21>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<20>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<19>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<18>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<17>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<16>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<47>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<46>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<45>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<44>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<43>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<42>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<41>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<40>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<39>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<38>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<37>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<36>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<35>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<34>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<33>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<32>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<63>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<62>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<61>" is +sourceless and has been removed. +The signal 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"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<8>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<7>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<6>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<5>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<4>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<3>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<2>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<1>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<0>" +is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/inv_dqs<0>1 +" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<97>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<99>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<100>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<101>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<102>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<103>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<104>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<105>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<106>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<107>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<160>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<161>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<162>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<163>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<164>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<165>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<166>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<167>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<168>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<169>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<170>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<171>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<172>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<173>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<174>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<175>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<176>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<177>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<178>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<179>" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_infrastructure/PSDONE" is sourceless and has +been removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[100].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[101].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[102].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[103].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[104].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[105].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[106].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[107].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[97].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[99].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[160].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[161].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[162].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[163].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[164].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[165].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[166].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[167].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[168].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[169].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[170].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[171].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[172].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[173].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[174].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[175].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[176].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[177].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[178].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[179].u_RAM64X1D" (RAM64X1D) removed. +Unused block "ftop/dram0/memc_memc/XST_GND" (ZERO) removed. +Unused block "ftop/dram0/memc_memc/XST_VCC" (ONE) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/u_out_ +parity" (OSERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. + +Optimized Block(s): +TYPE BLOCK +VCC XST_VCC +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/cap0/XST_GND +VCC ftop/cap0/XST_VCC +GND ftop/cap0/dataBram_0_memory/XST_GND +VCC ftop/cap0/dataBram_0_memory/XST_VCC +GND ftop/cap0/dataBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_0_memory/XST_GND +VCC ftop/cap0/metaBram_0_memory/XST_VCC +GND ftop/cap0/metaBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_1_memory/XST_GND +VCC ftop/cap0/metaBram_1_memory/XST_VCC +GND ftop/cap0/metaBram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_2_memory/XST_GND +VCC ftop/cap0/metaBram_2_memory/XST_VCC +GND ftop/cap0/metaBram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_3_memory/XST_GND +VCC ftop/cap0/metaBram_3_memory/XST_VCC +GND ftop/cap0/metaBram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/wci_wslv_reqF/XST_GND +GND ftop/cap0/wsiS_reqFifo/XST_GND +VCC ftop/cap0/wsiS_reqFifo/XST_VCC +GND ftop/ctop/app/XST_GND +GND ftop/ctop/app/appW1/XST_GND +VCC ftop/ctop/app/appW1/XST_VCC +GND ftop/ctop/app/appW1/rgen_gsF/XST_GND +GND ftop/ctop/app/appW1/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW2/XST_GND +VCC ftop/ctop/app/appW2/XST_VCC +GND ftop/ctop/app/appW2/respF_memory/XST_GND +VCC ftop/ctop/app/appW2/respF_memory/XST_VCC +GND ftop/ctop/app/appW2/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/XST_GND +VCC ftop/ctop/app/appW3/XST_VCC +GND ftop/ctop/app/appW3/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/appW4/XST_GND +VCC ftop/ctop/app/appW4/XST_VCC +GND ftop/ctop/app/appW4/respF_memory/XST_GND +VCC ftop/ctop/app/appW4/respF_memory/XST_VCC +GND ftop/ctop/app/appW4/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW4/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/id/XST_GND +VCC ftop/ctop/app/id/XST_VCC +GND ftop/ctop/inf/cp/XST_GND +VCC ftop/ctop/inf/cp/XST_VCC +GND ftop/ctop/inf/cp/bluart/XST_GND +VCC ftop/ctop/inf/cp/bluart/XST_VCC +GND ftop/ctop/inf/cp/rom_memory/XST_GND +VCC ftop/ctop/inf/cp/rom_memory/XST_VCC +GND ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/ctop/inf/cp/timeServ_setRefF/XST_GND +VCC ftop/ctop/inf/cp/wci_10_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_11_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_12_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_13_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_14_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_1_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_2_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_3_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_4_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_8_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_9_mReset/rstSync/XST_VCC +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h207610 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20762 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20763 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20764 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20765 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20766 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20767 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20768 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20769 + optimized to 1 +GND ftop/ctop/inf/cpTlp/XST_GND +VCC ftop/ctop/inf/cpTlp/XST_VCC +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp0/XST_GND +VCC ftop/ctop/inf/dp0/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/wci_reqF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_reqF/XST_GND +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp1/XST_GND +VCC ftop/ctop/inf/dp1/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/wci_reqF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_dhF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_reqF/XST_GND +GND ftop/dram0/XST_GND +VCC ftop/dram0/XST_VCC +GND ftop/dram0/dbg_dqs_n_tap_cnt/XST_GND +GND ftop/dram0/dbg_dqs_p_tap_cnt/XST_GND +GND ftop/dram0/dbg_rdlvl_err/XST_GND +GND ftop/dram0/lreqF/XST_GND +GND ftop/dram0/lrespF/XST_GND +GND ftop/dram0/memc_memc/u_infrastructure/XST_GND +VCC ftop/dram0/memc_memc/u_infrastructure/XST_VCC +GND ftop/dram0/memc_memc/u_iodelay_ctrl/XST_GND +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_state0/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd +_top/gen_pd[0].gen_pd_inst.u_phy_pd/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wr +lvl/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_G +ND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_V +CC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctr +l_sync/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_VCC +VCC ftop/dram0/memc_rst_stretch_n/XST_VCC +GND ftop/dram0/wci_wslv_reqF/XST_GND +GND ftop/flash0/XST_GND +VCC ftop/flash0/XST_VCC +GND ftop/flash0/wci_wslv_reqF/XST_GND +GND ftop/fmc150/XST_GND +VCC ftop/fmc150/XST_VCC +VCC ftop/fmc150/fcCdc_testRst/XST_VCC +VCC ftop/fmc150/spiCDC_slowReset/XST_VCC +VCC ftop/fmc150/spiDAC_slowReset/XST_VCC +GND ftop/fmc150/wci_wslv_reqF/XST_GND +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/rxRS_rxRst/XST_VCC +GND ftop/gbe0/gmac/txRS_txF/XST_GND +VCC ftop/gbe0/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbe0/wci_wslv_reqF/XST_GND +GND ftop/lcd_ctrl/XST_GND +VCC ftop/lcd_ctrl/XST_VCC +GND ftop/pciw_fI2P/XST_GND +GND ftop/pciw_fP2I/XST_GND +VCC ftop/pciw_p125rst/XST_VCC +VCC ftop/pciw_p250rst/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_VCC +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/XS +T_GND +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_VCC +VCC ftop/sys0_rst/XST_VCC +LUT2 ftop/ctop/inf/noc_sm2/pktFork/fo1/Result<2>_SW0 + optimized to 0 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ddr3_addr<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<8> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<9> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<10> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<11> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<12> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cas_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ck_n<0> | IOBS | OUTPUT | DIFF_SSTL15 | | | | | | | +| ddr3_ck_p<0> | IOBM | OUTPUT | DIFF_SSTL15 | | | | OSERDES | | | +| ddr3_cke<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cs_n<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_dm<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dq<0> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<1> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<2> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<3> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<4> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<5> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<6> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<7> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<8> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<9> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<10> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<11> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<12> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<13> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<14> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<15> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<16> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<17> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<18> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<19> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<20> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<21> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<22> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<23> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<24> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<25> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<26> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<27> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<28> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<29> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<30> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<31> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<32> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<33> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<34> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<35> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<36> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<37> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<38> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<39> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<40> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<41> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<42> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<43> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<44> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<45> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<46> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<47> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<48> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<49> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<50> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<51> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<52> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<53> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<54> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<55> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<56> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<57> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<58> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<59> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<60> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<61> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<62> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<63> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_n<0> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<1> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<2> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<3> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<4> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<5> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<6> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<7> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_p<0> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_p<1> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<2> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<3> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<4> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<5> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<6> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<7> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_odt<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ras_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_reset_n | IOB | OUTPUT | SSTL15 | | | | ODDR | | | +| ddr3_we_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| flash_addr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_ce_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_oe_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_wait | IOB | INPUT | LVCMOS25 | | | | | | | +| flash_we_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_clk_n | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_clk_p | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_pdn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_refen | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| flp_com_sclk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_com_sdc2m | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| gmii_rx_clk | IOB | INPUT | LVCMOS25 | | | | | | FIXED | +| gmii_rx_dv | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rx_er | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<7> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| lcd_db<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_e | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rw | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdd | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| pci0_clkn | IPAD | INPUT | | | | | | | | +| pci0_clkp | IPAD | INPUT | | | | | | | | +| pci0_reset_n | IOB | INPUT | LVCMOS25 | | | | | PULLUP | | +| pci_exp_rxn<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<3> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<3> | IPAD | INPUT | | | | | | | | +| pci_exp_txn<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<3> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<3> | OPAD | OUTPUT | | | | | | | | +| ppsExtIn | IOB | INPUT | LVCMOS25 | | | | | | | +| ppsOut | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| sys0_clkn | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys0_clkp | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys1_clkn | IPAD | INPUT | | | | | | | | +| sys1_clkp | IPAD | INPUT | | | | | | | | +| upads_cts_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_rts | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| upads_rx_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_tx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_pcie0" + No COMPRESSION specified for Area Group "AG_pcie0" + RANGE: SLICE_X136Y147:SLICE_X155Y120 + Slice Logic Utilization: + Number of Slice Registers: 456 out of 4,480 10% + Number of Slice LUTs: 669 out of 2,240 29% + Number used as logic: 662 + Number used as Memory: 7 + Slice Logic Distribution: + Number of occupied Slices: 270 out of 560 48% + Number of LUT Flip Flop pairs used: 749 + Number with an unused Flip Flop: 321 out of 749 42% + Number with an unused LUT: 68 out of 749 9% + Number of fully used LUT-FF pairs: 360 out of 749 48% + Number of RAMB36E1/FIFO36E1s: 8 + Number using RAMB36E1 only: 8 + Number using FIFO36E1 only: 0 + + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/logs/ml605-20140127_1142/fpgaTop-ml605.srp b/logs/ml605-20140127_1142/fpgaTop-ml605.srp new file mode 100644 index 00000000..b2284fe2 --- /dev/null +++ b/logs/ml605-20140127_1142/fpgaTop-ml605.srp @@ -0,0 +1,13979 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter xsthdpini set to ocpihdp_v6.ini + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-ml605.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc6vlx240t-ff1156-1 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +LUT Combining : off +Reduce Control Sets : off +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Power Reduction : NO +Library Search Order : fpgaTop.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +---- Other Options +change_error_to_warning : "HDLCompiler:532 HDLCompiler:597" + +========================================================================= + +INFO:Xst - Changing 'HDLCompiler:532' to warning +INFO:Xst - Changing 'HDLCompiler:597' to warning + +========================================================================= +* HDL Parsing * +========================================================================= +The vhdl library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +The veri library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFO.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/Ethernet_v6_v1_5.v" into library work +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" Line 85. parameter declaration becomes local in pcie_upconfig_fix_3451_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" Line 76. parameter declaration becomes local in pcie_reset_delay_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" Line 120. parameter declaration becomes local in pcie_brams_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" Line 216. parameter declaration becomes local in pcie_gtx_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 325. parameter declaration becomes local in pcie_pipe_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" Line 103. parameter declaration becomes local in pcie_pipe_lane_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" Line 90. parameter declaration becomes local in pcie_pipe_misc_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 85. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 87. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 88. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 89. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 90. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 91. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 93. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 94. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 95. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 96. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 107. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 108. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 109. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 110. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 90. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 91. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 92. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 93. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 94. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 95. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 96. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 97. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 98. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 99. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 100. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTimeClient.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCRC32.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGMAC.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkICAPWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 200. parameter declaration becomes local in mc with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_buf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_dec_fix.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into library work +Parsing module . +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" into library work +Parsing module . +WARNING:HDLCompiler:751 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 271: Redeclaration of ansi port app_addr is not allowed +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPCM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktFork.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktMerge.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkUUID.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCCP.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWciMonitor.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFMC150.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkLCDController.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" into library work +Parsing module . + +========================================================================= +* HDL Elaboration * +========================================================================= +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Port flash_wp_n is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1440: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1472: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1473: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1480: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1481: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1482: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1483: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1484: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1488: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1489: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1490: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1491: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1492: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1493: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1494: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1495: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1496: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1497: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1506: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1507: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1508: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1509: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1510: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1514: Assignment to wtiS_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1515: Assignment to wtiS_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1516: Assignment to wtiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1517: Assignment to wtiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1519: Assignment to nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1520: Assignment to statusReg_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1521: Assignment to statusReg_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1522: Assignment to dataBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1529: Assignment to dataBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1533: Assignment to dataBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1537: Assignment to dataBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1538: Assignment to dataBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1539: Assignment to dataBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1540: Assignment to dataBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1541: Assignment to dataBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1542: Assignment to dataBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1543: Assignment to dataBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1544: Assignment to dataBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1546: Assignment to dataBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1547: Assignment to dataBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1548: Assignment to dataBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1555: Assignment to dataBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1560: Assignment to dataBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1561: Assignment to dataBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1563: Assignment to dataBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1564: Assignment to dataBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1566: Assignment to dataBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1567: Assignment to dataBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1568: Assignment to dataBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1569: Assignment to dataBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1571: Assignment to dataBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1572: Assignment to dataBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1574: Assignment to metaBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1581: Assignment to metaBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1585: Assignment to metaBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1589: Assignment to metaBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1590: Assignment to metaBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1591: Assignment to metaBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1592: Assignment to metaBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1593: Assignment to metaBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1594: Assignment to metaBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1595: Assignment to metaBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1596: Assignment to metaBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1598: Assignment to metaBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1599: Assignment to metaBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1600: Assignment to metaBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1607: Assignment to metaBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1612: Assignment to metaBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1613: Assignment to metaBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1615: Assignment to metaBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1616: Assignment to metaBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1618: Assignment to metaBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1619: Assignment to metaBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1620: Assignment to metaBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1621: Assignment to metaBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1623: Assignment to metaBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1624: Assignment to metaBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1626: Assignment to metaBram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1633: Assignment to metaBram_1_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1637: Assignment to metaBram_1_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1640: Assignment to metaBram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1641: Assignment to metaBram_1_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1642: Assignment to metaBram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1643: Assignment to metaBram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1644: Assignment to metaBram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1645: Assignment to metaBram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1646: Assignment to metaBram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1647: Assignment to metaBram_1_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1649: Assignment to metaBram_1_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1650: Assignment to metaBram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1651: Assignment to metaBram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1658: Assignment to metaBram_1_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1663: Assignment to metaBram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1664: Assignment to metaBram_1_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1666: Assignment to metaBram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1671: Assignment to metaBram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1672: Assignment to metaBram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1673: Assignment to metaBram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1674: Assignment to metaBram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1676: Assignment to metaBram_1_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1677: Assignment to metaBram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1679: Assignment to metaBram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1686: Assignment to metaBram_2_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1690: Assignment to metaBram_2_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1694: Assignment to metaBram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1695: Assignment to metaBram_2_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1696: Assignment to metaBram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1697: Assignment to metaBram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1698: Assignment to metaBram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1699: Assignment to metaBram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1700: Assignment to metaBram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1701: Assignment to metaBram_2_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1703: Assignment to metaBram_2_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1704: Assignment to metaBram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1705: Assignment to metaBram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1712: Assignment to metaBram_2_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1717: Assignment to metaBram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1718: Assignment to metaBram_2_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1720: Assignment to metaBram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1721: Assignment to metaBram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1723: Assignment to metaBram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1724: Assignment to metaBram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1725: Assignment to metaBram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1726: Assignment to metaBram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1728: Assignment to metaBram_2_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1729: Assignment to metaBram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1731: Assignment to metaBram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1738: Assignment to metaBram_3_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1742: Assignment to metaBram_3_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1746: Assignment to metaBram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1747: Assignment to metaBram_3_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1748: Assignment to metaBram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1749: Assignment to metaBram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1750: Assignment to metaBram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1751: Assignment to metaBram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1752: Assignment to metaBram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1753: Assignment to metaBram_3_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1755: Assignment to metaBram_3_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1756: Assignment to metaBram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1757: Assignment to metaBram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1764: Assignment to metaBram_3_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1769: Assignment to metaBram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1770: Assignment to metaBram_3_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1772: Assignment to metaBram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1773: Assignment to metaBram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1775: Assignment to metaBram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1776: Assignment to metaBram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1777: Assignment to metaBram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1778: Assignment to metaBram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1780: Assignment to metaBram_3_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1781: Assignment to metaBram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1783: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1784: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1785: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1786: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1787: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1788: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1789: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1790: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1791: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1792: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1793: Assignment to wti_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1794: Assignment to wti_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1795: Assignment to wti_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1796: Assignment to wti_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1797: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1801: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1808: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1809: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1819: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1820: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1822: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1823: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1824: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1826: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1827: Assignment to dataBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1831: Assignment to metaBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1836: Assignment to metaBram_1_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1837: Assignment to metaBram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1839: Assignment to metaBram_2_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1844: Assignment to metaBram_3_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1849: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1850: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1851: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2108: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2132: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2692: Assignment to isFirst ignored, since the identifier is never used +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1519: Port EN_uuid is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 829: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 883: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 884: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 888: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 889: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 890: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 891: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 892: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 896: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 897: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 898: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 899: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 900: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 901: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 902: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 903: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 904: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 905: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 906: Assignment to wmemi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 909: Assignment to wmemi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 910: Assignment to wmemi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 913: Assignment to wmemi_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 914: Assignment to wmemi_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 915: Assignment to wmemi_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 916: Assignment to wmemi_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 917: Assignment to wmemi_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 918: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 919: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 920: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 921: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 922: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 923: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 924: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 925: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 926: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 930: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 934: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 935: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 949: Assignment to wmemi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 952: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1120: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1144: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1238: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1286: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1307: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1434: Assignment to respCnt ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 787: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 830: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 831: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 835: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 836: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 837: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 838: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 839: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 843: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 844: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 845: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 846: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 847: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 848: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 849: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 850: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 851: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 852: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 861: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 862: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 863: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 864: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 865: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 869: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 870: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 872: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 873: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 874: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 875: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 876: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 877: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 878: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 879: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 880: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 881: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 882: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 883: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 884: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 885: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 886: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 890: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 894: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 895: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 905: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 906: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 908: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 909: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 910: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 912: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 913: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 915: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 916: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 917: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 918: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 919: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1019: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1043: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1128: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1152: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1349: Assignment to wci_wslv_cEdge ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1743: Assignment to tieOff0_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1744: Assignment to tieOff0_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1745: Assignment to tieOff0_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1746: Assignment to tieOff0_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1747: Assignment to tieOff0_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1748: Assignment to tieOff0_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1749: Assignment to tieOff0_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1750: Assignment to tieOff0_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1751: Assignment to tieOff0_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1752: Assignment to tieOff0_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1753: Assignment to tieOff5_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1754: Assignment to tieOff5_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1755: Assignment to tieOff5_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1756: Assignment to tieOff5_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1757: Assignment to tieOff5_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1758: Assignment to tieOff5_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1759: Assignment to tieOff5_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1760: Assignment to tieOff5_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1761: Assignment to tieOff5_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1762: Assignment to tieOff5_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1763: Assignment to tieOff6_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1764: Assignment to tieOff6_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1765: Assignment to tieOff6_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1766: Assignment to tieOff6_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1767: Assignment to tieOff6_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1768: Assignment to tieOff6_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1769: Assignment to tieOff6_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1770: Assignment to tieOff6_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1771: Assignment to tieOff6_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1772: Assignment to tieOff6_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1773: Assignment to tieOff7_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1774: Assignment to tieOff7_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1775: Assignment to tieOff7_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1776: Assignment to tieOff7_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1777: Assignment to tieOff7_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1778: Assignment to tieOff7_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1779: Assignment to tieOff7_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1780: Assignment to tieOff7_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1781: Assignment to tieOff7_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1782: Assignment to tieOff7_wci_Es_mData_w_whas ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBLUART.v" Line 343: Assignment to rxCtsReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9534: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9609: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9686: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9763: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9840: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9917: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9997: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10073: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10149: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10225: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10301: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10377: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10453: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10529: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10605: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10649: Assignment to warmResetP_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10650: Assignment to warmResetP_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10651: Assignment to timeServ_jamFrac_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10654: Assignment to timeServ_jamFracVal_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10655: Assignment to timeServ_jamFracVal_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10656: Assignment to deviceDNA_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10657: Assignment to deviceDNA_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10660: Assignment to devDNAV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10661: Assignment to rom_serverAdapter_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10675: Assignment to rom_serverAdapter_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10676: Assignment to rom_serverAdapter_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10678: Assignment to rom_serverAdapter_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10679: Assignment to rom_serverAdapter_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10681: Assignment to rom_serverAdapter_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10682: Assignment to rom_serverAdapter_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10683: Assignment to rom_serverAdapter_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10684: Assignment to rom_serverAdapter_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10686: Assignment to rom_serverAdapter_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10687: Assignment to rom_serverAdapter_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10689: Assignment to dna_rdReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10691: Assignment to dna_shftReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10693: Assignment to uuidV_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10694: Assignment to uuidV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10695: Assignment to wci_0_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10701: Assignment to wci_0_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10702: Assignment to wci_0_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10703: Assignment to wci_0_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10704: Assignment to wci_0_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10708: Assignment to wci_1_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10714: Assignment to wci_1_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10715: Assignment to wci_1_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10716: Assignment to wci_1_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10717: Assignment to wci_1_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10721: Assignment to wci_2_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10727: Assignment to wci_2_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10728: Assignment to wci_2_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10729: Assignment to wci_2_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10730: Assignment to wci_2_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10734: Assignment to wci_3_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10740: Assignment to wci_3_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10741: Assignment to wci_3_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10742: Assignment to wci_3_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10743: Assignment to wci_3_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10747: Assignment to wci_4_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10753: Assignment to wci_4_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10754: Assignment to wci_4_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10755: Assignment to wci_4_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10756: Assignment to wci_4_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10760: Assignment to wci_5_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10766: Assignment to wci_5_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10767: Assignment to wci_5_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10768: Assignment to wci_5_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10769: Assignment to wci_5_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10773: Assignment to wci_6_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10779: Assignment to wci_6_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10780: Assignment to wci_6_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10781: Assignment to wci_6_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10782: Assignment to wci_6_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10786: Assignment to wci_7_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10792: Assignment to wci_7_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10793: Assignment to wci_7_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10794: Assignment to wci_7_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10795: Assignment to wci_7_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10799: Assignment to wci_8_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10805: Assignment to wci_8_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10806: Assignment to wci_8_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10807: Assignment to wci_8_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10808: Assignment to wci_8_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10812: Assignment to wci_9_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10818: Assignment to wci_9_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10819: Assignment to wci_9_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10820: Assignment to wci_9_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10821: Assignment to wci_9_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10825: Assignment to wci_10_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10831: Assignment to wci_10_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10832: Assignment to wci_10_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10833: Assignment to wci_10_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10834: Assignment to wci_10_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10838: Assignment to wci_11_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10844: Assignment to wci_11_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10845: Assignment to wci_11_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10846: Assignment to wci_11_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10847: Assignment to wci_11_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10851: Assignment to wci_12_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10857: Assignment to wci_12_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10858: Assignment to wci_12_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10859: Assignment to wci_12_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10860: Assignment to wci_12_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10864: Assignment to wci_13_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10870: Assignment to wci_13_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10871: Assignment to wci_13_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10872: Assignment to wci_13_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10873: Assignment to wci_13_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10877: Assignment to wci_14_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10883: Assignment to wci_14_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10884: Assignment to wci_14_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10885: Assignment to wci_14_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10886: Assignment to wci_14_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10890: Assignment to wci_Emv_0_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10891: Assignment to wci_Emv_0_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10892: Assignment to wci_Emv_0_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10893: Assignment to wci_Emv_0_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10894: Assignment to wci_Emv_1_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10895: Assignment to wci_Emv_1_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10896: Assignment to wci_Emv_1_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10897: Assignment to wci_Emv_1_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10898: Assignment to wci_Emv_2_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10899: Assignment to wci_Emv_2_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10900: Assignment to wci_Emv_2_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10901: Assignment to wci_Emv_2_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10902: Assignment to wci_Emv_3_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10903: Assignment to wci_Emv_3_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10904: Assignment to wci_Emv_3_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10905: Assignment to wci_Emv_3_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10906: Assignment to wci_Emv_4_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10907: Assignment to wci_Emv_4_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10908: Assignment to wci_Emv_4_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10909: Assignment to wci_Emv_4_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10910: Assignment to wci_Emv_5_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10911: Assignment to wci_Emv_5_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10912: Assignment to wci_Emv_5_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10913: Assignment to wci_Emv_5_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10914: Assignment to wci_Emv_6_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10915: Assignment to wci_Emv_6_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10916: Assignment to wci_Emv_6_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10917: Assignment to wci_Emv_6_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10918: Assignment to wci_Emv_7_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10919: Assignment to wci_Emv_7_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10920: Assignment to wci_Emv_7_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10921: Assignment to wci_Emv_7_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10922: Assignment to wci_Emv_8_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10923: Assignment to wci_Emv_8_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10924: Assignment to wci_Emv_8_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10925: Assignment to wci_Emv_8_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10926: Assignment to wci_Emv_9_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10927: Assignment to wci_Emv_9_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10928: Assignment to wci_Emv_9_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10929: Assignment to wci_Emv_9_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10930: Assignment to wci_Emv_10_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10931: Assignment to wci_Emv_10_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10932: Assignment to wci_Emv_10_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10933: Assignment to wci_Emv_10_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10934: Assignment to wci_Emv_11_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10935: Assignment to wci_Emv_11_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10936: Assignment to wci_Emv_11_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10937: Assignment to wci_Emv_11_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10938: Assignment to wci_Emv_12_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10939: Assignment to wci_Emv_12_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10940: Assignment to wci_Emv_12_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10941: Assignment to wci_Emv_12_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10942: Assignment to wci_Emv_13_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10943: Assignment to wci_Emv_13_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10944: Assignment to wci_Emv_13_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10945: Assignment to wci_Emv_13_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10946: Assignment to wci_Emv_14_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10947: Assignment to wci_Emv_14_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10948: Assignment to wci_Emv_14_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10949: Assignment to wci_Emv_14_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10955: Assignment to wci_0_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10959: Assignment to wci_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10960: Assignment to wci_1_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10964: Assignment to wci_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10965: Assignment to wci_2_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10969: Assignment to wci_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10970: Assignment to wci_3_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10974: Assignment to wci_3_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10975: Assignment to wci_4_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10979: Assignment to wci_4_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10980: Assignment to wci_5_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10984: Assignment to wci_5_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10985: Assignment to wci_6_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10989: Assignment to wci_6_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10990: Assignment to wci_7_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10994: Assignment to wci_7_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10995: Assignment to wci_8_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10999: Assignment to wci_8_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11000: Assignment to wci_9_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11004: Assignment to wci_9_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11005: Assignment to wci_10_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11010: Assignment to wci_10_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11011: Assignment to wci_11_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11016: Assignment to wci_11_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11017: Assignment to wci_12_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11022: Assignment to wci_12_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11023: Assignment to wci_13_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11028: Assignment to wci_13_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11029: Assignment to wci_14_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 11034: Assignment to wci_14_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12327: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12349: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12514: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12702: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12724: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12890: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12912: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13078: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13266: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13288: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13453: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13475: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13639: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13661: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13825: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13847: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14011: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14033: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14197: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14219: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14383: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14405: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14569: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14591: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14755: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14777: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14941: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14963: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15051: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15363: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15550: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15607: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15665: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15723: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15781: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15839: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15897: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15954: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16011: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16068: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16125: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16182: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16239: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16296: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16353: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 24740: Assignment to warmResetP ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 25888: Assignment to timeServ_ppsExtCapture ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 118: Assignment to wti_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 119: Assignment to wti_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 120: Assignment to wti_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 140: Assignment to wti_peerIsReady ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 198: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 240: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1731: Assignment to wtiM_0_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1732: Assignment to wtiM_0_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1733: Assignment to wtiM_1_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1734: Assignment to wtiM_1_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1735: Assignment to wtiM_2_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1736: Assignment to wtiM_2_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1737: Assignment to wtiM_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1738: Assignment to wtiM_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1739: Assignment to wtiM_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1960: Assignment to wtiM_0_peerIsReady ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1519: Input port EN_uuid is not connected on this instance +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1243: Port sda is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 353: Port pd_PSEN is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 347: Assignment to ocb_mon_PSDONE ignored, since the identifier is never used +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 369: Module memc_ui_top does not have a parameter named OCB_MONITOR +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 379: Module memc_ui_top does not have a parameter named SIM_CAL_OPTION +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 380: Module memc_ui_top does not have a parameter named SIM_INIT_OPTION + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 386: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 432: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" Line 146: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" Line 153: Net does not have a driver. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 443: Result of 64-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 444: Result of 64-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 168: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 169: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 201: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" Line 426: Result of 32-bit expression is truncated to fit in 6-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 140: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 198: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 204: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:532 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 323: Index <13> is out of range [12:0] for signal . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 151: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 506: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 764: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 854: Result of 8-bit expression is truncated to fit in 7-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 879: Result of 11-bit expression is truncated to fit in 10-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 888: Result of 10-bit expression is truncated to fit in 9-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 935: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 950: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 966: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 987: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1038: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1051: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1179: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1208: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1083: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1561: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1573: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1657: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1735: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1745: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" Line 232: Assignment to rst_r ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 152: Assignment to dqs_ibuf_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 288: Assignment to dqs_n_tfb ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" Line 147: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" Line 239: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" Line 199: Assignment to dqs_oe_r ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 269: Assignment to wrdata_en_r7 ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1549: Assignment to wrlvl_done_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1634: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1758: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1761: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1764: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1767: Result of 32-bit expression is truncated to fit in 8-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 284: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 298: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 523: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 540: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 453: Assignment to wl_state_r1 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 310: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 324: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 331: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 339: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 301: Found full_case directive in module phy_rdclk_gen. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 173: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 180: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" Line 163: Result of 10-bit expression is truncated to fit in 9-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 566: Result of 8-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 647: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 707: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 878: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 918: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 946: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1025: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1046: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1048: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1167: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1179: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1283: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1292: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1296: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1317: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1343: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1356: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1357: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1372: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1395: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1405: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1413: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1479: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1481: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1483: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1497: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1525: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1073: Assignment to found_two_edge_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1541: Result of 31-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1650: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1784: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1809: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1880: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1974: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1984: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1995: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2037: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2091: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" Line 275: Result of 32-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 199: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 229: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 416: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 417: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 593: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 977: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 568: Assignment to ecc_single ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 570: Assignment to ecc_err_addr ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" Line 232: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" Line 199: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 620: Assignment to hi_priority ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 377: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 378: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 396: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 412: Assignment to ddr3_parity ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 419: Assignment to bank_mach_next ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 423: Assignment to app_ecc_multiple_err_i ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 267: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 268: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 298: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 306: Net does not have a driver. +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 399: Input port pd_PSDONE is not connected on this instance +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1246: Size mismatch in connection of port . Formal port size is 27-bit while actual signal size is 33-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1295: Size mismatch in connection of port . Formal port size is 256-bit while actual signal size is 32-bit. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1655: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1701: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1702: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1708: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1709: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1710: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1711: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1712: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1716: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1717: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1718: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1719: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1720: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1721: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1722: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1723: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1724: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1725: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1726: Assignment to memc_wdfWren_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1730: Assignment to memc_wdfEnd_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1731: Assignment to memc_wdfEnd_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1737: Assignment to wmemi_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1743: Assignment to wmemi_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1744: Assignment to wmemi_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1749: Assignment to wmemi_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1754: Assignment to wmemi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1755: Assignment to wmemi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1756: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1757: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1758: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1759: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1760: Assignment to memInReset_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1761: Assignment to memInReset_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1762: Assignment to wmemiReadInFlight_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1766: Assignment to wmemiReadInFlight_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1767: Assignment to wmemiReadInFlight_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1768: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1769: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1770: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1771: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1772: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1773: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1774: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1775: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1776: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1777: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1778: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1782: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1788: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1789: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1803: Assignment to wmemi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1804: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1805: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1806: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1996: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2020: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2121: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2143: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2289: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2746: Assignment to pioReadInFlight ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2869: Assignment to dbgCtrl ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 915: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 948: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 949: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 955: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 956: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 957: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 958: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 959: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 963: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 964: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 965: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 966: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 967: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 968: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 969: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 970: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 971: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 972: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 973: Assignment to flashC_rseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 977: Assignment to flashC_rseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 978: Assignment to flashC_rseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 979: Assignment to flashC_rseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 980: Assignment to flashC_rseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 981: Assignment to flashC_rseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 982: Assignment to flashC_rseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 984: Assignment to flashC_wseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 988: Assignment to flashC_wseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 989: Assignment to flashC_wseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 990: Assignment to flashC_wseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 991: Assignment to flashC_wseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 992: Assignment to flashC_wseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 993: Assignment to flashC_wseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 995: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 999: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1005: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1006: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1025: Assignment to flashC_rseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1052: Assignment to flashC_wseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1268: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1446: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1470: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1586: Assignment to flashC_wdReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1227: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1264: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1265: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1273: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1274: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1275: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1276: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1277: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1281: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1282: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1283: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1284: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1285: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1286: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1287: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1288: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1289: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1290: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1297: Assignment to spiCDC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1298: Assignment to spiCDC_doResp_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1302: Assignment to spiDAC_cGate_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1305: Assignment to spiDAC_csbR_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1306: Assignment to spiDAC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1314: Assignment to fcCdc_pulseAction_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1315: Assignment to fcCdc_pulseAction_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1316: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1320: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1328: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1329: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1342: Assignment to spiCDC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1343: Assignment to spiCDC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1344: Assignment to spiCDC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1345: Assignment to spiCDC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1346: Assignment to spiCDC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1347: Assignment to spiCDC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1348: Assignment to spiCDC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1349: Assignment to spiCDC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1350: Assignment to spiCDC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1354: Assignment to spiDAC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1355: Assignment to spiDAC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1356: Assignment to spiDAC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1357: Assignment to spiDAC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1358: Assignment to spiDAC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1359: Assignment to spiDAC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1360: Assignment to spiDAC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1361: Assignment to spiDAC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1362: Assignment to spiDAC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1363: Assignment to fcCdc_grayCounter_pwIncrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1364: Assignment to fcCdc_grayCounter_pwDecrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1365: Assignment to oneKHz_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1366: Assignment to oneKHz_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1367: Assignment to spiCDC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1368: Assignment to spiDAC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1369: Assignment to fcCdc_grayCounter_wdCounterCrossing_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1719: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1743: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 2023: Assignment to splitReadInFlight ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 614: Assignment to gmii_rx_clk_O ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 624: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 626: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 627: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 628: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1023: Assignment to rxRS_rxOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1024: Assignment to rxRS_rxOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1025: Assignment to txRS_txOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1026: Assignment to txRS_txOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1035: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1051: Assignment to txRS_txDV_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1056: Assignment to txRS_txER_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1057: Assignment to txRS_txER_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1058: Assignment to txRS_underflow_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1059: Assignment to txRS_underflow_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1062: Assignment to rxRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1065: Assignment to rxRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1066: Assignment to txRS_preambleCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1067: Assignment to txRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1068: Assignment to txRS_ifgCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1078: Assignment to txRS_lenCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1085: Assignment to txRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1437: Assignment to txRS_underflow ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1485: Assignment to rxRS_isSOF ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1768: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1802: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1803: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1809: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1810: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1811: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1812: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1813: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1817: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1818: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1819: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1820: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1821: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1822: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1823: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1824: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1825: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1826: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1827: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1828: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1829: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1830: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1831: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1832: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1833: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1836: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1837: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1846: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1847: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1848: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1849: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1850: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1854: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1855: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1856: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1857: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1858: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1859: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1860: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1861: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1862: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1863: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1864: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1868: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1874: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1875: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1885: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1886: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1887: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1888: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1889: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1891: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1892: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1893: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1895: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1896: Assignment to mdi_pwTick_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1897: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1898: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1899: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2341: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2365: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3497: Assignment to txDBGPos ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3755: Assignment to wti_nowReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1806: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1877: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1923: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2064: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2278: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2746: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2822: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 719: Assignment to block_clk ignored, since the identifier is never used + +Elaborating module +. + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1273: Assignment to TRNRDLLPSRCRDYN ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 180: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 229: Result of 9-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1886: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 69-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1894: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 68-bit. + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 986: Assignment to rx_func_level_reset_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1918: Assignment to pciw_pci0_wTrnTxSof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1919: Assignment to pciw_pci0_wTrnTxSof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1920: Assignment to pciw_pci0_wTrnTxEof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1921: Assignment to pciw_pci0_wTrnTxEof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1922: Assignment to pciw_pci0_wTrnTxDsc_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1923: Assignment to pciw_pci0_wTrnTxDsc_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1924: Assignment to pciw_pci0_wTrnTxRem_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1925: Assignment to pciw_pci0_wTrnTxRem_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1926: Assignment to pciw_pci0_wTrnTxDat_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1927: Assignment to pciw_pci0_wTrnTxDat_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1928: Assignment to pciw_pci0_wTrnRxNpOk_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1929: Assignment to pciw_pci0_wTrnRxNpOk_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1930: Assignment to pciw_pci0_wTrnRxCplS_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1931: Assignment to pciw_pci0_wTrnRxCplS_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1932: Assignment to pciw_pcie_irq_wInterruptRdyN_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1934: Assignment to pciw_pcie_irq_wInterruptRdyN_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1935: Assignment to pciw_pcie_irq_wInterruptDo_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1937: Assignment to pciw_pcie_irq_wInterruptDo_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1950: Assignment to pciw_p2iAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1951: Assignment to pciw_p2iAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1952: Assignment to pciw_p2iAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1957: Assignment to pciw_i2pAF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1959: Assignment to pciw_i2pAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1960: Assignment to pciw_i2pAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1961: Assignment to pciw_i2pAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1962: Assignment to infLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1963: Assignment to blinkLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2348: Assignment to pciw_pcie_irq_rMMEnabled ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Input port gmii_col_i is not connected on this instance +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v". +WARNING:Xst:2898 - Port 'gmii_col_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_crs_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_intr_i', unconnected in block instance 'ftop', is tied to GND. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1242: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1242: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1270: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1501: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1657: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1778: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 82-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 82-bit register for signal . + Found 32-bit adder for signal created at line 1966. + Found 1-bit comparator equal for signal created at line 1868 + Found 1-bit comparator equal for signal created at line 2133 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 538 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 983: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1028: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1073: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1118: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1163: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1202: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 3-bit register for signal . + Found 2-bit subtractor for signal created at line 2087. + Found 2-bit subtractor for signal created at line 2205. + Found 2-bit subtractor for signal created at line 2537. + Found 32-bit adder for signal created at line 1421. + Found 32-bit adder for signal created at line 1422. + Found 2-bit adder for signal created at line 1428. + Found 2-bit adder for signal created at line 2086. + Found 32-bit adder for signal created at line 2173. + Found 32-bit adder for signal created at line 2192. + Found 2-bit adder for signal created at line 2204. + Found 32-bit adder for signal created at line 2230. + Found 3-bit adder for signal created at line 2474. + Found 3-bit adder for signal created at line 2474. + Found 3-bit adder for signal created at line 2485. + Found 3-bit adder for signal created at line 2485. + Found 3-bit adder for signal created at line 2493. + Found 3-bit adder for signal created at line 2493. + Found 3-bit adder for signal created at line 2499. + Found 3-bit adder for signal created at line 2499. + Found 3-bit adder for signal created at line 2507. + Found 3-bit adder for signal created at line 2507. + Found 14-bit adder for signal created at line 2515. + Found 3-bit adder for signal created at line 2518. + Found 3-bit adder for signal created at line 2538. + Found 3-bit adder for signal created at line 2539. + Found 4x3-bit Read Only RAM for signal <_n1538> + Found 1-bit 4-to-1 multiplexer for signal created at line 2589. + Found 32-bit 4-to-1 multiplexer for signal created at line 2624. + Found 1-bit 4-to-1 multiplexer for signal created at line 2649. + Found 1-bit 4-to-1 multiplexer for signal created at line 2674. + Found 34-bit 8-to-1 multiplexer for signal <_n1602> created at line 867. + Found 2-bit comparator greater for signal created at line 944 + Found 2-bit comparator greater for signal created at line 1511 + Found 1-bit comparator not equal for signal created at line 2089 + Found 1-bit comparator not equal for signal created at line 2207 + Found 3-bit comparator greater for signal created at line 2457 + Found 3-bit comparator greater for signal created at line 2459 + Found 3-bit comparator greater for signal created at line 2460 + Found 3-bit comparator greater for signal created at line 2461 + Found 3-bit comparator greater for signal created at line 2462 + Found 32-bit comparator greater for signal created at line 2481 + Found 32-bit comparator greater for signal created at line 2514 + Found 3-bit comparator greater for signal created at line 2592 + Found 3-bit comparator greater for signal created at line 2595 + Found 3-bit comparator greater for signal created at line 2598 + Found 3-bit comparator greater for signal created at line 2601 + Found 3-bit comparator greater for signal created at line 2613 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 347 D-type flip-flop(s). + inferred 16 Comparator(s). + inferred 22 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 1024x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 77 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCTop16B.v". +WARNING:Xst:2898 - Port 'EN_uuid', unconnected in block instance 'inf', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1333: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1519: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1519: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCApp16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" line 623: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit subtractor for signal created at line 813. + Found 32-bit subtractor for signal created at line 997. + Found 2-bit subtractor for signal created at line 1099. + Found 32-bit subtractor for signal created at line 1341. + Found 2-bit subtractor for signal created at line 1403. + Found 2-bit subtractor for signal created at line 1404. + Found 2-bit subtractor for signal created at line 1405. + Found 2-bit adder for signal created at line 819. + Found 2-bit adder for signal created at line 849. + Found 2-bit adder for signal created at line 860. + Found 32-bit adder for signal created at line 955. + Found 32-bit adder for signal created at line 961. + Found 32-bit adder for signal created at line 965. + Found 32-bit adder for signal > created at line 1006. + Found 32-bit adder for signal > created at line 1007. + Found 32-bit adder for signal > created at line 1008. + Found 32-bit adder for signal > created at line 1009. + Found 32-bit adder for signal created at line 1019. + Found 2-bit adder for signal created at line 1098. + Found 32-bit adder for signal > created at line 1171. + Found 32-bit adder for signal > created at line 1172. + Found 32-bit adder for signal > created at line 1173. + Found 32-bit adder for signal > created at line 1174. + Found 32-bit adder for signal created at line 1178. + Found 32-bit adder for signal created at line 1185. + Found 32-bit adder for signal created at line 1192. + Found 4x3-bit Read Only RAM for signal <_n1567> + Found 34-bit 13-to-1 multiplexer for signal <_n1655> created at line 525. + Found 2-bit comparator greater for signal created at line 576 + Found 1-bit comparator not equal for signal created at line 1101 + Found 128-bit comparator not equal for signal created at line 1372 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 25 Adder/Subtractor(s). + inferred 1201 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 264 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n1964> + Found 34-bit 24-to-1 multiplexer for signal <_n2118> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x169-bit dual-port RAM for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 338 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x169-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 174 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit subtractor for signal created at line 808. + Found 2-bit subtractor for signal created at line 998. + Found 2-bit subtractor for signal created at line 1245. + Found 2-bit subtractor for signal created at line 1318. + Found 2-bit adder for signal created at line 777. + Found 2-bit adder for signal created at line 809. + Found 2-bit adder for signal created at line 997. + Found 32-bit adder for signal created at line 1085. + Found 32-bit adder for signal created at line 1101. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1213. + Found 32-bit adder for signal created at line 1232. + Found 2-bit adder for signal created at line 1244. + Found 32-bit adder for signal created at line 1271. + Found 32-bit adder for signal > created at line 1321. + Found 32-bit adder for signal > created at line 1322. + Found 32-bit adder for signal > created at line 1323. + Found 32-bit adder for signal > created at line 1324. + Found 4x3-bit Read Only RAM for signal <_n0684> + Found 34-bit 15-to-1 multiplexer for signal <_n0763> created at line 537. + Found 2-bit comparator greater for signal created at line 579 + Found 2-bit comparator greater for signal created at line 866 + Found 1-bit comparator not equal for signal created at line 1000 + Found 1-bit comparator not equal for signal created at line 1247 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 16 Adder/Subtractor(s). + inferred 710 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2039> + Found 34-bit 24-to-1 multiplexer for signal <_n2113> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkUUID.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit comparator not equal for signal created at line 68 + Found 1-bit comparator equal for signal created at line 69 + Summary: + inferred 6 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCInf16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2077: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2524: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2524: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCCP.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5320: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5320: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5320: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5488: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5507: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5526: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5545: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5583: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5602: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5621: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5640: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5659: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5678: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5697: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5716: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5735: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5754: Output port of the instance is unconnected or connected to loadless signal. + Found 65-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 57-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 64-bit subtractor for signal created at line 11101. + Found 50-bit subtractor for signal created at line 12080. + Found 28-bit subtractor for signal created at line 12185. + Found 50-bit subtractor for signal <_281474976710656_MINUS_timeServ_delSecond__q1> created at line 17460. + Found 4-bit subtractor for signal created at line 17701. + Found 4-bit subtractor for signal created at line 17702. + Found 6-bit subtractor for signal created at line 17756. + Found 32-bit adder for signal created at line 9499. + Found 1-bit adder for signal created at line 9521. + Found 1-bit adder for signal created at line 9600. + Found 1-bit adder for signal created at line 9677. + Found 1-bit adder for signal created at line 9754. + Found 1-bit adder for signal created at line 9831. + Found 1-bit adder for signal created at line 9908. + Found 1-bit adder for signal created at line 9984. + Found 1-bit adder for signal created at line 10060. + Found 1-bit adder for signal created at line 10136. + Found 1-bit adder for signal created at line 10212. + Found 1-bit adder for signal created at line 10288. + Found 1-bit adder for signal created at line 10364. + Found 1-bit adder for signal created at line 10440. + Found 1-bit adder for signal created at line 10516. + Found 1-bit adder for signal created at line 10592. + Found 7-bit adder for signal created at line 12002. + Found 50-bit adder for signal created at line 12087. + Found 8-bit adder for signal created at line 12126. + Found 28-bit adder for signal created at line 12173. + Found 28-bit adder for signal created at line 12195. + Found 28-bit adder for signal created at line 12202. + Found 6-bit adder for signal created at line 12236. + Found 3-bit adder for signal created at line 17546. + Found 3-bit adder for signal created at line 17546. + Found 32-bit adder for signal created at line 17735. + Found 32-bit adder for signal created at line 17736. + Found 32-bit adder for signal created at line 17737. + Found 32-bit adder for signal created at line 17738. + Found 32-bit adder for signal created at line 17739. + Found 32-bit adder for signal created at line 17740. + Found 32-bit adder for signal created at line 17742. + Found 32-bit adder for signal created at line 17746. + Found 50-bit adder for signal created at line 17747. + Found 32-bit adder for signal created at line 17748. + Found 32-bit adder for signal created at line 17749. + Found 32-bit adder for signal created at line 17750. + Found 32-bit adder for signal created at line 17751. + Found 32-bit adder for signal created at line 17752. + Found 32-bit adder for signal created at line 17753. + Found 32-bit adder for signal created at line 17754. + Found 32-bit adder for signal created at line 17755. + Found 32-bit shifter logical left for signal created at line 4615 + Found 32-bit shifter logical left for signal created at line 4616 + Found 32-bit shifter logical left for signal created at line 4617 + Found 32-bit shifter logical left for signal created at line 4618 + Found 32-bit shifter logical left for signal created at line 4619 + Found 32-bit shifter logical left for signal created at line 4620 + Found 32-bit shifter logical left for signal created at line 4621 + Found 32-bit shifter logical left for signal created at line 4622 + Found 32-bit shifter logical left for signal created at line 4623 + Found 32-bit shifter logical left for signal created at line 4624 + Found 32-bit shifter logical left for signal created at line 4625 + Found 32-bit shifter logical left for signal created at line 4626 + Found 32-bit shifter logical left for signal created at line 4627 + Found 32-bit shifter logical left for signal created at line 4628 + Found 32-bit shifter logical left for signal created at line 4629 + Found 64x8-bit Read Only RAM for signal + Found 32-bit 16-to-1 multiplexer for signal created at line 17851. + Found 1-bit 16-to-1 multiplexer for signal created at line 17919. + Found 1-bit 16-to-1 multiplexer for signal created at line 17988. + Found 1-bit 16-to-1 multiplexer for signal created at line 18068. + Found 1-bit 16-to-1 multiplexer for signal created at line 18136. + Found 1-bit 16-to-1 multiplexer for signal created at line 18205. + Found 1-bit 16-to-1 multiplexer for signal created at line 18273. + Found 1-bit 16-to-1 multiplexer for signal created at line 18342. + Found 1-bit 16-to-1 multiplexer for signal created at line 18410. + Found 1-bit 16-to-1 multiplexer for signal created at line 18479. + Found 1-bit 16-to-1 multiplexer for signal created at line 18547. + Found 1-bit 16-to-1 multiplexer for signal created at line 18616. + Found 1-bit 16-to-1 multiplexer for signal created at line 18684. + Found 1-bit 16-to-1 multiplexer for signal created at line 18753. + Found 1-bit 16-to-1 multiplexer for signal created at line 18821. + Found 1-bit 16-to-1 multiplexer for signal created at line 18890. + Found 1-bit 16-to-1 multiplexer for signal created at line 18958. + Found 1-bit 16-to-1 multiplexer for signal created at line 19027. + Found 1-bit 16-to-1 multiplexer for signal created at line 19095. + Found 1-bit 16-to-1 multiplexer for signal created at line 19164. + Found 1-bit 16-to-1 multiplexer for signal created at line 19232. + Found 1-bit 16-to-1 multiplexer for signal created at line 19301. + Found 1-bit 16-to-1 multiplexer for signal created at line 19369. + Found 1-bit 16-to-1 multiplexer for signal created at line 19438. + Found 1-bit 16-to-1 multiplexer for signal created at line 19506. + Found 1-bit 16-to-1 multiplexer for signal created at line 19575. + Found 1-bit 16-to-1 multiplexer for signal created at line 19643. + Found 1-bit 16-to-1 multiplexer for signal created at line 19712. + Found 1-bit 16-to-1 multiplexer for signal created at line 19780. + Found 1-bit 16-to-1 multiplexer for signal created at line 19849. + Found 1-bit 16-to-1 multiplexer for signal created at line 19916. + Found 1-bit 16-to-1 multiplexer for signal created at line 19983. + Found 1-bit 16-to-1 multiplexer for signal created at line 20096. + Found 1-bit 16-to-1 multiplexer for signal created at line 20346. + Found 1-bit 16-to-1 multiplexer for signal created at line 20415. + Found 1-bit 16-to-1 multiplexer for signal created at line 20495. + Found 1-bit 16-to-1 multiplexer for signal created at line 20700. + Found 1-bit 16-to-1 multiplexer for signal created at line 20769. + Found 1-bit 16-to-1 multiplexer for signal created at line 20974. + Found 1-bit 16-to-1 multiplexer for signal created at line 21043. + Found 1-bit 16-to-1 multiplexer for signal created at line 21248. + Found 1-bit 16-to-1 multiplexer for signal created at line 21317. + Found 1-bit 16-to-1 multiplexer for signal created at line 21522. + Found 1-bit 16-to-1 multiplexer for signal created at line 21591. + Found 1-bit 16-to-1 multiplexer for signal created at line 21796. + Found 1-bit 16-to-1 multiplexer for signal created at line 21865. + Found 1-bit 16-to-1 multiplexer for signal created at line 22070. + Found 1-bit 16-to-1 multiplexer for signal created at line 22139. + Found 1-bit 16-to-1 multiplexer for signal created at line 22344. + Found 1-bit 16-to-1 multiplexer for signal created at line 22413. + Found 1-bit 16-to-1 multiplexer for signal created at line 22618. + Found 1-bit 16-to-1 multiplexer for signal created at line 22687. + Found 1-bit 16-to-1 multiplexer for signal created at line 22892. + Found 1-bit 16-to-1 multiplexer for signal created at line 22961. + Found 1-bit 16-to-1 multiplexer for signal created at line 23166. + Found 1-bit 16-to-1 multiplexer for signal created at line 23235. + Found 1-bit 16-to-1 multiplexer for signal created at line 23440. + Found 1-bit 16-to-1 multiplexer for signal created at line 23509. + Found 1-bit 16-to-1 multiplexer for signal created at line 23714. + Found 1-bit 16-to-1 multiplexer for signal created at line 23783. + Found 1-bit 16-to-1 multiplexer for signal created at line 23988. + Found 1-bit 16-to-1 multiplexer for signal created at line 24057. + Found 1-bit 16-to-1 multiplexer for signal created at line 24258. + Found 1-bit 16-to-1 multiplexer for signal created at line 24325. + Found 1-bit 16-to-1 multiplexer for signal created at line 24422. + Found 1-bit 16-to-1 multiplexer for signal created at line 24518. + Found 32-bit 16-to-1 multiplexer for signal created at line 24686. + Found 3-bit comparator greater for signal created at line 5931 + Found 7-bit comparator lessequal for signal created at line 10692 + Found 7-bit comparator lessequal for signal created at line 10692 + Found 28-bit comparator greater for signal created at line 12122 + Found 2-bit comparator not equal for signal created at line 16595 + Found 8-bit comparator greater for signal created at line 17484 + Found 8-bit comparator greater for signal created at line 17513 + Found 24-bit comparator greater for signal created at line 17515 + Found 24-bit comparator greater for signal created at line 17525 + Found 28-bit comparator greater for signal created at line 17555 + Found 28-bit comparator greater for signal created at line 17563 + Found 28-bit comparator greater for signal created at line 17565 + Found 32-bit comparator greater for signal created at line 17597 + Found 32-bit comparator greater for signal created at line 17604 + Found 32-bit comparator greater for signal created at line 17611 + Found 32-bit comparator greater for signal created at line 17618 + Found 32-bit comparator greater for signal created at line 17625 + Found 32-bit comparator greater for signal created at line 17632 + Found 32-bit comparator greater for signal created at line 17639 + Found 32-bit comparator greater for signal created at line 17646 + Found 32-bit comparator greater for signal created at line 17653 + Found 32-bit comparator greater for signal created at line 17660 + Found 32-bit comparator greater for signal created at line 17667 + Found 32-bit comparator greater for signal created at line 17674 + Found 32-bit comparator greater for signal created at line 17681 + Found 32-bit comparator greater for signal created at line 17688 + Found 32-bit comparator greater for signal created at line 17695 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 4107 D-type flip-flop(s). + inferred 27 Comparator(s). + inferred 300 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBLUART.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit adder for signal created at line 264. + Found 16-bit adder for signal created at line 285. + Found 4-bit adder for signal created at line 294. + Found 16-bit adder for signal created at line 327. + Found 1-bit 10-to-1 multiplexer for signal created at line 302. + Found 16-bit comparator equal for signal created at line 244 + Found 16-bit comparator greater for signal created at line 285 + Found 16-bit comparator equal for signal created at line 328 + Found 16-bit comparator greater for signal created at line 329 + Found 16-bit comparator equal for signal created at line 338 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 68 D-type flip-flop(s). + inferred 5 Comparator(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x8-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 15 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM1Load.v". + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x64-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 86 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 30-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 10-bit subtractor for signal created at line 313. + Found 10-bit subtractor for signal created at line 314. + Found 2-bit subtractor for signal created at line 322. + Found 10-bit subtractor for signal created at line 323. + Found 12-bit subtractor for signal created at line 490. + Found 12-bit subtractor for signal created at line 522. + Found 2-bit adder for signal created at line 319. + Found 30-bit adder for signal created at line 321. + Found 2-bit subtractor for signal > created at line 203. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n0624> + Found 4x2-bit Read Only RAM for signal <_n0643> + Found 4x2-bit Read Only RAM for signal <_n0662> + Found 32-bit 4-to-1 multiplexer for signal created at line 548. + Summary: + inferred 4 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 283 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 56-bit register for signal . + Found 56-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 114 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 308 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 10-bit subtractor for signal created at line 3265. + Found 10-bit subtractor for signal created at line 3268. + Found 10-bit subtractor for signal created at line 3269. + Found 10-bit subtractor for signal created at line 3271. + Found 10-bit subtractor for signal created at line 3275. + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3306. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 17-bit adder for signal created at line 3296. + Found 17-bit adder for signal created at line 3298. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 5-bit adder for signal created at line 4548. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6690. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1973. + Found 2-bit subtractor for signal created at line 1969. + Found 4x16-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal <_n4170> + Found 4x2-bit Read Only RAM for signal <_n4189> + Found 4x2-bit Read Only RAM for signal <_n4214> + Found 4x2-bit Read Only RAM for signal <_n4232> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4487> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 8-bit comparator equal for signal created at line 6489 + Found 17-bit comparator lessequal for signal created at line 6519 + Found 13-bit comparator lessequal for signal created at line 6673 + Found 10-bit comparator greater for signal created at line 6677 + Found 10-bit comparator greater for signal created at line 6679 + Found 8-bit comparator equal for signal created at line 6681 + Found 5-bit comparator equal for signal created at line 6682 + Found 3-bit comparator equal for signal created at line 6683 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6818 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 91 Adder/Subtractor(s). + inferred 2516 D-type flip-flop(s). + inferred 34 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 153-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2448-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 153-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2608 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x146-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 151 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3314. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 32-bit adder for signal created at line 3389. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6692. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1973. + Found 2-bit subtractor for signal created at line 1969. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4129> + Found 4x3-bit Read Only RAM for signal <_n4152> + Found 4x2-bit Read Only RAM for signal <_n4176> + Found 4x2-bit Read Only RAM for signal <_n4194> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4454> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 17-bit comparator equal for signal created at line 6658 + Found 13-bit comparator lessequal for signal created at line 6669 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6808 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + Summary: + inferred 5 RAM(s). + inferred 87 Adder/Subtractor(s). + inferred 2502 D-type flip-flop(s). + inferred 28 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTimeClient.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSM.v". + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktFork.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit shifter logical left for signal created at line 107 + Found 7-bit shifter logical left for signal created at line 107 + Found 1-bit 4-to-1 multiplexer for signal created at line 247. + Found 3-bit comparator equal for signal created at line 225 + Found 7-bit comparator equal for signal created at line 226 + Found 1-bit comparator equal for signal created at line 226 + Found 4-bit comparator equal for signal created at line 230 + Found 8-bit comparator equal for signal created at line 237 + Found 7-bit comparator equal for signal created at line 250 + Summary: + inferred 2 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 4 Multiplexer(s). + inferred 2 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktMerge.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1243: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1400: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit subtractor for signal created at line 1975. + Found 2-bit subtractor for signal created at line 2544. + Found 2-bit subtractor for signal created at line 2547. + Found 2-bit adder for signal created at line 1643. + Found 8-bit adder for signal created at line 1680. + Found 8-bit adder for signal created at line 1680. + Found 2-bit adder for signal created at line 1683. + Found 16-bit adder for signal created at line 1840. + Found 16-bit adder for signal created at line 1845. + Found 8-bit adder for signal created at line 1905. + Found 32-bit adder for signal created at line 1915. + Found 2-bit adder for signal created at line 1974. + Found 32-bit adder for signal created at line 2070. + Found 32-bit adder for signal created at line 2074. + Found 32-bit adder for signal created at line 2085. + Found 4x3-bit Read Only RAM for signal <_n1695> + Found 32-bit 39-to-1 multiplexer for signal <_n1810> created at line 887. + Found 34-bit 4-to-1 multiplexer for signal created at line 856. + Found 2-bit comparator greater for signal created at line 959 + Found 1-bit comparator not equal for signal created at line 1977 + Found 8-bit comparator greater for signal created at line 2314 + Found 8-bit comparator greater for signal created at line 2546 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 849 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 161 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 5-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 10 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 24-bit register for signal . + Found 24-bit register for signal . + Summary: + inferred 48 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x177-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 199 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x128-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 150 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v". +WARNING:Xst:2898 - Port 'dbg_wr_dqs_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_dq_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'pd_PSDONE', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_tap_set_en', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_inc_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_dec_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 334: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "syn_maxfan = 10" for signal . + Found 31-bit register for signal . + Summary: + inferred 31 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v". + Set property "syn_maxfan = 10" for signal . + Set property "syn_maxfan = 10" for signal . + Found 33-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 612: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'dfi_dram_clk_disable', unconnected in block 'mc', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'dfi_reset_n', unconnected in block 'mc', is tied to its initial value (1). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v". +WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 206. + Found 3-bit subtractor for signal created at line 267. + Found 4-bit subtractor for signal created at line 326. + Found 3-bit subtractor for signal created at line 385. + Found 3-bit adder for signal created at line 205. + Found 4-bit adder for signal created at line 329. + Found 3-bit comparator lessequal for signal created at line 271 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 17 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 6 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 236: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 321: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit subtractor for signal created at line 122. + Found 6-bit subtractor for signal created at line 147. + Found 20-bit subtractor for signal created at line 175. + Found 1-bit adder for signal created at line 267. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 43 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_col_r<10>', unconnected in block 'bank_compare', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 280 + Found 3-bit comparator equal for signal created at line 221 + Found 13-bit comparator equal for signal created at line 230 + Summary: + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 7 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 8 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'bank_common', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 2-bit subtractor for signal created at line 393. + Found 6-bit subtractor for signal created at line 430. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 18 Adder/Subtractor(s). + inferred 21 D-type flip-flop(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 159: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 185: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 235: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'arb_row_col', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'arb_row_col', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'row_mux.row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:2935 - Signal 'col_mux.col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 349 + Found 1-bit shifter logical left for signal > created at line 351 + Found 1-bit shifter logical left for signal created at line 390 + Summary: + inferred 13 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 3 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 11-bit register for signal >. + Found 1-bit register for signal >. + Found 11-bit register for signal . + Found 3-bit subtractor for signal created at line 260. + Found 2-bit subtractor for signal created at line 280. + Found 5-bit adder for signal created at line 377. + Found 5-bit adder for signal created at line 386. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 45 D-type flip-flop(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1131: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v". +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst - Value "0" of property "syn_replicate" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 256-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:1799 - State 011110 is never reached in FSM . +INFO:Xst:1799 - State 100101 is never reached in FSM . +INFO:Xst:1799 - State 100100 is never reached in FSM . +INFO:Xst:1799 - State 100111 is never reached in FSM . +INFO:Xst:1799 - State 011101 is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 86 | + | Inputs | 31 | + | Outputs | 43 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit subtractor for signal created at line 1560. + Found 7-bit adder for signal created at line 854. + Found 10-bit adder for signal created at line 879. + Found 9-bit adder for signal created at line 888. + Found 8-bit adder for signal created at line 935. + Found 8-bit adder for signal created at line 966. + Found 2-bit adder for signal created at line 987. + Found 2-bit adder for signal created at line 1038. + Found 3-bit adder for signal created at line 1051. + Found 2-bit adder for signal created at line 1561. + Found 2-bit adder for signal created at line 1573. + Found 2-bit adder for signal created at line 1657. + Found 4-bit adder for signal created at line 1735. + Found 5-bit subtractor for signal > created at line 764. + Found 16x256-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal + Found 2-bit comparator greater for signal created at line 1208 + Found 32-bit comparator not equal for signal created at line 1560 + Found 2-bit comparator greater for signal created at line 1597 + WARNING:Xst:2404 - FFs/Latches <7:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:2>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <2:10>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 468 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 21 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v". + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_keep = 1" for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 D-type flip-flop(s). + inferred 17 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v". + Set property "syn_maxfan = 1" for signal . + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 6-bit register for signal . + Found 6-bit register for signal . + Summary: + inferred 12 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal created at line 109. + Found 4-bit 4-to-1 multiplexer for signal created at line 133. + Summary: + inferred 17 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Summary: + inferred 14 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Summary: + inferred 26 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 108 D-type flip-flop(s). + inferred 124 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 2-bit adder for signal created at line 1634. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 137 D-type flip-flop(s). + inferred 146 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 40-bit register for signal >. + Found 16-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal >. + Found 40-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <9>>. + Found 1-bit register for signal <8>>. + Found 1-bit register for signal <7>>. + Found 1-bit register for signal <6>>. + Found 1-bit register for signal <5>>. + Found 1-bit register for signal <14>>. + Found 1-bit register for signal <13>>. + Found 1-bit register for signal <12>>. + Found 1-bit register for signal <11>>. + Found 1-bit register for signal <10>>. + Found 1-bit register for signal <19>>. + Found 1-bit register for signal <18>>. + Found 1-bit register for signal <17>>. + Found 1-bit register for signal <16>>. + Found 1-bit register for signal <15>>. + Found 1-bit register for signal <24>>. + Found 1-bit register for signal <23>>. + Found 1-bit register for signal <22>>. + Found 1-bit register for signal <21>>. + Found 1-bit register for signal <20>>. + Found 1-bit register for signal <29>>. + Found 1-bit register for signal <28>>. + Found 1-bit register for signal <27>>. + Found 1-bit register for signal <26>>. + Found 1-bit register for signal <25>>. + Found 1-bit register for signal <34>>. + Found 1-bit register for signal <33>>. + Found 1-bit register for signal <32>>. + Found 1-bit register for signal <31>>. + Found 1-bit register for signal <30>>. + Found 1-bit register for signal <39>>. + Found 1-bit register for signal <38>>. + Found 1-bit register for signal <37>>. + Found 1-bit register for signal <36>>. + Found 1-bit register for signal <35>>. + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal >. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 23 | + | Inputs | 10 | + | Outputs | 11 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 541. + Found 4-bit subtractor for signal created at line 581. + Found 2-bit adder for signal created at line 284. + Found 2-bit adder for signal created at line 298. + Found 5-bit adder for signal created at line 492. + Found 4-bit adder for signal created at line 566. + Found 4-bit adder for signal created at line 567. + Found 4-bit adder for signal created at line 568. + Found 2-bit adder for signal created at line 586. + Found 5-bit adder for signal created at line 641. + Found 3x4-bit multiplier for signal created at line 408. + Found 1-bit 8-to-1 multiplexer for signal created at line 264. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 299. + Found 5-bit 8-to-1 multiplexer for signal created at line 341. + Found 1-bit 8-to-1 multiplexer for signal created at line 512. + Found 1-bit 8-to-1 multiplexer for signal created at line 529. + Found 1-bit 16-to-1 multiplexer for signal created at line 640. + Found 1-bit 16-to-1 multiplexer for signal created at line 641. + Found 1-bit 8-to-1 multiplexer for signal created at line 665. + Found 1-bit 8-to-1 multiplexer for signal created at line 668. + Found 2-bit comparator lessequal for signal created at line 230 + Found 5-bit comparator greater for signal created at line 280 + Found 1-bit comparator equal for signal created at line 282 + Found 2-bit comparator greater for signal created at line 283 + Found 1-bit comparator equal for signal created at line 295 + Found 2-bit comparator greater for signal created at line 297 + Found 4-bit comparator lessequal for signal created at line 341 + Found 2-bit comparator lessequal for signal created at line 341 + Found 5-bit comparator greater for signal created at line 530 + Found 5-bit comparator greater for signal created at line 543 + Found 4-bit comparator lessequal for signal created at line 549 + Found 32-bit comparator equal for signal created at line 581 + Found 5-bit comparator lessequal for signal created at line 673 + Summary: + inferred 1 Multiplier(s). + inferred 10 Adder/Subtractor(s). + inferred 351 D-type flip-flop(s). + inferred 13 Comparator(s). + inferred 163 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 11 | + | Inputs | 4 | + | Outputs | 27 | + | Clock | clk (rising_edge) | + | Reset | rst_oserdes (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit adder for signal created at line 310. + Found 4-bit adder for signal created at line 324. + Found 4-bit adder for signal created at line 331. + Found 4-bit adder for signal created at line 339. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 81 D-type flip-flop(s). + inferred 8 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 256-bit register for signal . + Summary: + inferred 288 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v". + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 5-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 3-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 42 | + | Inputs | 18 | + | Outputs | 18 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 10 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 6 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 15 | + | Inputs | 9 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 1284. + Found 6-bit subtractor for signal created at line 1297. + Found 6-bit subtractor for signal created at line 1395. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 4-bit adder for signal created at line 647. + Found 4-bit adder for signal created at line 707. + Found 12-bit adder for signal created at line 918. + Found 12-bit adder for signal created at line 946. + Found 3-bit adder for signal created at line 1025. + Found 5-bit adder for signal created at line 1046. + Found 31-bit adder for signal created at line 1284. + Found 6-bit adder for signal created at line 1290. + Found 32-bit adder for signal created at line 1297. + Found 3-bit adder for signal created at line 1343. + Found 5-bit adder for signal created at line 1413. + Found 7-bit adder for signal created at line 1480. + Found 32-bit adder for signal created at line 1541. + Found 6-bit adder for signal created at line 1543. + Found 3-bit adder for signal created at line 1650. + Found 5-bit adder for signal created at line 1784. + Found 3-bit adder for signal created at line 1880. + Found 5-bit adder for signal created at line 1974. + Found 2-bit adder for signal created at line 1984. + Found 3-bit adder for signal created at line 1996. + Found 3-bit adder for signal created at line 2037. + Found 5-bit subtractor for signal > created at line 1048. + Found 6-bit subtractor for signal > created at line 1293. + Found 6-bit subtractor for signal > created at line 1372. + Found 5-bit subtractor for signal > created at line 1479. + Found 5-bit subtractor for signal > created at line 1483. + Found 5-bit subtractor for signal > created at line 1497. + Found 5-bit subtractor for signal > created at line 1525. + Found 5-bit subtractor for signal > created at line 1809. + Found 5-bit subtractor for signal > created at line 2091. + Found 3x3-bit multiplier for signal created at line 599. + Found 30-bit shifter logical right for signal created at line 1996 + Found 3x3-bit multiplier for signal created at line 2021. + Found 3-bit 3-to-1 multiplexer for signal created at line 490. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 5-bit comparator lessequal for signal created at line 1289 + Found 6-bit comparator greater for signal created at line 1290 + Found 3-bit comparator greater for signal created at line 1336 + Found 6-bit comparator greater for signal created at line 1383 + Found 6-bit comparator lessequal for signal created at line 1478 + Found 7-bit comparator lessequal for signal created at line 1480 + Found 5-bit comparator lessequal for signal created at line 1756 + Found 3-bit comparator greater for signal created at line 1872 + Found 5-bit comparator lessequal for signal created at line 2013 + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 Multiplier(s). + inferred 44 Adder/Subtractor(s). + inferred 870 D-type flip-flop(s). + inferred 73 Comparator(s). + inferred 232 Multiplexer(s). + inferred 1 Combinational logic shifter(s). + inferred 3 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 9 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 416. + Found 6-bit adder for signal created at line 502. + Found 16-bit adder for signal created at line 536. + Found 16-bit adder for signal created at line 546. + Found 4-bit adder for signal created at line 593. + Found 4-bit subtractor for signal created at line 184. + Found 5-bit subtractor for signal > created at line 417. + Found 1-bit 16-to-1 multiplexer for signal created at line 203. + Found 1-bit 16-to-1 multiplexer for signal created at line 205. + Found 1-bit 16-to-1 multiplexer for signal created at line 232. + Found 1-bit 16-to-1 multiplexer for signal created at line 233. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 67 D-type flip-flop(s). + inferred 12 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 11 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v". + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 256-bit register for signal . + Found 5-bit subtractor for signal created at line 376. + Found 4-bit adder for signal created at line 232. + Found 4-bit adder for signal created at line 252. + Found 4-bit adder for signal created at line 283. + Found 5-bit adder for signal created at line 377. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 339 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal created at line 224. + Found 6-bit adder for signal created at line 183. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 11 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 2-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 41 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 177-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 356 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2048-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 128-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2183 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 294 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 106 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFlashWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" line 585: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 84 | + | Inputs | 8 | + | Outputs | 8 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_183_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 25 | + | Transitions | 299 | + | Inputs | 11 | + | Outputs | 25 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_183_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1425. + Found 2-bit subtractor for signal created at line 1562. + Found 2-bit adder for signal created at line 903. + Found 2-bit adder for signal created at line 1424. + Found 4x3-bit Read Only RAM for signal <_n0836> + Found 32-bit 7-to-1 multiplexer for signal <_n0855> created at line 507. + Found 2-bit comparator greater for signal created at line 527 + Found 1-bit comparator not equal for signal created at line 1427 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 3 Adder/Subtractor(s). + inferred 315 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 41-bit register for signal . + Found 41-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFMC150.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 820: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 891: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 956: Output port of the instance is unconnected or connected to loadless signal. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 33-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 5-bit subtractor for signal created at line 1185. + Found 6-bit subtractor for signal created at line 1188. + Found 3-bit subtractor for signal created at line 1194. + Found 3-bit subtractor for signal created at line 1196. + Found 18-bit subtractor for signal created at line 1400. + Found 2-bit subtractor for signal created at line 1698. + Found 5-bit subtractor for signal <_31_MINUS_spiCDC_dPos_29___d230> created at line 1855. + Found 2-bit subtractor for signal created at line 1920. + Found 5-bit subtractor for signal created at line 1922. + Found 18-bit adder for signal created at line 1183. + Found 2-bit adder for signal created at line 1213. + Found 2-bit adder for signal created at line 1697. + Found 18-bit shifter logical left for signal created at line 708 + Found 4x3-bit Read Only RAM for signal <_n1003> + Found 1-bit 18-to-1 multiplexer for signal created at line 1179. + Found 1-bit 8-to-1 multiplexer for signal created at line 1207. + Found 1-bit 28-to-1 multiplexer for signal created at line 1921. + Found 1-bit 4-to-1 multiplexer for signal <_n0983> created at line 701. + Found 1-bit 4-to-1 multiplexer for signal <_n0993> created at line 700. + Found 2-bit comparator greater for signal created at line 782 + Found 1-bit comparator equal for signal created at line 969 + Found 1-bit comparator equal for signal created at line 976 + Found 1-bit comparator equal for signal created at line 1056 + Found 1-bit comparator not equal for signal created at line 1700 + Found 1-bit comparator equal for signal created at line 1848 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 11 Adder/Subtractor(s). + inferred 367 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 39 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 106. + Found 3-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetEither.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncReset0.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 106. + Found 4-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGbeWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1447: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1459: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1503: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1517: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 22-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 16 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_218_o_equal_658_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1793. + Found 22-bit subtractor for signal created at line 2096. + Found 2-bit subtractor for signal created at line 2320. + Found 2-bit subtractor for signal created at line 2964. + Found 5-bit subtractor for signal created at line 2966. + Found 5-bit subtractor for signal created at line 2967. + Found 5-bit subtractor for signal created at line 2968. + Found 5-bit adder for signal created at line 1745. + Found 4-bit adder for signal created at line 1746. + Found 4-bit adder for signal created at line 1748. + Found 2-bit adder for signal created at line 1756. + Found 32-bit adder for signal created at line 2101. + Found 32-bit adder for signal created at line 2108. + Found 32-bit adder for signal created at line 2141. + Found 32-bit adder for signal created at line 2146. + Found 32-bit adder for signal created at line 2211. + Found 32-bit adder for signal created at line 2225. + Found 32-bit adder for signal created at line 2229. + Found 32-bit adder for signal created at line 2262. + Found 2-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2407. + Found 32-bit adder for signal created at line 2423. + Found 5-bit adder for signal created at line 2957. + Found 32-bit adder for signal created at line 2965. + Found 4x3-bit Read Only RAM for signal <_n2212> + Found 4x10-bit Read Only RAM for signal <_n2467> + Found 256x2-bit Read Only RAM for signal <_n2863> + Found 8-bit 15-to-1 multiplexer for signal created at line 3010. + Found 8-bit 15-to-1 multiplexer for signal created at line 3059. + Found 8-bit 15-to-1 multiplexer for signal <_n2241> created at line 3108. + Found 8-bit 15-to-1 multiplexer for signal <_n2270> created at line 1132. + Found 8-bit 15-to-1 multiplexer for signal <_n2402> created at line 1131. + Found 34-bit 32-to-1 multiplexer for signal <_n2480> created at line 1093. + Found 2-bit comparator greater for signal created at line 1245 + Found 4-bit comparator greater for signal created at line 1748 + Found 22-bit comparator greater for signal created at line 2098 + Found 32-bit comparator greater for signal created at line 2200 + Found 1-bit comparator not equal for signal created at line 2322 + Found 8-bit comparator greater for signal created at line 2782 + Found 8-bit comparator equal for signal created at line 2810 + Found 8-bit comparator equal for signal created at line 2875 + Found 8-bit comparator equal for signal created at line 2877 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 3 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 1539 D-type flip-flop(s). + inferred 9 Comparator(s). + inferred 100 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGMAC.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 5-bit subtractor for signal created at line 995. + Found 3-bit subtractor for signal created at line 1397. + Found 4-bit adder for signal created at line 971. + Found 12-bit adder for signal created at line 999. + Found 5-bit adder for signal created at line 1003. + Found 8-bit 4-to-1 multiplexer for signal <_n0420> created at line 518. + Found 32-bit comparator not equal for signal created at line 975 + Found 4-bit comparator greater for signal created at line 1136 + Found 12-bit comparator greater for signal created at line 1394 + Found 5-bit comparator greater for signal created at line 1396 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 Adder/Subtractor(s). + inferred 113 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCRC32.v". + Found 32-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator not equal for signal created at line 127 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 48 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 16x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 5-bit comparator not equal for signal created at line 126 + Found 5-bit comparator not equal for signal created at line 127 + Found 5-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 56 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal created at line 50 + Summary: + inferred 1 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 112-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 226 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkLCDController.v". + Found 2-bit register for signal . + Found 24-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 15 | + | Inputs | 12 | + | Outputs | 2 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_241_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 61 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_241_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 140 | + | Transitions | 4472 | + | Inputs | 18 | + | Outputs | 139 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_241_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_241_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_241_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 24-bit subtractor for signal created at line 1550. + Found 8-bit adder for signal created at line 1551. + Found 5-bit adder for signal created at line 1594. + Found 4-bit adder for signal created at line 1595. + Found 8-bit 16-to-1 multiplexer for signal <_n1469> created at line 443. + Found 8-bit 16-to-1 multiplexer for signal <_n1500> created at line 443. + Found 5-bit comparator greater for signal created at line 2925 + Found 4-bit comparator greater for signal created at line 2938 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 330 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 11 Multiplexer(s). + inferred 5 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x81-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 81-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 88 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v". + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 709: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 99. + Found 8-bit adder for signal created at line 100. + Found 8-bit adder for signal created at line 101. + Summary: + inferred 3 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 8 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" line 254: Output port of the instance is unconnected or connected to loadless signal. + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 4-bit subtractor for signal created at line 484. + Found 5-bit adder for signal created at line 464. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 20 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | drp_clk (rising_edge) | + | Reset | Reset_n (negative) | + | Reset type | synchronous | + | Reset State | 0011 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 180. + Found 16x32-bit Read Only RAM for signal <_n0098> + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 10 D-type flip-flop(s). + inferred 7 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v". + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 26 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 00001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 14 | + | Inputs | 7 | + | Outputs | 4 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 308. + Found 4-bit adder for signal created at line 328. + Found 4-bit adder for signal created at line 360. + Found 5-bit comparator greater for signal created at line 283 + Found 4-bit comparator lessequal for signal created at line 356 + Summary: + inferred 3 Adder/Subtractor(s). + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 7 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 21 | + | Transitions | 40 | + | Inputs | 10 | + | Outputs | 21 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0000000000000100000000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 179. + Found 8-bit adder for signal created at line 180. + Found 1-bit comparator equal for signal created at line 534 + Summary: + inferred 2 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 19 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x8-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 41 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v". + Summary: + no macro. +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port RAM : 5 + 1024x32-bit single-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 16x256-bit single-port Read Only RAM : 1 + 16x32-bit single-port Read Only RAM : 4 + 2048x169-bit dual-port RAM : 2 + 2048x32-bit dual-port RAM : 8 + 256x2-bit single-port Read Only RAM : 1 + 2x128-bit dual-port RAM : 1 + 2x146-bit dual-port RAM : 2 + 2x169-bit dual-port RAM : 3 + 2x177-bit dual-port RAM : 1 + 2x32-bit dual-port RAM : 26 + 2x61-bit dual-port RAM : 2 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 11 + 3x8-bit dual-port RAM : 1 + 3x81-bit dual-port RAM : 2 + 4x10-bit single-port Read Only RAM : 1 + 4x16-bit single-port Read Only RAM : 3 + 4x2-bit single-port Read Only RAM : 9 + 4x3-bit single-port Read Only RAM : 12 + 64x8-bit single-port Read Only RAM : 1 + 8x10-bit dual-port RAM : 1 + 8x8-bit dual-port RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 818 + 1-bit adder : 120 + 10-bit adder : 1 + 10-bit subtractor : 16 + 11-bit adder : 2 + 12-bit adder : 15 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 7 + 14-bit subtractor : 6 + 16-bit adder : 36 + 16-bit addsub : 8 + 16-bit subtractor : 6 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit adder : 1 + 18-bit subtractor : 1 + 2-bit adder : 45 + 2-bit addsub : 44 + 2-bit subtractor : 72 + 20-bit subtractor : 1 + 22-bit subtractor : 1 + 24-bit adder : 2 + 24-bit subtractor : 1 + 28-bit adder : 3 + 28-bit subtractor : 1 + 3-bit adder : 64 + 3-bit subtractor : 11 + 30-bit adder : 1 + 31-bit adder : 1 + 32-bit adder : 100 + 32-bit subtractor : 3 + 4-bit adder : 31 + 4-bit addsub : 26 + 4-bit subtractor : 35 + 5-bit adder : 46 + 5-bit addsub : 4 + 5-bit subtractor : 21 + 50-bit adder : 2 + 50-bit subtractor : 2 + 6-bit adder : 12 + 6-bit subtractor : 10 + 64-bit subtractor : 1 + 7-bit adder : 3 + 8-bit adder : 23 + 9-bit adder : 1 +# Registers : 5197 + 1-bit register : 3170 + 10-bit register : 17 + 11-bit register : 2 + 112-bit register : 3 + 113-bit register : 2 + 12-bit register : 26 + 128-bit register : 12 + 129-bit register : 4 + 13-bit register : 13 + 130-bit register : 12 + 131-bit register : 4 + 139-bit register : 4 + 14-bit register : 16 + 146-bit register : 10 + 15-bit register : 5 + 153-bit register : 28 + 16-bit register : 106 + 169-bit register : 13 + 17-bit register : 20 + 177-bit register : 3 + 18-bit register : 7 + 182-bit register : 2 + 2-bit register : 297 + 20-bit register : 2 + 2048-bit register : 1 + 22-bit register : 1 + 24-bit register : 4 + 2448-bit register : 22 + 256-bit register : 3 + 27-bit register : 4 + 28-bit register : 24 + 3-bit register : 162 + 30-bit register : 1 + 31-bit register : 1 + 32-bit register : 245 + 33-bit register : 22 + 34-bit register : 37 + 4-bit register : 393 + 40-bit register : 34 + 41-bit register : 2 + 45-bit register : 5 + 48-bit register : 2 + 5-bit register : 105 + 50-bit register : 5 + 52-bit register : 4 + 56-bit register : 2 + 57-bit register : 1 + 59-bit register : 12 + 6-bit register : 160 + 61-bit register : 8 + 64-bit register : 19 + 65-bit register : 1 + 67-bit register : 6 + 7-bit register : 5 + 72-bit register : 26 + 79-bit register : 2 + 8-bit register : 91 + 81-bit register : 2 + 82-bit register : 2 + 9-bit register : 5 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 3346 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 71 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 1363 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 24 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 43 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 16 + 128-bit 16-to-1 multiplexer : 1 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 16 + 15-bit 2-to-1 multiplexer : 1 + 153-bit 16-to-1 multiplexer : 22 + 16-bit 2-to-1 multiplexer : 56 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 16-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 103 + 20-bit 2-to-1 multiplexer : 13 + 22-bit 2-to-1 multiplexer : 1 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 131 + 3-bit 3-to-1 multiplexer : 1 + 30-bit 2-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 320 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 47 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 32-to-1 multiplexer : 1 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 76 + 4-bit 4-to-1 multiplexer : 144 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 146 + 5-bit 8-to-1 multiplexer : 1 + 50-bit 2-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 3 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 86 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 5 + 8-bit 16-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 131 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 7 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 32-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 169-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 169-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 8-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 146-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 146-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 81-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 81-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 177-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 177-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 128-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 128-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 8-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 10-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 64-word x 8-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 256-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port block RAM : 5 + 1024x32-bit single-port block RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 16x256-bit single-port distributed Read Only RAM : 1 + 16x32-bit single-port distributed Read Only RAM : 4 + 2048x169-bit dual-port block RAM : 2 + 2048x32-bit dual-port block RAM : 8 + 256x2-bit single-port distributed Read Only RAM : 1 + 2x128-bit dual-port distributed RAM : 1 + 2x146-bit dual-port distributed RAM : 2 + 2x169-bit dual-port distributed RAM : 3 + 2x177-bit dual-port distributed RAM : 1 + 2x32-bit dual-port distributed RAM : 26 + 2x61-bit dual-port distributed RAM : 2 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 11 + 3x8-bit dual-port distributed RAM : 1 + 3x81-bit dual-port distributed RAM : 2 + 4x10-bit single-port distributed Read Only RAM : 1 + 4x16-bit single-port distributed Read Only RAM : 3 + 4x2-bit single-port distributed Read Only RAM : 9 + 4x3-bit single-port distributed Read Only RAM : 12 + 64x8-bit single-port distributed Read Only RAM : 1 + 8x10-bit dual-port distributed RAM : 1 + 8x8-bit dual-port distributed RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 416 + 1-bit adder : 101 + 10-bit subtractor : 15 + 11-bit adder : 2 + 12-bit adder : 4 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 5 + 14-bit subtractor : 4 + 16-bit adder : 13 + 16-bit subtractor : 4 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit subtractor : 1 + 2-bit adder : 22 + 2-bit adder carry in : 1 + 2-bit subtractor : 64 + 24-bit subtractor : 1 + 28-bit subtractor : 1 + 3-bit adder : 3 + 3-bit adder carry in : 1 + 3-bit subtractor : 8 + 32-bit adder : 40 + 32-bit subtractor : 3 + 4-bit adder : 5 + 4-bit subtractor : 30 + 5-bit adder : 4 + 5-bit addsub : 1 + 5-bit subtractor : 17 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 6 + 64-bit subtractor : 1 + 7-bit adder : 2 + 8-bit adder : 12 +# Adder Trees : 3 + 2-bit / 5-inputs adder tree : 1 + 5-bit / 9-inputs adder tree : 2 +# Counters : 394 + 1-bit up counter : 107 + 10-bit down counter : 1 + 10-bit up counter : 1 + 12-bit up counter : 9 + 16-bit down counter : 2 + 16-bit up counter : 23 + 16-bit updown counter : 8 + 18-bit up counter : 1 + 2-bit down counter : 8 + 2-bit up counter : 16 + 2-bit updown counter : 44 + 20-bit down counter : 1 + 22-bit down counter : 1 + 28-bit up counter : 3 + 3-bit down counter : 3 + 3-bit up counter : 15 + 30-bit up counter : 1 + 32-bit up counter : 57 + 4-bit down counter : 5 + 4-bit up counter : 26 + 4-bit updown counter : 26 + 5-bit down counter : 4 + 5-bit up counter : 12 + 5-bit updown counter : 3 + 6-bit down counter : 4 + 6-bit up counter : 2 + 7-bit up counter : 2 + 8-bit up counter : 8 + 9-bit up counter : 1 +# Accumulators : 40 + 12-bit up accumulator cin : 2 + 14-bit down loadable accumulator : 2 + 14-bit up accumulator : 5 + 16-bit up accumulator : 2 + 3-bit up accumulator cin : 22 + 32-bit up loadable accumulator : 1 + 4-bit up loadable accumulator : 1 + 50-bit up accumulator : 1 + 50-bit up loadable accumulator : 1 + 6-bit up accumulator : 1 + 8-bit up accumulator cin : 1 + 8-bit up loadable accumulator : 1 +# Registers : 38720 + Flip-Flops : 38720 +# Shift Registers : 3498 + 16-bit dynamic shift register : 3498 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 4618 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 15-to-1 multiplexer : 24 + 1-bit 16-to-1 multiplexer : 87 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 2613 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 32-to-1 multiplexer : 34 + 1-bit 4-to-1 multiplexer : 312 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 38 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 15 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 14 + 15-bit 2-to-1 multiplexer : 1 + 16-bit 2-to-1 multiplexer : 40 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 91 + 20-bit 2-to-1 multiplexer : 13 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 122 + 3-bit 3-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 287 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 36 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 56 + 4-bit 4-to-1 multiplexer : 72 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 31 + 5-bit 8-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 2 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 84 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 125 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 6 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 00001 | 000 + 00010 | 001 + 00100 | 010 + 01000 | 011 + 10000 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0001 | 00 + 0010 | 01 + 0100 | 11 + 1000 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0011 | 000 + 0110 | 001 + 0111 | 011 + 0001 | 010 + 1000 | 110 + 1001 | 111 + 0010 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------- + State | Encoding +---------------------------------------------------- + 0000000000000100000000000 | 000000000000000000001 + 0010000000000000000000000 | 000000000000000000010 + 0000100000000000000000000 | 000000000000000000100 + 0100000000000000000000000 | 000000000000000001000 + 1000000000000000000000000 | 000000000000000010000 + 0000000010000000000000000 | 000000000000000100000 + 0000000100000000000000000 | 000000000000001000000 + 0000000000000000000000010 | 000000000000010000000 + 0000001000000000000000000 | 000000000000100000000 + 0000000000000000000000001 | 000000000001000000000 + 0000000000010000000000000 | 000000000010000000000 + 0000000000000000010000000 | 000000000100000000000 + 0000010000000000000000000 | 000000001000000000000 + 0000000000000000000000100 | 000000010000000000000 + 0000000000000000000001000 | 000000100000000000000 + 0000000000000000001000000 | 000001000000000000000 + 0000000000100000000000000 | 000010000000000000000 + 0001000000000000000000000 | 000100000000000000000 + 0000000000000000100000000 | 001000000000000000000 + 0000000000000001000000000 | 010000000000000000000 + 0000000000000010000000000 | 100000000000000000000 +---------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 10 | 01 + 01 | 11 +------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------ + State | Encoding +------------------------------------ + 00000 | 0000000000000000000000001 + 11000 | 0000000000000000000000010 + 00001 | 0000000000000000000000100 + 00010 | 0000000000000000000001000 + 00011 | 0000000000000000000010000 + 00100 | 0000000000000000000100000 + 00111 | 0000000000000000001000000 + 01000 | 0000000000000000010000000 + 01001 | 0000000000000000100000000 + 01010 | 0000000000000001000000000 + 01011 | 0000000000000010000000000 + 01100 | 0000000000000100000000000 + 01111 | 0000000000001000000000000 + 10000 | 0000000000010000000000000 + 10001 | 0000000000100000000000000 + 10010 | 0000000001000000000000000 + 10011 | 0000000010000000000000000 + 10100 | 0000000100000000000000000 + 10111 | 0000001000000000000000000 + 00101 | 0000010000000000000000000 + 00110 | 0000100000000000000000000 + 01101 | 0001000000000000000000000 + 01110 | 0010000000000000000000000 + 10101 | 0100000000000000000000000 + 10110 | 1000000000000000000000000 +------------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------- + State | Encoding +-------------------- + 0000 | 000000001 + 0111 | 000000010 + 0001 | 000000100 + 0010 | 000001000 + 0101 | 000010000 + 0110 | 000100000 + 0011 | 001000000 + 0100 | 010000000 + 1010 | 100000000 +-------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 0000001 + 001 | 0000010 + 010 | 0000100 + 011 | 0001000 + 100 | 0010000 + 101 | 0100000 + 110 | 1000000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------------- + State | Encoding +------------------------------------------------- + 000000 | 0000000000000000000000000000000000001 + 000001 | 0000000000000000000000000000000000010 + 000010 | 0000000000000000000000000000000000100 + 000011 | 0000000000000000000000000000000001000 + 000100 | 0000000000000000000000000000000010000 + 010110 | 0000000000000000000000000000000100000 + 000101 | 0000000000000000000000000000001000000 + 000110 | 0000000000000000000000000000010000000 + 000111 | 0000000000000000000000000000100000000 + 001000 | 0000000000000000000000000001000000000 + 001001 | 0000000000000000000000000010000000000 + 001010 | 0000000000000000000000000100000000000 + 001011 | 0000000000000000000000001000000000000 + 001100 | 0000000000000000000000010000000000000 + 001101 | 0000000000000000000000100000000000000 + 010101 | 0000000000000000000001000000000000000 + 011010 | 0000000000000000000010000000000000000 + 011001 | 0000000000000000000100000000000000000 + 001111 | 0000000000000000001000000000000000000 + 010010 | 0000000000000000010000000000000000000 + 010100 | 0000000000000000100000000000000000000 + 010011 | 0000000000000001000000000000000000000 + 010111 | 0000000000000010000000000000000000000 + 011111 | 0000000000000100000000000000000000000 + 011000 | 0000000000001000000000000000000000000 + 011011 | 0000000000010000000000000000000000000 + 011100 | 0000000000100000000000000000000000000 + 010001 | 0000000001000000000000000000000000000 + 101000 | 0000000010000000000000000000000000000 + 001110 | 0000000100000000000000000000000000000 + 100011 | 0000001000000000000000000000000000000 + 101010 | 0000010000000000000000000000000000000 + 010000 | 0000100000000000000000000000000000000 + 011110 | unreached + 100000 | 0001000000000000000000000000000000000 + 100001 | 0010000000000000000000000000000000000 + 100010 | 0100000000000000000000000000000000000 + 100101 | unreached + 100100 | unreached + 100111 | unreached + 011101 | unreached + 101001 | 1000000000000000000000000000000000000 +------------------------------------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0100 | 0100 + 0011 | 0011 + 1000 | 1000 + 0111 | 0111 + 0110 | 0110 + 0101 | 0101 + 0010 | 0010 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 110 | 011 + 100 | 100 + 101 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00000 | 00000 + 00001 | 00001 + 00010 | 00010 + 00011 | 00011 + 01100 | 01100 + 01011 | 01011 + 00100 | 00100 + 00111 | 00111 + 00101 | 00101 + 01101 | 01101 + 00110 | 00110 + 01000 | 01000 + 10010 | 10010 + 01010 | 01010 + 01111 | 01111 + 01110 | 01110 + 10000 | 10000 + 01001 | 01001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0010 | 0010 + 0011 | 0011 + 0100 | 0100 + 0110 | 0110 + 0101 | 0101 + 0111 | 0111 + 1000 | 1000 + 1001 | 1001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 011 | 011 + 100 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1010 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0100 | 00000100000 + 0101 | 00001000000 + 0110 | 00010000000 + 0111 | 00100000000 + 1000 | 01000000000 + 1001 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. 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00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00111101 | 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 01000001 | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 10101010 | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------------------------------------------------------------------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +INFO:Xst:1901 - Instance use_ramb36.ramb36 in unit use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 +INFO:Xst:1901 - Instance GEN2_LINK.pipe_clk_bufgmux in unit pcie_clocking_v6 of type BUFGMUX has been replaced by BUFGCTRL +INFO:Xst:1901 - Instance gmii_rxc_dly in unit mkGMAC of type IODELAY has been replaced by IODELAYE1 +INFO:Xst:1901 - Instance gmii_rx_clk in unit mkGMAC of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 3. +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 16-bit shift register was found for signal and currently occupies 16 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 33-bit shift register was found for signal and currently occupies 33 logic cells (16 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 31-bit shift register was found for signal and currently occupies 31 logic cells (15 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 3-bit shift register for signal . +Unit processed. + +Processing Unit : + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 3-bit shift register for signal . + Found 16-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 4-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 34083 + Flip-Flops : 34083 +# Shift Registers : 44 + 10-bit shift register : 2 + 16-bit shift register : 5 + 2-bit shift register : 34 + 3-bit shift register : 2 + 4-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : fpgaTop.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 47176 +# BUF : 102 +# GND : 220 +# INV : 1309 +# LUT1 : 2525 +# LUT2 : 3318 +# LUT3 : 4452 +# LUT4 : 4179 +# LUT5 : 7016 +# LUT6 : 13955 +# MULT_AND : 90 +# MUXCY : 4699 +# MUXF7 : 684 +# MUXF8 : 72 +# VCC : 187 +# XORCY : 4368 +# FlipFlops/Latches : 34143 +# FD : 7167 +# FD_1 : 432 +# FDC : 480 +# FDCE : 1342 +# FDE : 10806 +# FDP : 146 +# FDPE : 58 +# FDR : 2129 +# FDRE : 9409 +# FDS : 112 +# FDSE : 2050 +# ODDR : 12 +# RAMS : 829 +# RAM32M : 432 +# RAM32X1D : 68 +# RAM64X1D : 288 +# RAMB18E1 : 3 +# RAMB36E1 : 38 +# Shift Registers : 2977 +# SRL16E : 5 +# SRLC16E : 2970 +# SRLC32E : 2 +# Clock Buffers : 12 +# BUFG : 11 +# BUFGCTRL : 1 +# IO Buffers : 232 +# IBUF : 29 +# IBUFDS : 2 +# IBUFDS_GTXE1 : 2 +# IOBUF : 81 +# IOBUFDS_DIFF_OUT : 8 +# OBUF : 109 +# OBUFDS : 1 +# GigabitIOs : 4 +# GTXE1 : 4 +# Others : 302 +# BUFIODQS : 9 +# BUFR : 3 +# DNA_PORT : 1 +# IDELAYCTRL : 1 +# IODELAYE1 : 91 +# ISERDESE1 : 72 +# MMCM_ADV : 2 +# OSERDESE1 : 122 +# PCIE_2_0 : 1 + +Device utilization summary: +--------------------------- + +Selected Device : 6vlx240tff1156-1 + + +Slice Logic Utilization: + Number of Slice Registers: 34143 out of 301440 11% + Number of Slice LUTs: 42171 out of 150720 27% + Number used as Logic: 36754 out of 150720 24% + Number used as Memory: 5417 out of 58400 9% + Number used as RAM: 2440 + Number used as SRL: 2977 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 57107 + Number with an unused Flip Flop: 22964 out of 57107 40% + Number with an unused LUT: 14936 out of 57107 26% + Number of fully used LUT-FF pairs: 19207 out of 57107 33% + Number of unique control sets: 2267 + +IO Utilization: + Number of IOs: 242 + Number of bonded IOBs: 237 out of 600 39% + +Specific Feature Utilization: + Number of Block RAM/FIFO: 40 out of 416 9% + Number using Block RAM only: 40 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT0 | 550 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT1 | 27930 | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | BUFGCTRL | 418 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDWE | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i)| 1 | +sys1_clkp | IBUF+IBUFDS_GTXE1+BUFG | 119 | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | BUFR | 134 | +sys0_clkp | MMCM_ADV:CLKOUT1 | 6206 | +flp_cdc_clk_p | IBUFDS+BUFG | 20 | +ftop/fmc150/spiCDC_cd/cntr_2 | BUFG | 76 | +ftop/fmc150/spiDAC_cd/cntr_3 | BUFG | 31 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| BUFR | 928 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| BUFR | 1542 | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/ctop/app/appW2/wmiM0_MDataValid(ftop/ctop/app/appW2/XST_GND:G) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 4 | +ftop/ctop/app/appW4/wmiM0_MAddrSpace(ftop/ctop/app/appW4/XST_GND:G) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 4 | +ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4605_o(ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4605_o1_INV_0:O) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i) | 3 | +ftop/ctop/app/appW2/respF_pwEnqueue_whas(ftop/ctop/app/appW2/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/app/appW4/respF_pwEnqueue_whas(ftop/ctop/app/appW4/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/inf/cp/rom_memory/DO<16>(ftop/ctop/inf/cp/rom_memory/XST_GND:G) | NONE(ftop/ctop/inf/cp/rom_memory/Mram_RAM1) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/N0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/XST_VCC:P) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0:Q) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/gbe0/gmac/CLK_GATE_rxclkBnd(ftop/gbe0/gmac/XST_VCC:P) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +ftop/gbe0/gmac/txRS_txER(ftop/gbe0/gmac/XST_GND:G) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -1 + + Minimum period: 4.758ns (Maximum Frequency: 210.172MHz) + Minimum input arrival time before clock: 1.793ns + Maximum output required time after clock: 1.923ns + Maximum combinational path delay: 0.538ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Clock period: 4.158ns (frequency: 240.483MHz) + Total number of paths / destination ports: 11817309 / 78724 +------------------------------------------------------------------------- +Delay: 8.317ns (Levels of Logic = 14) + Source: ftop/ctop/inf/cp/cpReq_37 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_0 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/ctop/inf/cp/cpReq_37 to ftop/ctop/inf/cp/cpRespF/data1_reg_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDSE:C->Q 51 0.375 0.648 cpReq_37 (cpReq_37) + LUT2:I0->O 35 0.068 0.570 n0613<37>1 (n0613) + LUT6:I5->O 164 0.068 0.580 Mmux__theResult_____1__h7819031 (_theResult_____1__h78190<2>) + MUXF7:S->O 1 0.267 0.000 Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7 (Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_4_f7) + MUXF8:I0->O 12 0.175 0.489 Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 (CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884) + LUT5:I4->O 1 0.068 0.417 WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F1_SW1 (N958) + LUT5:I4->O 23 0.068 0.557 WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F1) + LUT5:I4->O 3 0.068 0.431 WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F) + LUT5:I4->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead14_SW0 (N956) + LUT4:I3->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead14 (WILL_FIRE_RL_completeWorkerRead14) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead16 (WILL_FIRE_RL_completeWorkerRead16) + LUT6:I5->O 20 0.068 0.542 WILL_FIRE_RL_completeWorkerRead31 (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 6 0.068 0.450 cpRespF_ENQ1 (cpRespF_ENQ) + begin scope: 'ftop/ctop/inf/cp/cpRespF:ENQ' + LUT2:I1->O 40 0.068 0.553 d1di1 (d1di) + FDE:CE 0.263 data1_reg_0 + ---------------------------------------- + Total 8.317ns (1.828ns logic, 6.489ns route) + (22.0% logic, 78.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125' + Clock period: 3.724ns (frequency: 268.528MHz) + Total number of paths / destination ports: 4781 / 823 +------------------------------------------------------------------------- +Delay: 3.724ns (Levels of Logic = 5) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + + Data Path: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 4 0.375 0.798 state_FSM_FFd5 (state_FSM_FFd5) + LUT6:I0->O 1 0.068 0.491 nextwaitcounter2<7>112 (nextwaitcounter2<7>112) + LUT6:I4->O 2 0.068 0.423 nextwaitcounter2<7>113 (nextwaitcounter2<7>11) + LUT4:I3->O 2 0.068 0.423 nextwaitcounter2<1>31 (nextwaitcounter2<1>3) + LUT6:I5->O 14 0.068 0.863 nextwaitcounter2<0>11 (nextwaitcounter2<0>1) + LUT6:I0->O 1 0.068 0.000 nextwaitcounter<4>1 (nextwaitcounter<4>) + FDR:D 0.011 waitcounter_4 + ---------------------------------------- + Total 3.724ns (0.726ns logic, 2.998ns route) + (19.5% logic, 80.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys1_clkp' + Clock period: 3.831ns (frequency: 261.028MHz) + Total number of paths / destination ports: 6108 / 281 +------------------------------------------------------------------------- +Delay: 3.831ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Source Clock: sys1_clkp rising + Destination Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.375 0.795 txRS_ifgCnt_value_2 (txRS_ifgCnt_value_2) + LUT6:I1->O 12 0.068 0.563 WILL_FIRE_RL_txRS_egress_SOF31 (Mmux_txRS_txData_D_IN122) + LUT6:I4->O 8 0.068 0.463 Mmux_txRS_crc_add_data11 (Mmux_txRS_crc_add_data11) + LUT2:I1->O 15 0.068 0.867 Mmux_txRS_crc_add_data21 (txRS_crc_add_data<1>) + begin scope: 'ftop/gbe0/gmac/txRS_crc:add_data<1>' + LUT6:I1->O 1 0.068 0.417 rRemainder$D_IN<5>1 (rRemainder$D_IN<5>1) + LUT5:I4->O 1 0.068 0.000 rRemainder$D_IN<5>3 (rRemainder$D_IN<5>) + FDSE:D 0.011 rRemainder_5 + ---------------------------------------- + Total 3.831ns (0.726ns logic, 3.105ns route) + (19.0% logic, 81.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Clock period: 3.576ns (frequency: 279.622MHz) + Total number of paths / destination ports: 2172 / 314 +------------------------------------------------------------------------- +Delay: 3.576ns (Levels of Logic = 4) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Source Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 18 0.375 0.603 dSyncReg2 (dSyncReg2) + end scope: 'ftop/gbe0/gmac/rxRS_rxOperateS:dD_OUT' + LUT3:I1->O 49 0.068 0.931 _n0454_inv211 (WILL_FIRE_RL_rxRS_ingress_advance) + LUT6:I1->O 2 0.068 0.781 _n0454_inv2 (_n0454_inv2) + LUT5:I0->O 4 0.068 0.419 _n0454_inv1 (_n0454_inv) + FDRE:CE 0.263 rxRS_preambleCnt_value_0 + ---------------------------------------- + Total 3.576ns (0.842ns logic, 2.734ns route) + (23.5% logic, 76.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 4.758ns (frequency: 210.172MHz) + Total number of paths / destination ports: 166452 / 12719 +------------------------------------------------------------------------- +Delay: 4.758ns (Levels of Logic = 13) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl (FF) + Source Clock: sys0_clkp rising + Destination Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.375 0.784 io_config_r_1 (io_config_r_1) + LUT6:I0->O 1 0.068 0.417 Mmux_io_config_ns41 (Mmux_io_config_ns4) + LUT6:I5->O 1 0.068 0.417 Mmux_io_config_ns42 (Mmux_io_config_ns41) + LUT5:I4->O 20 0.068 0.542 Mmux_io_config_ns43 (dfi_odt_nom1<0>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:io_config<1>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:io_config<1>' + LUT4:I3->O 4 0.068 0.511 inhbt_wr_config11 (inhbt_wr_config) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:inhbt_wr_config' + LUT6:I4->O 6 0.068 0.808 rtc (rtc) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:rtc' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:rtc' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:rtc<2>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0:rtc<2>' + LUT6:I1->O 1 0.068 0.417 io_config_valid_ns_norst2 (io_config_valid_ns_norst2) + LUT2:I1->O 1 0.068 0.000 io_config_valid_ns_norst3 (io_config_valid_ns_norst) + FDR:D 0.011 io_config_valid_r_lcl + ---------------------------------------- + Total 4.758ns (0.862ns logic, 3.896ns route) + (18.1% logic, 81.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'flp_cdc_clk_p' + Clock period: 4.676ns (frequency: 213.858MHz) + Total number of paths / destination ports: 12407 / 37 +------------------------------------------------------------------------- +Delay: 4.676ns (Levels of Logic = 7) + Source: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 (FF) + Destination: ftop/fmc150/fcCdc_grayCounter_rsCounter_0 (FF) + Source Clock: flp_cdc_clk_p rising + Destination Clock: flp_cdc_clk_p rising + + Data Path: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 to ftop/fmc150/fcCdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 5 0.375 0.802 fcCdc_grayCounter_rsCounter_16 (fcCdc_grayCounter_rsCounter_16) + LUT6:I1->O 3 0.068 0.595 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>2 (Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>1) + LUT3:I0->O 14 0.068 0.502 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>4 (fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454) + LUT6:I5->O 13 0.068 0.571 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d49014 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490<0>) + LUT6:I4->O 1 0.068 0.638 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o_91 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o_91) + LUT6:I2->O 1 0.068 0.000 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o_4 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o_4) + MUXF7:I0->O 18 0.245 0.529 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o_2_f7 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_181_o_Mux_53_o) + LUT6:I5->O 1 0.068 0.000 Mmux_MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_181 (MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_1<16>) + FDC:D 0.011 fcCdc_grayCounter_rsCounter_16 + ---------------------------------------- + Total 4.676ns (1.039ns logic, 3.637ns route) + (22.2% logic, 77.8% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Clock period: 3.708ns (frequency: 269.687MHz) + Total number of paths / destination ports: 745 / 184 +------------------------------------------------------------------------- +Delay: 3.708ns (Levels of Logic = 7) + Source: ftop/fmc150/spiCDC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiCDC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_slowReset/reset_hold_1 to ftop/fmc150/spiCDC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 9 0.375 0.470 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiCDC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiCDC_reqF_dInReset:RST' + INV:I->O 8 0.086 0.824 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiCDC_reqF_dInReset:VAL' + LUT6:I0->O 4 0.068 0.511 MUX_spiCDC_rcv_d_write_1__SEL_21 (MUX_spiCDC_rcv_d_write_1__SEL_2) + LUT4:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable91 (Reset_OR_DriverANDClockEnable9) + FDRE:R 0.434 spiCDC_reqF_head_wrapped + ---------------------------------------- + Total 3.708ns (1.099ns logic, 2.609ns route) + (29.6% logic, 70.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Clock period: 3.785ns (frequency: 264.201MHz) + Total number of paths / destination ports: 336 / 69 +------------------------------------------------------------------------- +Delay: 3.785ns (Levels of Logic = 8) + Source: ftop/fmc150/spiDAC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiDAC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_slowReset/reset_hold_1 to ftop/fmc150/spiDAC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 6 0.375 0.450 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiDAC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiDAC_reqF_dInReset:RST' + INV:I->O 5 0.086 0.444 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiDAC_reqF_dInReset:VAL' + LUT6:I5->O 13 0.068 0.497 WILL_FIRE_RL_spiDAC_doxcv_d1 (WILL_FIRE_RL_spiDAC_doxcv_d) + LUT5:I4->O 2 0.068 0.423 spiDAC_reqF_head_wrapped_EN1 (spiDAC_reqF_head_wrapped_EN) + LUT3:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable101 (Reset_OR_DriverANDClockEnable10) + FDRE:R 0.434 spiDAC_reqF_head_wrapped + ---------------------------------------- + Total 3.785ns (1.167ns logic, 2.618ns route) + (30.8% logic, 69.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 2069 / 1093 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 3439 / 1815 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 25 / 25 +------------------------------------------------------------------------- +Offset: 1.457ns (Levels of Logic = 4) + Source: pci0_reset_n (PAD) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 (FF) + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising + + Data Path: pci0_reset_n to ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 pci0_reset_n_IBUF (pci0_reset_n_IBUF) + begin scope: 'ftop:pci0_rstn' + begin scope: 'ftop/pciw_pci0_pcie_ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i:sys_reset_n' + INV:I->O 22 0.086 0.535 sys_reset_n_inv1_INV_0 (sys_reset_n_inv) + FDCE:CLR 0.434 reg_count_23_16_0 + ---------------------------------------- + Total 1.457ns (0.523ns logic, 0.934ns route) + (35.9% logic, 64.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0/gmac:gmii_rx_rxd_i<0>' + FD:D 0.011 rxRS_rxData_0 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 75 / 75 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: ppsExtIn (PAD) + Destination: ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 (FF) + Destination Clock: sys0_clkp rising + + Data Path: ppsExtIn to ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 ppsExtIn_IBUF (ppsExtIn_IBUF) + begin scope: 'ftop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf/cp:gps_ppsSyncIn_x' + FDR:D 0.011 timeServ_ppsExtSync_d1 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_cdc_sdi (PAD) + Destination: ftop/fmc150/spiCDC_sdiP (FF) + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 falling + + Data Path: flp_cdc_sdi to ftop/fmc150/spiCDC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_cdc_sdi_IBUF (flp_cdc_sdi_IBUF) + begin scope: 'ftop:flpCDC_sdi_arg' + begin scope: 'ftop/fmc150:padsCDC_sdi_arg' + FD:D 0.011 spiCDC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_dac_sdi (PAD) + Destination: ftop/fmc150/spiDAC_sdiP (FF) + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 falling + + Data Path: flp_dac_sdi to ftop/fmc150/spiDAC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_dac_sdi_IBUF (flp_dac_sdi_IBUF) + begin scope: 'ftop:flpDAC_sdi_arg' + begin scope: 'ftop/fmc150:padsDAC_sdi_arg' + FD:D 0.011 spiDAC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 1665 / 675 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 999 / 405 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 79 / 62 +------------------------------------------------------------------------- +Offset: 1.360ns (Levels of Logic = 4) + Source: ftop/flash0/flashC_tsOE (FF) + Destination: flash_io_dq<15> (PAD) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/flash0/flashC_tsOE to flash_io_dq<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.399 flashC_tsOE (flashC_tsOE) + begin scope: 'ftop/flash0/flashC_tsd:OE' + INV:I->O 16 0.086 0.497 OE_inv1_INV_0 (OE_inv) + IOBUF:T->IO 0.003 IO_15_IOBUF (IO<15>) + end scope: 'ftop/flash0/flashC_tsd:IO<15>' + end scope: 'ftop/flash0:flash_io_dq<15>' + end scope: 'ftop:flash_io_dq<15>' + ---------------------------------------- + Total 1.360ns (0.464ns logic, 0.896ns route) + (34.1% logic, 65.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys1_clkp' + Total number of paths / destination ports: 12 / 12 +------------------------------------------------------------------------- +Offset: 1.009ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Destination: gmii_txd<7> (PAD) + Source Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_iobTxData_7 to gmii_txd<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ODDR:C->Q 1 0.607 0.399 txRS_iobTxData_7 (gmii_tx_txd<7>) + end scope: 'ftop/gbe0/gmac:gmii_tx_txd<7>' + end scope: 'ftop/gbe0:gmii_tx_txd<7>' + end scope: 'ftop:gmii_tx_txd<7>' + OBUF:I->O 0.003 gmii_txd_7_OBUF (gmii_txd<7>) + ---------------------------------------- + Total 1.009ns (0.610ns logic, 0.399ns route) + (60.5% logic, 39.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 1228 / 1056 +------------------------------------------------------------------------- +Offset: 1.870ns (Levels of Logic = 5) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST (PAD) + Source Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDP:C->Q 3 0.375 0.413 rstdiv0_sync_r_32 (rstdiv0_sync_r_32) + end scope: 'ftop/dram0/memc_memc/u_infrastructure:rstdiv0' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top:rst' + BUF:I->O 10 0.086 0.458 rst_1 (rst_1) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0:rst' + BUF:I->O 9 0.086 0.452 rst_8 (rst_8) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob:rst' + OSERDESE1:RST 0.000 u_oserdes_ck_p + ---------------------------------------- + Total 1.870ns (0.547ns logic, 1.323ns route) + (29.3% logic, 70.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 5 / 4 +------------------------------------------------------------------------- +Offset: 1.923ns (Levels of Logic = 4) + Source: ftop/fmc150/spiCDC_csbR (FF) + Destination: flp_com_sclk (PAD) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_csbR to flp_com_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 2 0.375 0.405 spiCDC_csbR (spiCDC_csbR) + INV:I->O 2 0.086 0.587 spiCDC_csbR_inv1_INV_0 (padsCDC_sclkgate) + end scope: 'ftop/fmc150:padsCDC_sclkgate' + end scope: 'ftop:flpCDC_sclkgate' + LUT4:I1->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.923ns (0.532ns logic, 1.391ns route) + (27.7% logic, 72.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 1.336ns (Levels of Logic = 3) + Source: ftop/fmc150/spiDAC_sdoR (FF) + Destination: flp_com_sdc2m (PAD) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_sdoR to flp_com_sdc2m + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.491 spiDAC_sdoR (spiDAC_sdoR) + end scope: 'ftop/fmc150:padsDAC_sdo' + end scope: 'ftop:flpDAC_sdo' + LUT4:I2->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.336ns (0.446ns logic, 0.890ns route) + (33.4% logic, 66.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 250 / 250 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_39 (dlyval_dq_39) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 150 / 150 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_14 (dlyval_dq_14) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 596 / 532 +------------------------------------------------------------------------- +Delay: 0.538ns (Levels of Logic = 3) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB (PAD) + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BUFIODQS:O 9 0.000 0.000 gen_ck_cpt[7].u_bufio_cpt (clk_cpt<7>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen:clk_cpt<7>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob:clk_cpt' + INV:I->O 0 0.086 0.000 iserdes_clkb1_INV_0 (iserdes_clkb) + ISERDESE1:CLKB 0.000 u_iserdes_dqs_p + ---------------------------------------- + Total 0.538ns (0.538ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock flp_cdc_clk_p +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 4.676| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.824| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiCDC_cd/cntr_2 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiCDC_cd/cntr_2 | 3.708| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.854| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiDAC_cd/cntr_3 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiDAC_cd/cntr_3 | 3.785| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.951| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 3.576| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.860| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 0.857| | | | +ftop/fmc150/spiCDC_cd/cntr_2 | 5.230| | | | +ftop/fmc150/spiDAC_cd/cntr_3 | 5.350| | | | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 2.078| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 8.317| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | 2.324| | | | +sys0_clkp | 2.712| | | | +sys1_clkp | 1.727| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 +-------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +-------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125| 3.724| | | | +-------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 1.675| | | | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 1.675| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | 2.229| | | | +sys0_clkp | 4.758| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 2.078| | | | +sys1_clkp | 3.831| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 346.00 secs +Total CPU time to Xst completion: 343.86 secs + +--> + + +Total memory usage is 1415024 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2463 ( 0 filtered) +Number of infos : 409 ( 0 filtered) + diff --git a/logs/ml605-20140127_1142/fpgaTop.bld b/logs/ml605-20140127_1142/fpgaTop.bld new file mode 100644 index 00000000..666cfc3d --- /dev/null +++ b/logs/ml605-20140127_1142/fpgaTop.bld @@ -0,0 +1,5797 @@ +Release 14.7 ngdbuild P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: /home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_trn_v6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc ml605.ucf -p xc6vlx240t-ff1156-1 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-ml605/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "ml605.ucf" ... +WARNING:NgdBuild - The value of SIM_DEVICE on instance + 'ftop/gbe0/gmac/rxClk_BUFR' of type BUFR has been changed from 'VIRTEX4' to + 'VIRTEX6' to correct post-ngdbuild and timing simulation for this primitive. + In order for functional simulation to be correct, the value of SIM_DEVICE + should be changed in this same manner in the source netlist or constraint + file. +Resolving constraint associations... +Checking Constraint Associations... +WARNING:ConstraintSystem - Constraint + [ml605.ucf(46)] was not distributed to the output pin TXOUTCLK of block + GTXD[0].GTX because the signal path to this output pin depends upon block + attribute settings. Constraint distribution does not support attribute + dependent distribution. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(113)]: NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(113)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(113)]: + NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(125)]: NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(125)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(125)]: + NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(126)]: NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(126)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(126)]: + NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(127)]: NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(127)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(127)]: + NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(281)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(286)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(287)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(294)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:58 - Constraint [ml605.ucf(761)]: INST + "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon" does not match any + design objects. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(761)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(768)]: INST "ftop/dram0/memc/u_infrastructure/u_mmcm_adv" not + found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(768)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(769)]: INST + "ftop/dram0/memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_ge + n/u_mmcm_clk_base" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(769)]' could not be + found and so the Locate constraint will be removed. + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT1: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT2: + +Done... + +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N100' has no driver +WARNING:NgdBuild:452 - logical net 'N101' has no driver +WARNING:NgdBuild:452 - logical net 'N102' has no driver +WARNING:NgdBuild:452 - logical net 'N103' has no driver +WARNING:NgdBuild:452 - logical net 'N104' has no driver +WARNING:NgdBuild:452 - logical net 'N105' has no driver +WARNING:NgdBuild:452 - logical net 'N106' has no driver +WARNING:NgdBuild:452 - logical net 'N107' has no driver +WARNING:NgdBuild:452 - logical net 'N108' has no driver +WARNING:NgdBuild:452 - logical net 'N109' has no driver +WARNING:NgdBuild:452 - logical net 'N110' has no driver +WARNING:NgdBuild:452 - logical net 'N111' has no driver +WARNING:NgdBuild:452 - logical net 'N112' has no driver +WARNING:NgdBuild:452 - logical net 'N113' has no driver +WARNING:NgdBuild:452 - logical net 'N114' has no driver +WARNING:NgdBuild:452 - logical net 'N115' has no driver +WARNING:NgdBuild:452 - logical net 'N116' has no driver +WARNING:NgdBuild:452 - logical net 'N117' has no driver +WARNING:NgdBuild:452 - logical net 'N118' has no driver +WARNING:NgdBuild:452 - logical net 'N119' has no driver +WARNING:NgdBuild:452 - logical net 'N120' has no driver +WARNING:NgdBuild:452 - logical net 'N121' has no driver +WARNING:NgdBuild:452 - logical net 'N122' has no driver +WARNING:NgdBuild:452 - logical net 'N123' has no driver +WARNING:NgdBuild:452 - logical net 'N124' has no driver +WARNING:NgdBuild:452 - logical net 'N125' has no driver +WARNING:NgdBuild:452 - logical net 'N126' has no driver +WARNING:NgdBuild:452 - logical net 'N127' has no driver +WARNING:NgdBuild:452 - logical net 'N128' has no driver +WARNING:NgdBuild:452 - logical net 'N129' has no driver +WARNING:NgdBuild:452 - logical net 'N130' has no driver +WARNING:NgdBuild:452 - logical net 'N131' has no driver +WARNING:NgdBuild:452 - logical net 'N132' has no driver +WARNING:NgdBuild:452 - logical net 'N133' has no driver +WARNING:NgdBuild:452 - logical net 'N134' has no driver +WARNING:NgdBuild:452 - logical net 'N135' has no driver +WARNING:NgdBuild:452 - logical net 'N136' has no driver +WARNING:NgdBuild:452 - logical net 'N137' has no driver +WARNING:NgdBuild:452 - logical net 'N138' has no driver +WARNING:NgdBuild:452 - logical net 'N139' has no driver +WARNING:NgdBuild:452 - logical net 'N140' has no driver +WARNING:NgdBuild:452 - logical net 'N141' has no driver +WARNING:NgdBuild:452 - logical net 'N142' has no driver +WARNING:NgdBuild:452 - logical net 'N143' has no driver +WARNING:NgdBuild:452 - logical net 'N144' has no driver +WARNING:NgdBuild:452 - logical net 'N145' has no driver +WARNING:NgdBuild:452 - logical net 'N146' has no driver +WARNING:NgdBuild:452 - logical net 'N147' has no driver +WARNING:NgdBuild:452 - logical net 'N148' has no driver +WARNING:NgdBuild:452 - logical net 'N149' has no driver +WARNING:NgdBuild:452 - logical net 'N150' has no driver +WARNING:NgdBuild:452 - logical net 'N151' has no driver +WARNING:NgdBuild:452 - logical net 'N152' has no driver +WARNING:NgdBuild:452 - logical net 'N153' has no driver +WARNING:NgdBuild:452 - logical net 'N154' has no driver +WARNING:NgdBuild:452 - logical net 'N155' has no driver +WARNING:NgdBuild:452 - logical net 'N156' has no driver +WARNING:NgdBuild:452 - logical net 'N157' has no driver +WARNING:NgdBuild:452 - logical net 'N158' has no driver +WARNING:NgdBuild:452 - logical net 'N159' has no driver +WARNING:NgdBuild:452 - logical net 'N160' has no driver +WARNING:NgdBuild:452 - logical net 'N161' has no driver +WARNING:NgdBuild:452 - logical net 'N162' has no driver +WARNING:NgdBuild:452 - logical net 'N163' has no driver +WARNING:NgdBuild:452 - logical net 'N164' has no driver +WARNING:NgdBuild:452 - logical net 'N165' has no driver +WARNING:NgdBuild:452 - logical net 'N166' has no driver +WARNING:NgdBuild:452 - logical net 'N167' has no driver +WARNING:NgdBuild:452 - logical net 'N168' has no driver +WARNING:NgdBuild:452 - logical net 'N169' has no driver +WARNING:NgdBuild:452 - logical net 'N170' has no driver +WARNING:NgdBuild:452 - logical net 'N171' has no driver +WARNING:NgdBuild:452 - logical net 'N172' has no driver +WARNING:NgdBuild:452 - logical net 'N173' has no driver +WARNING:NgdBuild:452 - logical net 'N174' has no driver +WARNING:NgdBuild:452 - logical net 'N175' has no driver +WARNING:NgdBuild:452 - logical net 'N176' has no driver +WARNING:NgdBuild:452 - logical net 'N177' has no driver +WARNING:NgdBuild:452 - logical net 'N178' has no driver +WARNING:NgdBuild:452 - logical net 'N179' has no driver +WARNING:NgdBuild:452 - logical net 'N180' has no driver +WARNING:NgdBuild:452 - logical net 'N181' has no driver +WARNING:NgdBuild:452 - logical net 'N182' has no driver +WARNING:NgdBuild:452 - logical net 'N183' has no driver +WARNING:NgdBuild:452 - logical net 'N184' has no driver +WARNING:NgdBuild:452 - logical net 'N185' has no driver +WARNING:NgdBuild:452 - logical net 'N186' has no driver +WARNING:NgdBuild:452 - logical net 'N187' has no driver +WARNING:NgdBuild:452 - logical net 'N188' has no driver +WARNING:NgdBuild:452 - logical net 'N189' has no driver +WARNING:NgdBuild:452 - logical net 'N190' has no driver +WARNING:NgdBuild:452 - logical net 'N191' has no driver +WARNING:NgdBuild:452 - logical net 'N192' has no driver +WARNING:NgdBuild:452 - logical net 'N193' has no driver +WARNING:NgdBuild:452 - logical net 'N194' has no driver +WARNING:NgdBuild:452 - logical net 'N195' has no driver +WARNING:NgdBuild:452 - logical net 'N196' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/upads_cts_arg' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_led' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0_wmemiS0_SRespLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<15>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<14>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<13>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<12>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<11>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<10>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_to_turnoff_n' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<1>' has no driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_dram_clk_disable' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_reset_n' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_cas_n1' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<21>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<20>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<19>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<18>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<172>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<46>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<9>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<8>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<179>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_ra' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_a<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/io_config_ns<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/m + aintenance_request.maint_grant_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<0> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<1> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<2> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<3> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/low_idle_cnt_r + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/was_priority' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd0_col' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd1_row' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<15>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<14>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<13>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<12>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<11>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<10>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<9>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<23>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<22>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<21>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<20>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<19>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<18>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<17>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<31>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<30>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<29>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<28>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<27>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<26>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<25>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<0>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<39>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<38>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<37>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<36>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<35>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<34>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<33>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<32>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<31>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<30>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<29>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<28>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<27>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<26>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<25>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<24>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<23>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<22>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<21>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<20>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<19>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<18>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<17>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<16>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<15>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<14>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<13>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<12>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<11>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<10>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<9>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<8>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/pd_prech_req' has no + driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 2508 + +Total memory usage is 832072 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 47 sec +Total CPU time to NGDBUILD completion: 47 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/ml605-20140127_1142/fpgaTop.par b/logs/ml605-20140127_1142/fpgaTop.par new file mode 100644 index 00000000..54aaf228 --- /dev/null +++ b/logs/ml605-20140127_1142/fpgaTop.par @@ -0,0 +1,1219 @@ +Release 14.7 par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +ar-cms520:: Mon Jan 27 11:32:44 2014 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '6vlx240t.nph' in environment /home/shep/ISE/14.7/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) + + +Device speed data version: "PRODUCTION 1.17 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 33,952 out of 301,440 11% + Number used as Flip Flops: 33,945 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 42,089 out of 150,720 27% + Number used as logic: 36,207 out of 150,720 24% + Number using O6 output only: 32,631 + Number using O5 output only: 2,408 + Number using O5 and O6: 1,168 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 799 + Number with same-slice register load: 667 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,438 out of 37,680 43% + Number of LUT Flip Flop pairs used: 49,974 + Number with an unused Flip Flop: 17,072 out of 49,974 34% + Number with an unused LUT: 7,885 out of 49,974 15% + Number of fully used LUT-FF pairs: 25,017 out of 49,974 50% + Number of slice register sites lost + to control set restrictions: 0 out of 301,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + + +Overall effort level (-ol): Standard +Router effort level (-rl): High + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +Starting initial Timing Analysis. REAL time: 40 secs +Finished initial Timing Analysis. REAL time: 41 secs + +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal upads_cts_arg_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/bluart/rxF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMB_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<29> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<7> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<31> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<17> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<19> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMB_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<173> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<145> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem27_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/txRS_txF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +Starting Router + + +Phase 1 : 255286 unrouted; REAL time: 47 secs + +Phase 2 : 218526 unrouted; REAL time: 1 mins 2 secs + +Phase 3 : 72359 unrouted; REAL time: 1 mins 52 secs + +Phase 4 : 72260 unrouted; (Setup:20311, Hold:30836, Component Switching Limit:0) REAL time: 2 mins 8 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:26207, Hold:28217, Component Switching Limit:0) REAL time: 3 mins 26 secs + +Phase 6 : 0 unrouted; (Setup:24499, Hold:28217, Component Switching Limit:0) REAL time: 4 mins 1 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 7 : 0 unrouted; (Setup:24499, Hold:28217, Component Switching Limit:0) REAL time: 5 mins 21 secs + +Phase 8 : 0 unrouted; (Setup:24499, Hold:28217, Component Switching Limit:0) REAL time: 5 mins 21 secs + +Phase 9 : 0 unrouted; (Setup:24499, Hold:28217, Component Switching Limit:0) REAL time: 5 mins 21 secs + +Phase 10 : 0 unrouted; (Setup:24499, Hold:0, Component Switching Limit:0) REAL time: 5 mins 26 secs + +Phase 11 : 0 unrouted; (Setup:20558, Hold:0, Component Switching Limit:0) REAL time: 5 mins 39 secs +Total REAL time to Router completion: 5 mins 39 secs +Total CPU time to Router completion: 6 mins 3 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/p125clk |BUFGCTRL_X0Y29| No | 7905 | 0.466 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| _tb_clk |BUFGCTRL_X0Y25| No | 2140 | 0.330 | 1.953 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/rxclkBnd | Regional Clk| No | 43 | 0.174 | 1.076 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/sys0_clk_O_BUFG | | | | | | +| | BUFGCTRL_X0Y1| No | 235 | 0.359 | 1.947 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1_clk_O |BUFGCTRL_X0Y24| No | 57 | 0.272 | 1.891 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/pipe_clk |BUFGCTRL_X0Y30| No | 182 | 0.418 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep_trn_clk |BUFGCTRL_X0Y28| No | 235 | 0.177 | 1.777 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<1> | Regional Clk|Yes | 432 | 0.197 | 1.040 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<0> | Regional Clk|Yes | 283 | 0.206 | 1.044 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpDAC_sclk | BUFGCTRL_X0Y3| No | 16 | 0.025 | 1.663 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpCDC_sclk | BUFGCTRL_X0Y2| No | 28 | 0.040 | 1.664 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flp_clk_O_BUFG | BUFGCTRL_X0Y0| No | 9 | 0.018 | 1.657 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/TxOutClk_bufg |BUFGCTRL_X0Y31| No | 6 | 0.008 | 1.640 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_mem |BUFGCTRL_X0Y26| No | 186 | 0.164 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_I1 | Local| | 3 | 0.000 | 0.997 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_309_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.281 | 0.636 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| I1 | Local| | 3 | 0.000 | 2.206 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| OUT | Local| | 2 | 0.000 | 0.359 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_OUT | Local| | 2 | 0.000 | 0.236 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/ctop/inf/cp/dna | | | | | | +| _cnt<0> | Local| | 13 | 0.000 | 2.816 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<7> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_wr_i | Local| | 10 | 0.402 | 1.403 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<6> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<2> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<3> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<4> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<5> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<0> | Local| | 18 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_clk_O | | | | | | +| | Local| | 8 | 0.000 | 2.396 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<1> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_301_ML_NE | | | | | | +| W_CLK | Local| | 2 | 0.000 | 0.365 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 20558 (Setup: 20558, Hold: 0, Component Switching Limit: 0) + +WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. + + Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options + are set in the tools for timing closure. + + Increase the PAR Effort Level setting to "high" + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + + Visit the Xilinx technical support web at http://support.xilinx.com and go to + either "Troubleshoot->Tech Tips->Timing & Constraints" or " + TechXclusives->Timing Closure" for tips and suggestions for meeting timing + in your design. + +Number of Timing Constraints that were not applied: 13 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- +* TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | SETUP | -0.307ns| 4.307ns| 90| 11862 + PCICLK HIGH 50% PRIORITY 1 | HOLD | 0.000ns| | 0| 0 + | MINPERIOD | 0.000ns| 4.000ns| 0| 0 +---------------------------------------------------------------------------------------------------------- +* TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | -0.287ns| 8.287ns| 68| 8696 + PCICLK / 2 HIGH 50% PRIORITY 100 | HOLD | 0.004ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | SETUP | 0.012ns| 4.988ns| 0| 0 + clk_pll = PERIOD TIMEGRP "ftop_dr | HOLD | 0.055ns| | 0| 0 + am0_memc_memc_u_infrastructure_clk_pll" T | | | | | + S_SYS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + Pin to Pin Skew Constraint | MAXDELAY | 0.108ns| 0.450ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALI | SETUP | 0.236ns| 0.264ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 2.040ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 | SETUP | 0.266ns| 4.734ns| 0| 0 + MHz HIGH 50% | HOLD | 0.067ns| | 0| 0 + | MINPERIOD | 0.239ns| 4.761ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VAL | SETUP | 0.268ns| 0.232ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 2.161ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VAL | SETUP | 0.304ns| 0.196ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 2.103ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VAL | SETUP | 0.348ns| 0.152ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.947ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VAL | SETUP | 0.384ns| 0.116ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.996ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VAL | SETUP | 0.462ns| 0.038ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.832ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VAL | SETUP | 0.510ns| -0.010ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.819ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VAL | SETUP | 0.533ns| -0.033ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.759ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VAL | SETUP | 0.542ns| -0.042ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.759ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALI | SETUP | 0.823ns| -0.323ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.353ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | MINPERIOD | 1.071ns| 1.429ns| 0| 0 + clk_mem_pll = PERIOD TIMEGRP "fto | | | | | + p_dram0_memc_memc_u_infrastructure_clk_me | | | | | + m_pll" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP | 1.788ns| 6.212ns| 0| 0 + CLK" 125 MHz HIGH 50% | HOLD | 0.069ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GT | SETUP | 2.143ns| 5.857ns| 0| 0 + X_CLK" 125 MHz HIGH 50% | HOLD | 0.091ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 M | MINPERIOD | 2.462ns| 1.538ns| 0| 0 + Hz HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD | N/A | N/A| N/A| N/A| N/A + TIMEGRP "ftop_dram0_memc_memc_cl | | | | | + k_wr_i" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 4.988ns| 0| 0| 91995| 75766| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 4.988ns| N/A| 0| 0| 75766| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.307ns| 0| 158| 0| 12943666| +| TS_CLK_125 | 8.000ns| 8.287ns| N/A| 68| 0| 12924369| 0| +| TS_CLK_250 | 4.000ns| 4.307ns| N/A| 90| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +2 constraints not met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 534 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 5 mins 56 secs +Total CPU time to PAR completion: 6 mins 21 secs + +Peak Memory Usage: 2217 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 158 errors found. + +Number of error messages: 0 +Number of warning messages: 557 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/ml605-20140127_1142/fpgaTop.twr b/logs/ml605-20140127_1142/fpgaTop.twr new file mode 100644 index 00000000..f2609548 --- /dev/null +++ b/logs/ml605-20140127_1142/fpgaTop.twr @@ -0,0 +1,10752 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +/home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc6vlx240t,ff1156,C,-1 (PRODUCTION 1.17 2013-10-13, STEPPING level 0) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 91995 paths analyzed, 3686 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.761ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.266ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.591ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 4.591ns (1.334ns logic, 3.257ns route) + (29.1% logic, 70.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.266ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.591ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_lastSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_2 + ------------------------------------------------- --------------------------- + Total 4.591ns (1.334ns logic, 3.257ns route) + (29.1% logic, 70.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.266ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.591ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_lastSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_1 + ------------------------------------------------- --------------------------- + Total 4.591ns (1.334ns logic, 3.257ns route) + (29.1% logic, 70.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.266ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.591ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_lastSecond_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_0 + ------------------------------------------------- --------------------------- + Total 4.591ns (1.334ns logic, 3.257ns route) + (29.1% logic, 70.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.281ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_22 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.576ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_22 to ftop/ctop/inf/cp/timeServ_lastSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_22 + SLICE_X7Y21.D1 net (fanout=4) 0.720 ftop/ctop/inf/cp/timeServ_refFromRise<22> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_1 + ------------------------------------------------- --------------------------- + Total 4.576ns (1.334ns logic, 3.242ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.281ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_22 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.576ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_22 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_22 + SLICE_X7Y21.D1 net (fanout=4) 0.720 ftop/ctop/inf/cp/timeServ_refFromRise<22> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 4.576ns (1.334ns logic, 3.242ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.281ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_22 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.576ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_22 to ftop/ctop/inf/cp/timeServ_lastSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_22 + SLICE_X7Y21.D1 net (fanout=4) 0.720 ftop/ctop/inf/cp/timeServ_refFromRise<22> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_2 + ------------------------------------------------- --------------------------- + Total 4.576ns (1.334ns logic, 3.242ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.281ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_22 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.576ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.956 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_22 to ftop/ctop/inf/cp/timeServ_lastSecond_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_22 + SLICE_X7Y21.D1 net (fanout=4) 0.720 ftop/ctop/inf/cp/timeServ_refFromRise<22> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_0 + ------------------------------------------------- --------------------------- + Total 4.576ns (1.334ns logic, 3.242ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.556ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_lastSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X7Y21.A2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_1 + ------------------------------------------------- --------------------------- + Total 4.556ns (1.424ns logic, 3.132ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.556ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_lastSecond_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X7Y21.A2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_0 + ------------------------------------------------- --------------------------- + Total 4.556ns (1.424ns logic, 3.132ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.542ns (Levels of Logic = 3) + Clock Path Skew: -0.116ns (0.948 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_delSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X32Y4.CE net (fanout=34) 1.782 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X32Y4.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_delSecond_1 + ------------------------------------------------- --------------------------- + Total 4.542ns (1.300ns logic, 3.242ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.542ns (Levels of Logic = 3) + Clock Path Skew: -0.116ns (0.948 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_delSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X32Y4.CE net (fanout=34) 1.782 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X32Y4.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_delSecond_3 + ------------------------------------------------- --------------------------- + Total 4.542ns (1.300ns logic, 3.242ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.556ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X7Y21.A2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 4.556ns (1.424ns logic, 3.132ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.556ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_lastSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X7Y21.A2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_2 + ------------------------------------------------- --------------------------- + Total 4.556ns (1.424ns logic, 3.132ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.542ns (Levels of Logic = 3) + Clock Path Skew: -0.116ns (0.948 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_delSecond_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X32Y4.CE net (fanout=34) 1.782 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X32Y4.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_delSecond_0 + ------------------------------------------------- --------------------------- + Total 4.542ns (1.300ns logic, 3.242ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_21 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.542ns (Levels of Logic = 3) + Clock Path Skew: -0.116ns (0.948 - 1.064) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_21 to ftop/ctop/inf/cp/timeServ_delSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y23.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_21 + SLICE_X7Y21.D2 net (fanout=4) 0.735 ftop/ctop/inf/cp/timeServ_refFromRise<21> + SLICE_X7Y21.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X32Y4.CE net (fanout=34) 1.782 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X32Y4.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_delSecond_2 + ------------------------------------------------- --------------------------- + Total 4.542ns (1.300ns logic, 3.242ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.553ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_lastSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X7Y21.A1 net (fanout=4) 0.607 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_2 + ------------------------------------------------- --------------------------- + Total 4.553ns (1.424ns logic, 3.129ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.551ns (Levels of Logic = 3) + Clock Path Skew: -0.104ns (0.956 - 1.060) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y21.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X7Y21.B2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X7Y21.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 4.551ns (1.419ns logic, 3.132ns route) + (31.2% logic, 68.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.551ns (Levels of Logic = 3) + Clock Path Skew: -0.104ns (0.956 - 1.060) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_lastSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y21.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X7Y21.B2 net (fanout=4) 0.610 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X7Y21.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_2 + ------------------------------------------------- --------------------------- + Total 4.551ns (1.419ns logic, 3.132ns route) + (31.2% logic, 68.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.553ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (0.956 - 1.058) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y20.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X7Y21.A1 net (fanout=4) 0.607 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X7Y21.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X7Y22.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B6 net (fanout=4) 0.725 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X13Y20.B Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_delSecond_EN1 + SLICE_X29Y4.CE net (fanout=34) 1.797 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X29Y4.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_lastSecond<3> + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 4.553ns (1.424ns logic, 3.129ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.067ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_0 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.067ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_0 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X28Y26.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_0 + SLICE_X28Y26.AX net (fanout=4) 0.065 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<0> + SLICE_X28Y26.CLK Tckdi (-Th) 0.113 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.067ns (0.002ns logic, 0.065ns route) + (3.0% logic, 97.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_15 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.511 - 0.472) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_15 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y115.DQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<15> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_15 + SLICE_X97Y116.AX net (fanout=1) 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<15> + SLICE_X97Y116.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<19> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_16 + ------------------------------------------------- --------------------------- + Total 0.120ns (0.022ns logic, 0.098ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.090ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_22 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_38 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.455 - 0.421) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_22 to ftop/ctop/inf/cp/timeServ_jamFracVal_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X27Y20.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<23> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_22 + SLICE_X26Y19.CX net (fanout=1) 0.115 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<22> + SLICE_X26Y19.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_38 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.009ns logic, 0.115ns route) + (7.3% logic, 92.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_39 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.455 - 0.421) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_23 to ftop/ctop/inf/cp/timeServ_jamFracVal_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X27Y20.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<23> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_23 + SLICE_X26Y19.DX net (fanout=1) 0.116 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<23> + SLICE_X26Y19.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_39 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.009ns logic, 0.116ns route) + (7.2% logic, 92.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_20 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_36 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.455 - 0.421) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_20 to ftop/ctop/inf/cp/timeServ_jamFracVal_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X27Y20.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<23> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_20 + SLICE_X26Y19.AX net (fanout=1) 0.116 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<20> + SLICE_X26Y19.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_36 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.009ns logic, 0.116ns route) + (7.2% logic, 92.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_rst_stretch_n/reset_hold_3 (FF) + Destination: ftop/dram0/memc_rst_stretch_n/reset_hold_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_rst_stretch_n/reset_hold_3 to ftop/dram0/memc_rst_stretch_n/reset_hold_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y125.DQ Tcko 0.098 ftop/dram0/memc_rst_stretch_n/reset_hold<3> + ftop/dram0/memc_rst_stretch_n/reset_hold_3 + SLICE_X108Y125.AX net (fanout=1) 0.094 ftop/dram0/memc_rst_stretch_n/reset_hold<3> + SLICE_X108Y125.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_rst_stretch_n/reset_hold<7> + ftop/dram0/memc_rst_stretch_n/reset_hold_4 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y115.DQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 + SLICE_X100Y115.AX net (fanout=1) 0.094 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + SLICE_X100Y115.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<7> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X28Y26.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + SLICE_X28Y26.C5 net (fanout=2) 0.072 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + SLICE_X28Y26.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[2]_xor_20_OUT_1_xo<0>1 + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y22.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + SLICE_X0Y22.A5 net (fanout=3) 0.072 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + SLICE_X0Y22.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.066 - 0.053) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y35.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 + SLICE_X12Y36.AX net (fanout=2) 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<4> + SLICE_X12Y36.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/itc0/now/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/itc0/now/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/itc0/now/sync/sToggleReg to ftop/ctop/inf/itc0/now/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X40Y70.AQ Tcko 0.115 ftop/ctop/inf/itc0/now/sync/sToggleReg + ftop/ctop/inf/itc0/now/sync/sToggleReg + SLICE_X40Y70.A5 net (fanout=3) 0.072 ftop/ctop/inf/itc0/now/sync/sToggleReg + SLICE_X40Y70.CLK Tah (-Th) 0.076 ftop/ctop/inf/itc0/now/sync/sToggleReg + ftop/ctop/inf/itc0/now/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/itc0/now/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_xo2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_xo2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_xo2 to ftop/ctop/inf/cp/timeServ_xo2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y25.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/timeServ_xo2 + SLICE_X8Y25.A5 net (fanout=5) 0.072 ftop/ctop/inf/cp/timeServ_xo2 + SLICE_X8Y25.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/Mcount_timeServ_refFreeCount_lut<0>_INV_0 + ftop/ctop/inf/cp/timeServ_xo2 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.066 - 0.053) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y35.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 + SLICE_X12Y36.CX net (fanout=2) 0.100 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<6> + SLICE_X12Y36.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_28 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_29 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_28 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y119.BQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<29> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_28 + SLICE_X93Y119.DX net (fanout=1) 0.092 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<28> + SLICE_X93Y119.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<29> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_29 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.022ns logic, 0.092ns route) + (19.3% logic, 80.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y32.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + SLICE_X13Y32.A5 net (fanout=3) 0.071 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + SLICE_X13Y32.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.114ns (0.043ns logic, 0.071ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y35.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + SLICE_X5Y35.A5 net (fanout=3) 0.071 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + SLICE_X5Y35.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.114ns (0.043ns logic, 0.071ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_rst_stretch_n/reset_hold_7 (FF) + Destination: ftop/dram0/memc_rst_stretch_n/reset_hold_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_rst_stretch_n/reset_hold_7 to ftop/dram0/memc_rst_stretch_n/reset_hold_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y125.DQ Tcko 0.115 ftop/dram0/memc_rst_stretch_n/reset_hold<7> + ftop/dram0/memc_rst_stretch_n/reset_hold_7 + SLICE_X108Y125.A4 net (fanout=1) 0.101 ftop/dram0/memc_rst_stretch_n/reset_hold<7> + SLICE_X108Y125.CLK Tah (-Th) 0.101 ftop/dram0/memc_rst_stretch_n/reset_hold<7> + ftop/dram0/memc_rst_stretch_n/reset_hold<7>_rt + ftop/dram0/memc_rst_stretch_n/reset_hold_8 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.014ns logic, 0.101ns route) + (12.2% logic, 87.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsOK (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsOK (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsOK to ftop/ctop/inf/cp/timeServ_ppsOK + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y24.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_ppsOK + ftop/ctop/inf/cp/timeServ_ppsOK + SLICE_X7Y24.A5 net (fanout=7) 0.072 ftop/ctop/inf/cp/timeServ_ppsOK + SLICE_X7Y24.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_ppsOK + ftop/ctop/inf/cp/timeServ_ppsOK_D_IN1 + ftop/ctop/inf/cp/timeServ_ppsOK + ------------------------------------------------- --------------------------- + Total 0.115ns (0.043ns logic, 0.072ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y21.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X44Y21.C5 net (fanout=3) 0.077 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X44Y21.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y24.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + SLICE_X0Y24.A5 net (fanout=3) 0.077 ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + SLICE_X0Y24.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Location pin: IDELAYCTRL_X1Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Location pin: IDELAYCTRL_X1Y4.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Location pin: IDELAYCTRL_X2Y1.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Location pin: IDELAYCTRL_X2Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Location pin: MMCM_ADV_X0Y6.CLKOUT0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Location pin: MMCM_ADV_X0Y6.CLKOUT2 + Clock network: ftop/dram0/memc_memc/clk_wr_i +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.571ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys0_clk_O_BUFG/I0 + Logical resource: ftop/sys0_clk_O_BUFG/I0 + Location pin: BUFGCTRL_X0Y1.I0 + Clock network: ftop/sys0_clk_O +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKIN(Finmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKFBOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Location pin: MMCM_ADV_X0Y6.CLKFBOUT + Clock network: ftop/dram0/memc_memc/u_infrastructure/clkfbout_pll +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Location pin: MMCM_ADV_X0Y6.CLKOUT1 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_pll +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Location pin: SLICE_X0Y22.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg/SR + Location pin: SLICE_X0Y24.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg1/SR + Location pin: SLICE_X0Y25.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Location pin: SLICE_X0Y25.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dLastState/SR + Location pin: SLICE_X0Y30.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg1/SR + Location pin: SLICE_X0Y30.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Location pin: SLICE_X0Y30.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dLastState/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg1/SR + Location pin: SLICE_X0Y35.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.538ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% +PRIORITY 100; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 12924369 paths analyzed, 137231 endpoints analyzed, 68 failing endpoints + 68 timing errors detected. (68 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 8.287ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.287ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/full_reg (FF) + Requirement: 8.000ns + Data Path Delay: 8.134ns (Levels of Logic = 10) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/full_reg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X95Y69.B6 net (fanout=5) 0.521 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X95Y69.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/_n0063_inv + ftop/ctop/inf/cp/cpRespF/_n0063_inv1 + SLICE_X95Y70.CE net (fanout=1) 0.246 ftop/ctop/inf/cp/cpRespF/_n0063_inv + SLICE_X95Y70.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF_FULL_N + ftop/ctop/inf/cp/cpRespF/full_reg + ------------------------------------------------- --------------------------- + Total 8.134ns (1.503ns logic, 6.631ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.282ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_16 (FF) + Requirement: 8.000ns + Data Path Delay: 8.129ns (Levels of Logic = 11) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.B5 net (fanout=40) 0.638 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.070 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<16>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_16 + ------------------------------------------------- --------------------------- + Total 8.129ns (1.255ns logic, 6.874ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.279ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 8.126ns (Levels of Logic = 11) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.C5 net (fanout=40) 0.632 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.073 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<19>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_19 + ------------------------------------------------- --------------------------- + Total 8.126ns (1.258ns logic, 6.868ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.270ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/full_reg (FF) + Requirement: 8.000ns + Data Path Delay: 8.117ns (Levels of Logic = 9) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/full_reg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X95Y69.B6 net (fanout=5) 0.521 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X95Y69.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/_n0063_inv + ftop/ctop/inf/cp/cpRespF/_n0063_inv1 + SLICE_X95Y70.CE net (fanout=1) 0.246 ftop/ctop/inf/cp/cpRespF/_n0063_inv + SLICE_X95Y70.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF_FULL_N + ftop/ctop/inf/cp/cpRespF/full_reg + ------------------------------------------------- --------------------------- + Total 8.117ns (1.435ns logic, 6.682ns route) + (17.7% logic, 82.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.269ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_32 (FF) + Requirement: 8.000ns + Data Path Delay: 8.115ns (Levels of Logic = 11) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_32 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X92Y68.B5 net (fanout=40) 0.666 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X92Y68.CLK Tas 0.028 ftop/ctop/inf/cp_server_response_get<38> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<32>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_32 + ------------------------------------------------- --------------------------- + Total 8.115ns (1.213ns logic, 6.902ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.267ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_38 (FF) + Requirement: 8.000ns + Data Path Delay: 8.113ns (Levels of Logic = 11) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X92Y68.C5 net (fanout=40) 0.662 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X92Y68.CLK Tas 0.030 ftop/ctop/inf/cp_server_response_get<38> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<38>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 8.113ns (1.215ns logic, 6.898ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.265ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.111ns (Levels of Logic = 10) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data1_reg_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y70.B6 net (fanout=21) 1.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y70.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A6 net (fanout=1) 0.258 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<11> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X94Y69.CE net (fanout=13) 0.673 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X94Y69.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_18 + ------------------------------------------------- --------------------------- + Total 8.111ns (1.503ns logic, 6.608ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.265ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_17 (FF) + Requirement: 8.000ns + Data Path Delay: 8.111ns (Levels of Logic = 10) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data1_reg_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y70.B6 net (fanout=21) 1.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y70.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A6 net (fanout=1) 0.258 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<11> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X94Y69.CE net (fanout=13) 0.673 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X94Y69.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_17 + ------------------------------------------------- --------------------------- + Total 8.111ns (1.503ns logic, 6.608ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.265ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 8.111ns (Levels of Logic = 10) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data1_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y70.B6 net (fanout=21) 1.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y70.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A6 net (fanout=1) 0.258 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<11> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X94Y69.CE net (fanout=13) 0.673 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X94Y69.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_19 + ------------------------------------------------- --------------------------- + Total 8.111ns (1.503ns logic, 6.608ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.265ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_16 (FF) + Requirement: 8.000ns + Data Path Delay: 8.112ns (Levels of Logic = 10) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.B5 net (fanout=40) 0.638 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.070 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<16>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_16 + ------------------------------------------------- --------------------------- + Total 8.112ns (1.187ns logic, 6.925ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.264ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/full_reg (FF) + Requirement: 8.000ns + Data Path Delay: 8.111ns (Levels of Logic = 10) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpRespF/full_reg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X62Y77.D4 net (fanout=40) 0.448 ftop/ctop/inf/cp/cpReq<21> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X95Y69.B6 net (fanout=5) 0.521 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X95Y69.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/_n0063_inv + ftop/ctop/inf/cp/cpRespF/_n0063_inv1 + SLICE_X95Y70.CE net (fanout=1) 0.246 ftop/ctop/inf/cp/cpRespF/_n0063_inv + SLICE_X95Y70.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF_FULL_N + ftop/ctop/inf/cp/cpRespF/full_reg + ------------------------------------------------- --------------------------- + Total 8.111ns (1.503ns logic, 6.608ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.262ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 8.109ns (Levels of Logic = 10) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.C5 net (fanout=40) 0.632 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.073 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<19>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_19 + ------------------------------------------------- --------------------------- + Total 8.109ns (1.190ns logic, 6.919ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.259ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_16 (FF) + Requirement: 8.000ns + Data Path Delay: 8.106ns (Levels of Logic = 11) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpRespF/data0_reg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X62Y77.D4 net (fanout=40) 0.448 ftop/ctop/inf/cp/cpReq<21> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.B5 net (fanout=40) 0.638 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.070 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<16>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_16 + ------------------------------------------------- --------------------------- + Total 8.106ns (1.255ns logic, 6.851ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.256ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_21 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 8.103ns (Levels of Logic = 11) + Clock Path Skew: -0.084ns (1.534 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_21 to ftop/ctop/inf/cp/cpRespF/data0_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_21 + SLICE_X62Y77.D4 net (fanout=40) 0.448 ftop/ctop/inf/cp/cpReq<21> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X66Y76.A6 net (fanout=20) 0.660 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X66Y76.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B6 net (fanout=44) 0.802 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 + SLICE_X63Y81.B Tilo 0.068 flash_addr_2_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T1 + SLICE_X66Y76.C6 net (fanout=14) 0.667 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + SLICE_X66Y76.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C5 net (fanout=1) 0.438 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead4 + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X93Y69.C5 net (fanout=40) 0.632 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X93Y69.CLK Tas 0.073 ftop/ctop/inf/cp_server_response_get<35> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<19>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_19 + ------------------------------------------------- --------------------------- + Total 8.103ns (1.258ns logic, 6.845ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.252ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_32 (FF) + Requirement: 8.000ns + Data Path Delay: 8.098ns (Levels of Logic = 10) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_32 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X92Y68.B5 net (fanout=40) 0.666 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X92Y68.CLK Tas 0.028 ftop/ctop/inf/cp_server_response_get<38> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<32>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_32 + ------------------------------------------------- --------------------------- + Total 8.098ns (1.145ns logic, 6.953ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.250ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_1_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<37>_REPLICA_229 (FF) + Requirement: 8.000ns + Data Path Delay: 7.922ns (Levels of Logic = 9) + Clock Path Skew: -0.259ns (1.496 - 1.755) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_1_busy to ftop/ctop/inf/cp/cpReq<37>_REPLICA_229 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X68Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_1_busy + ftop/ctop/inf/cp/wci_1_busy + SLICE_X66Y79.D5 net (fanout=14) 0.331 ftop/ctop/inf/cp/wci_1_busy + SLICE_X66Y79.D Tilo 0.068 ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o + ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o1 + SLICE_X62Y76.D2 net (fanout=2) 1.019 ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o + SLICE_X62Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/cpReq<37>_REPLICA_228 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_2_f8 + SLICE_X66Y74.C6 net (fanout=51) 0.686 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 + SLICE_X66Y74.C Tilo 0.068 ftop/ctop/inf/cp/Mmux_IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d261933 + ftop/ctop/inf/cp/cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d30921 + SLICE_X69Y73.A6 net (fanout=14) 0.407 ftop/ctop/inf/cp/cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 + SLICE_X69Y73.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite13 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T1 + SLICE_X62Y79.C3 net (fanout=7) 0.926 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T + SLICE_X62Y79.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite1 + SLICE_X70Y75.A5 net (fanout=1) 0.812 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite1 + SLICE_X70Y75.A Tilo 0.068 ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320_51 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite7 + SLICE_X66Y75.B6 net (fanout=1) 0.375 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite7 + SLICE_X66Y75.B Tilo 0.068 ftop/ctop/inf/cp/N760 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite32_SW0 + SLICE_X66Y75.A6 net (fanout=1) 0.125 ftop/ctop/inf/cp/N672 + SLICE_X66Y75.A Tilo 0.068 ftop/ctop/inf/cp/N760 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite32 + SLICE_X68Y78.B5 net (fanout=19) 0.513 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X68Y78.B Tilo 0.068 ftop/ctop/inf/cp/N756 + ftop/ctop/inf/cp/cpReq_EN5 + SLICE_X53Y80.CE net (fanout=33) 1.077 ftop/ctop/inf/cp/cpReq_EN + SLICE_X53Y80.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<37>_REPLICA_229 + ftop/ctop/inf/cp/cpReq<37>_REPLICA_229 + ------------------------------------------------- --------------------------- + Total 7.922ns (1.651ns logic, 6.271ns route) + (20.8% logic, 79.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.250ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_1_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<36>_REPLICA_241 (FF) + Requirement: 8.000ns + Data Path Delay: 7.922ns (Levels of Logic = 9) + Clock Path Skew: -0.259ns (1.496 - 1.755) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_1_busy to ftop/ctop/inf/cp/cpReq<36>_REPLICA_241 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X68Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_1_busy + ftop/ctop/inf/cp/wci_1_busy + SLICE_X66Y79.D5 net (fanout=14) 0.331 ftop/ctop/inf/cp/wci_1_busy + SLICE_X66Y79.D Tilo 0.068 ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o + ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o1 + SLICE_X62Y76.D2 net (fanout=2) 1.019 ftop/ctop/inf/cp/wci_1_busy_wci_1_respF_FULL_N_AND_4269_o + SLICE_X62Y76.BMUX Topdb 0.408 ftop/ctop/inf/cp/cpReq<37>_REPLICA_228 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_6 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077_2_f8 + SLICE_X66Y74.C6 net (fanout=51) 0.686 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 + SLICE_X66Y74.C Tilo 0.068 ftop/ctop/inf/cp/Mmux_IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d261933 + ftop/ctop/inf/cp/cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d30921 + SLICE_X69Y73.A6 net (fanout=14) 0.407 ftop/ctop/inf/cp/cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 + SLICE_X69Y73.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite13 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T1 + SLICE_X62Y79.C3 net (fanout=7) 0.926 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T + SLICE_X62Y79.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite1 + SLICE_X70Y75.A5 net (fanout=1) 0.812 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite1 + SLICE_X70Y75.A Tilo 0.068 ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320_51 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite7 + SLICE_X66Y75.B6 net (fanout=1) 0.375 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite7 + SLICE_X66Y75.B Tilo 0.068 ftop/ctop/inf/cp/N760 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite32_SW0 + SLICE_X66Y75.A6 net (fanout=1) 0.125 ftop/ctop/inf/cp/N672 + SLICE_X66Y75.A Tilo 0.068 ftop/ctop/inf/cp/N760 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite32 + SLICE_X68Y78.B5 net (fanout=19) 0.513 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerWrite + SLICE_X68Y78.B Tilo 0.068 ftop/ctop/inf/cp/N756 + ftop/ctop/inf/cp/cpReq_EN5 + SLICE_X53Y80.CE net (fanout=33) 1.077 ftop/ctop/inf/cp/cpReq_EN + SLICE_X53Y80.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<37>_REPLICA_229 + ftop/ctop/inf/cp/cpReq<36>_REPLICA_241 + ------------------------------------------------- --------------------------- + Total 7.922ns (1.651ns logic, 6.271ns route) + (20.8% logic, 79.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.250ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data0_reg_38 (FF) + Requirement: 8.000ns + Data Path Delay: 8.096ns (Levels of Logic = 10) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X90Y69.C6 net (fanout=21) 1.297 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X90Y69.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X90Y69.A3 net (fanout=5) 0.372 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X90Y69.A Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d0di1 + SLICE_X92Y68.C5 net (fanout=40) 0.662 ftop/ctop/inf/cp/cpRespF/d0di + SLICE_X92Y68.CLK Tas 0.030 ftop/ctop/inf/cp_server_response_get<38> + ftop/ctop/inf/cp/cpRespF/d0di_d0h_or_8_OUT<38>1 + ftop/ctop/inf/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 8.096ns (1.147ns logic, 6.949ns route) + (14.2% logic, 85.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.248ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_18 (FF) + Requirement: 8.000ns + Data Path Delay: 8.094ns (Levels of Logic = 9) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data1_reg_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y70.B6 net (fanout=21) 1.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y70.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A6 net (fanout=1) 0.258 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<11> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X94Y69.CE net (fanout=13) 0.673 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X94Y69.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_18 + ------------------------------------------------- --------------------------- + Total 8.094ns (1.435ns logic, 6.659ns route) + (17.7% logic, 82.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.248ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_23 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 8.094ns (Levels of Logic = 9) + Clock Path Skew: -0.085ns (1.533 - 1.618) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_23 to ftop/ctop/inf/cp/cpRespF/data1_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y78.CQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<28> + ftop/ctop/inf/cp/cpReq_23 + SLICE_X62Y77.D3 net (fanout=22) 0.471 ftop/ctop/inf/cp/cpReq<23> + SLICE_X62Y77.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_wReset_n + ftop/ctop/inf/cp/Msub_wn__h78174_xor<3>11 + SLICE_X56Y78.D5 net (fanout=5) 0.470 ftop/ctop/inf/cp/wn__h78174<3> + SLICE_X56Y78.D Tilo 0.068 ftop/ctop/inf/cp/wci_8_busy + ftop/ctop/inf/cp/Mmux__theResult_____1__h7819041 + SLICE_X63Y77.BX net (fanout=48) 0.570 ftop/ctop/inf/cp/_theResult_____1__h78190<3> + SLICE_X63Y77.BMUX Tbxb 0.236 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884_2_f8 + SLICE_X64Y80.C6 net (fanout=20) 0.618 ftop/ctop/inf/cp/CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 + SLICE_X64Y80.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T + ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B6 net (fanout=53) 0.887 ftop/ctop/inf/cp/NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 + SLICE_X55Y83.B Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997_REPLICA_214 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T1 + SLICE_X65Y79.C3 net (fanout=23) 1.113 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T + SLICE_X65Y79.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead6 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A1 net (fanout=1) 0.489 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X64Y79.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_busy + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y70.B6 net (fanout=21) 1.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y70.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A6 net (fanout=1) 0.258 ftop/ctop/inf/cp/cpRespF_ENQ1_REPLICA_248 + SLICE_X88Y70.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<11> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X94Y69.CE net (fanout=13) 0.673 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X94Y69.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_19 + ------------------------------------------------- --------------------------- + Total 8.094ns (1.435ns logic, 6.659ns route) + (17.7% logic, 82.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack (hold path): 0.004ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_102 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_102_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.170 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_102 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_102_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y125.CQ Tcko 0.098 ftop/pciw_p2iS<103> + ftop/pciw_p2iS_102 + SLICE_X148Y125.CX net (fanout=1) 0.200 ftop/pciw_p2iS<102> + SLICE_X148Y125.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<103> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_102_0 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.068ns logic, 0.200ns route) + (25.4% logic, 74.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_86 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_86_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.171 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_86 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_86_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y121.CQ Tcko 0.098 ftop/pciw_p2iS<87> + ftop/pciw_p2iS_86 + SLICE_X148Y118.CX net (fanout=1) 0.202 ftop/pciw_p2iS<86> + SLICE_X148Y118.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<87> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_86_0 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.068ns logic, 0.202ns route) + (25.2% logic, 74.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_103 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_103_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.170 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_103 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_103_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y125.DQ Tcko 0.098 ftop/pciw_p2iS<103> + ftop/pciw_p2iS_103 + SLICE_X148Y125.DX net (fanout=1) 0.214 ftop/pciw_p2iS<103> + SLICE_X148Y125.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<103> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_103_0 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.060ns logic, 0.214ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_45 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_45_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.277ns (Levels of Logic = 0) + Clock Path Skew: 0.074ns (1.169 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_45 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_45_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X152Y127.BQ Tcko 0.115 ftop/pciw_p2iS<47> + ftop/pciw_p2iS_45 + SLICE_X148Y127.BX net (fanout=1) 0.189 ftop/pciw_p2iS<45> + SLICE_X148Y127.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<47> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_45_0 + ------------------------------------------------- --------------------------- + Total 0.277ns (0.088ns logic, 0.189ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_100 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_100_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.170 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_100 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_100_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y125.AQ Tcko 0.098 ftop/pciw_p2iS<103> + ftop/pciw_p2iS_100 + SLICE_X148Y125.AX net (fanout=1) 0.217 ftop/pciw_p2iS<100> + SLICE_X148Y125.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<103> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_100_0 + ------------------------------------------------- --------------------------- + Total 0.279ns (0.062ns logic, 0.217ns route) + (22.2% logic, 77.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_144 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_144_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.283ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (1.173 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_144 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_144_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y124.AQ Tcko 0.098 ftop/pciw_p2iS<147> + ftop/pciw_p2iS_144 + SLICE_X158Y117.AX net (fanout=1) 0.221 ftop/pciw_p2iS<144> + SLICE_X158Y117.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<147> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_144_0 + ------------------------------------------------- --------------------------- + Total 0.283ns (0.062ns logic, 0.221ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_147 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_147_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.283ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (1.173 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_147 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_147_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y124.DQ Tcko 0.098 ftop/pciw_p2iS<147> + ftop/pciw_p2iS_147 + SLICE_X158Y117.DX net (fanout=1) 0.223 ftop/pciw_p2iS<147> + SLICE_X158Y117.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<147> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_147_0 + ------------------------------------------------- --------------------------- + Total 0.283ns (0.060ns logic, 0.223ns route) + (21.2% logic, 78.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMC + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.771 - 0.663) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 to ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y156.DQ Tcko 0.098 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.D1 net (fanout=10) 0.305 ftop/ctop/inf/dp0/wmi_wmi_reqF/tail_0_0 + SLICE_X4Y161.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/wmi_wmi_reqF/_n0101<17> + ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.124ns (-0.181ns logic, 0.305ns route) + (-146.0% logic, 246.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.018ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_146 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_146_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.285ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (1.173 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_146 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_146_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y124.CQ Tcko 0.098 ftop/pciw_p2iS<147> + ftop/pciw_p2iS_146 + SLICE_X158Y117.CX net (fanout=1) 0.217 ftop/pciw_p2iS<146> + SLICE_X158Y117.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<147> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_146_0 + ------------------------------------------------- --------------------------- + Total 0.285ns (0.068ns logic, 0.217ns route) + (23.9% logic, 76.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/app/appW1/wmemi_dhF_q_1_65 (FF) + Destination: ftop/ctop/app/appW1/wmemi_dhF_q_0_65 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.768 - 0.661) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/app/appW1/wmemi_dhF_q_1_65 to ftop/ctop/app/appW1/wmemi_dhF_q_0_65 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X142Y159.DQ Tcko 0.115 ftop/ctop/app/appW1/wmemi_dhF_q_1<65> + ftop/ctop/app/appW1/wmemi_dhF_q_1_65 + SLICE_X142Y160.C6 net (fanout=1) 0.088 ftop/ctop/app/appW1/wmemi_dhF_q_1<65> + SLICE_X142Y160.CLK Tah (-Th) 0.076 ftop/ctop_wmemiM0_MData<50> + ftop/ctop/app/appW1/wmemi_dhF_q_0_D_IN<65>1 + ftop/ctop/app/appW1/wmemi_dhF_q_0_65 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.039ns logic, 0.088ns route) + (30.7% logic, 69.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.032ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/wci_10_reqF_q_0_9 (FF) + Destination: ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.139ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.784 - 0.677) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/wci_10_reqF_q_0_9 to ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y40.BQ Tcko 0.098 ftop/ctop_wci_m_2_MData<11> + ftop/ctop/inf/cp/wci_10_reqF_q_0_9 + SLICE_X60Y39.BX net (fanout=2) 0.092 ftop/ctop_wci_m_2_MData<9> + SLICE_X60Y39.CLK Tdh (-Th) 0.051 ftop/gbe0/wci_wslv_reqF/_n0101<11> + ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.139ns (0.047ns logic, 0.092ns route) + (33.8% logic, 66.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.038ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_99 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_99_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.298ns (Levels of Logic = 0) + Clock Path Skew: 0.071ns (1.166 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_99 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_99_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y124.DQ Tcko 0.098 ftop/pciw_p2iS<99> + ftop/pciw_p2iS_99 + SLICE_X146Y124.DX net (fanout=1) 0.238 ftop/pciw_p2iS<99> + SLICE_X146Y124.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<99> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_99_0 + ------------------------------------------------- --------------------------- + Total 0.298ns (0.060ns logic, 0.238ns route) + (20.1% logic, 79.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.039ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_26 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_26_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.296ns (Levels of Logic = 0) + Clock Path Skew: 0.068ns (1.157 - 1.089) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_26 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_26_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y134.CQ Tcko 0.098 ftop/pciw_p2iS<27> + ftop/pciw_p2iS_26 + SLICE_X158Y140.CX net (fanout=1) 0.228 ftop/pciw_p2iS<26> + SLICE_X158Y140.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<27> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_56_o_dat[15][152]_wide_mux_5_OUT_26_0 + ------------------------------------------------- --------------------------- + Total 0.296ns (0.068ns logic, 0.228ns route) + (23.0% logic, 77.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.042ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.077ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.447 - 0.412) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y19.BQ Tcko 0.098 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + SLICE_X128Y20.D2 net (fanout=10) 0.258 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + SLICE_X128Y20.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/_n0101<30> + ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/DP + ------------------------------------------------- --------------------------- + Total 0.077ns (-0.181ns logic, 0.258ns route) + (-235.1% logic, 335.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.042ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.077ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.447 - 0.412) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y19.BQ Tcko 0.098 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + SLICE_X128Y20.D2 net (fanout=10) 0.258 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/tail_0_0 + SLICE_X128Y20.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/_n0101<30> + ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr62/SP + ------------------------------------------------- --------------------------- + Total 0.077ns (-0.181ns logic, 0.258ns route) + (-235.1% logic, 335.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Location pin: GTXE1_X0Y15.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Location pin: GTXE1_X0Y14.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Location pin: GTXE1_X0Y13.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Location pin: GTXE1_X0Y12.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% +PRIORITY 1; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 19297 paths analyzed, 6214 endpoints analyzed, 90 failing endpoints + 90 timing errors detected. (90 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.307ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.307ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.078ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (0.924 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y140.CE net (fanout=13) 0.650 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA + ------------------------------------------------- --------------------------- + Total 4.078ns (1.108ns logic, 2.970ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMC + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.009ns (Levels of Logic = 2) + Clock Path Skew: -0.171ns (0.919 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X128Y140.CE net (fanout=13) 0.581 ftop/pciw_fI2P/BUS_0003 + SLICE_X128Y140.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMD + ------------------------------------------------- --------------------------- + Total 4.009ns (1.108ns logic, 2.901ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.238ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr3_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.012ns (Levels of Logic = 2) + Clock Path Skew: -0.163ns (0.927 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr3_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y142.CE net (fanout=13) 0.584 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y142.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<17> + ftop/pciw_fI2P/Mram_arr3_RAMA + ------------------------------------------------- --------------------------- + Total 4.012ns (1.108ns logic, 2.904ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.238ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr3_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.012ns (Levels of Logic = 2) + Clock Path Skew: -0.163ns (0.927 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr3_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y142.CE net (fanout=13) 0.584 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y142.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<17> + ftop/pciw_fI2P/Mram_arr3_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.012ns (1.108ns logic, 2.904ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.238ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr3_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.012ns (Levels of Logic = 2) + Clock Path Skew: -0.163ns (0.927 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr3_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y142.CE net (fanout=13) 0.584 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y142.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<17> + ftop/pciw_fI2P/Mram_arr3_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.012ns (1.108ns logic, 2.904ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.238ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr3_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.012ns (Levels of Logic = 2) + Clock Path Skew: -0.163ns (0.927 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr3_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X139Y135.C6 net (fanout=69) 1.548 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X139Y135.C Tilo 0.068 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/waitcounter2<7> + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X133Y141.D6 net (fanout=95) 0.772 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X133Y141.D Tilo 0.068 ftop/pciw_fI2P/BUS_0003 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X126Y142.CE net (fanout=13) 0.584 ftop/pciw_fI2P/BUS_0003 + SLICE_X126Y142.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<17> + ftop/pciw_fI2P/Mram_arr3_RAMB + ------------------------------------------------- --------------------------- + Total 4.012ns (1.108ns logic, 2.904ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_36 (FF) + Requirement: 0.000ns + Data Path Delay: 0.262ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (1.140 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X126Y132.A4 net (fanout=75) 0.240 ftop/pciw_i2pS<135> + SLICE_X126Y132.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<39> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN301 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_36 + ------------------------------------------------- --------------------------- + Total 0.262ns (0.022ns logic, 0.240ns route) + (8.4% logic, 91.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.264ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (1.140 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X122Y134.B2 net (fanout=75) 0.243 ftop/pciw_i2pS<135> + SLICE_X122Y134.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<3> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN121 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_1 + ------------------------------------------------- --------------------------- + Total 0.264ns (0.021ns logic, 0.243ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.003ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_53 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.143 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_53 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X122Y132.B2 net (fanout=75) 0.247 ftop/pciw_i2pS<135> + SLICE_X122Y132.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN491 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_53 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.021ns logic, 0.247ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.003ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_18 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 1) + Clock Path Skew: 0.077ns (1.144 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X122Y131.C2 net (fanout=75) 0.247 ftop/pciw_i2pS<135> + SLICE_X122Y131.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN101 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_18 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.022ns logic, 0.247ns route) + (8.2% logic, 91.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.004ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.143 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X120Y133.A2 net (fanout=76) 0.247 ftop/pciw_i2pS<134> + SLICE_X120Y133.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<11> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN801 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.022ns logic, 0.247ns route) + (8.2% logic, 91.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.004ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_59 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 (FF) + Requirement: 0.000ns + Data Path Delay: 0.263ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (1.136 - 1.066) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_59 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y125.DQ Tcko 0.098 ftop/pciw_i2pS<59> + ftop/pciw_i2pS_59 + SLICE_X128Y133.D6 net (fanout=1) 0.242 ftop/pciw_i2pS<59> + SLICE_X128Y133.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN551 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_59 + ------------------------------------------------- --------------------------- + Total 0.263ns (0.021ns logic, 0.242ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.004ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_61 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 (FF) + Requirement: 0.000ns + Data Path Delay: 0.261ns (Levels of Logic = 1) + Clock Path Skew: 0.068ns (1.138 - 1.070) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_61 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y132.BQ Tcko 0.098 ftop/pciw_i2pS<63> + ftop/pciw_i2pS_61 + SLICE_X123Y136.B3 net (fanout=1) 0.220 ftop/pciw_i2pS<61> + SLICE_X123Y136.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN581 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_61 + ------------------------------------------------- --------------------------- + Total 0.261ns (0.041ns logic, 0.220ns route) + (15.7% logic, 84.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 1) + Clock Path Skew: 0.077ns (1.144 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X122Y131.B2 net (fanout=75) 0.250 ftop/pciw_i2pS<135> + SLICE_X122Y131.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN91 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.021ns logic, 0.250ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_14 (FF) + Requirement: 0.000ns + Data Path Delay: 0.262ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (1.134 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X124Y137.C6 net (fanout=75) 0.240 ftop/pciw_i2pS<135> + SLICE_X124Y137.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<15> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN610 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_14 + ------------------------------------------------- --------------------------- + Total 0.262ns (0.022ns logic, 0.240ns route) + (8.4% logic, 91.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_35 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 (FF) + Requirement: 0.000ns + Data Path Delay: 0.252ns (Levels of Logic = 1) + Clock Path Skew: 0.057ns (1.142 - 1.085) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_35 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X113Y133.DQ Tcko 0.098 ftop/pciw_i2pS<35> + ftop/pciw_i2pS_35 + SLICE_X121Y134.D6 net (fanout=1) 0.211 ftop/pciw_i2pS<35> + SLICE_X121Y134.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<35> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN291 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 + ------------------------------------------------- --------------------------- + Total 0.252ns (0.041ns logic, 0.211ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.008ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_47 (FF) + Requirement: 0.000ns + Data Path Delay: 0.273ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.143 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_47 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X123Y132.D1 net (fanout=76) 0.232 ftop/pciw_i2pS<134> + SLICE_X123Y132.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<47> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN421 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_47 + ------------------------------------------------- --------------------------- + Total 0.273ns (0.041ns logic, 0.232ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.009ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.272ns (Levels of Logic = 1) + Clock Path Skew: 0.074ns (1.141 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X124Y132.B2 net (fanout=75) 0.251 ftop/pciw_i2pS<135> + SLICE_X124Y132.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN561 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + ------------------------------------------------- --------------------------- + Total 0.272ns (0.021ns logic, 0.251ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.012ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.275ns (Levels of Logic = 1) + Clock Path Skew: 0.074ns (1.141 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X124Y132.B3 net (fanout=76) 0.254 ftop/pciw_i2pS<134> + SLICE_X124Y132.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN561 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + ------------------------------------------------- --------------------------- + Total 0.275ns (0.021ns logic, 0.254ns route) + (7.6% logic, 92.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 1) + Clock Path Skew: 0.071ns (1.138 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X120Y137.D6 net (fanout=75) 0.253 ftop/pciw_i2pS<135> + SLICE_X120Y137.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<23> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN161 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_23 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.021ns logic, 0.253ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_20 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 1) + Clock Path Skew: 0.071ns (1.138 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X120Y137.A6 net (fanout=75) 0.252 ftop/pciw_i2pS<135> + SLICE_X120Y137.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<23> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN131 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_20 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.022ns logic, 0.252ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.095ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (0.533 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<15> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 + SLICE_X150Y123.B2 net (fanout=5) 0.171 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<15> + SLICE_X150Y123.B Tilo 0.034 ftop/ctop/inf/cpTlp/inF/data1_reg<71> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>61 + PCIE_X0Y1.PIPERX3DATA15 net (fanout=1) 0.239 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<15> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.447 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ---------------------------------------------------- --------------------------- + Total 0.095ns (-0.315ns logic, 0.410ns route) + (-331.6% logic, 431.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 (FF) + Requirement: 0.000ns + Data Path Delay: 0.275ns (Levels of Logic = 1) + Clock Path Skew: 0.071ns (1.138 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.DQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X123Y136.D4 net (fanout=75) 0.234 ftop/pciw_i2pS<135> + SLICE_X123Y136.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<63> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN601 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_63 + ------------------------------------------------- --------------------------- + Total 0.275ns (0.041ns logic, 0.234ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 1) + Clock Path Skew: 0.074ns (1.141 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X124Y132.C3 net (fanout=76) 0.256 ftop/pciw_i2pS<134> + SLICE_X124Y132.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN671 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_6 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.022ns logic, 0.256ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/reg_state_rxvld_ei_FSM_FFd2 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 1) + Clock Path Skew: 0.091ns (0.533 - 0.442) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/reg_state_rxvld_ei_FSM_FFd2 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------------ ------------------- + SLICE_X144Y133.AQ Tcko 0.115 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/reg_state_rxvld_ei_FSM_FFd2 + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/reg_state_rxvld_ei_FSM_FFd2 + SLICE_X147Y132.D5 net (fanout=10) 0.143 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/reg_state_rxvld_ei_FSM_FFd2 + SLICE_X147Y132.D Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2CHARISK<1> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/USER_RXCHARISK<1>1 + PCIE_X0Y1.PIPERX2CHARISK1 net (fanout=1) 0.308 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2CHARISK<1> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.494 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ------------------------------------------------------ --------------------------- + Total 0.106ns (-0.345ns logic, 0.451ns route) + (-325.5% logic, 425.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_30 (FF) + Requirement: 0.000ns + Data Path Delay: 0.280ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.143 - 1.067) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y133.CQ Tcko 0.098 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X121Y133.C2 net (fanout=76) 0.238 ftop/pciw_i2pS<134> + SLICE_X121Y133.CLK Tah (-Th) 0.056 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<31> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN241 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_30 + ------------------------------------------------- --------------------------- + Total 0.280ns (0.042ns logic, 0.238ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tpciper_PIPECLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Location pin: PCIE_X0Y1.PIPECLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X7Y28.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Location pin: RAMB36_X7Y28.CLKBWRCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X6Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2442 paths analyzed, 535 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 6.212ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.788ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_28 (FF) + Requirement: 8.000ns + Data Path Delay: 6.168ns (Levels of Logic = 4) + Clock Path Skew: -0.009ns (0.771 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_28 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y12.CE net (fanout=9) 1.239 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<30> + ftop/gbe0/gmac/rxRS_crc/rRemainder_28 + ------------------------------------------------- --------------------------- + Total 6.168ns (0.937ns logic, 5.231ns route) + (15.2% logic, 84.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.788ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_30 (FF) + Requirement: 8.000ns + Data Path Delay: 6.168ns (Levels of Logic = 4) + Clock Path Skew: -0.009ns (0.771 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y12.CE net (fanout=9) 1.239 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<30> + ftop/gbe0/gmac/rxRS_crc/rRemainder_30 + ------------------------------------------------- --------------------------- + Total 6.168ns (0.937ns logic, 5.231ns route) + (15.2% logic, 84.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.788ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_29 (FF) + Requirement: 8.000ns + Data Path Delay: 6.168ns (Levels of Logic = 4) + Clock Path Skew: -0.009ns (0.771 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y12.CE net (fanout=9) 1.239 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<30> + ftop/gbe0/gmac/rxRS_crc/rRemainder_29 + ------------------------------------------------- --------------------------- + Total 6.168ns (0.937ns logic, 5.231ns route) + (15.2% logic, 84.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.866ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_31 (FF) + Requirement: 8.000ns + Data Path Delay: 6.080ns (Levels of Logic = 4) + Clock Path Skew: -0.019ns (0.761 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X119Y12.CE net (fanout=9) 1.117 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X119Y12.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/rxRS_crc/rRemainder_31 + ------------------------------------------------- --------------------------- + Total 6.080ns (0.971ns logic, 5.109ns route) + (16.0% logic, 84.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.900ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_16 (FF) + Requirement: 8.000ns + Data Path Delay: 6.046ns (Levels of Logic = 4) + Clock Path Skew: -0.019ns (0.761 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X118Y12.CE net (fanout=9) 1.117 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X118Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_16 + ------------------------------------------------- --------------------------- + Total 6.046ns (0.937ns logic, 5.109ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.900ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_19 (FF) + Requirement: 8.000ns + Data Path Delay: 6.046ns (Levels of Logic = 4) + Clock Path Skew: -0.019ns (0.761 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X118Y12.CE net (fanout=9) 1.117 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X118Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 6.046ns (0.937ns logic, 5.109ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.900ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_17 (FF) + Requirement: 8.000ns + Data Path Delay: 6.046ns (Levels of Logic = 4) + Clock Path Skew: -0.019ns (0.761 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X118Y12.CE net (fanout=9) 1.117 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X118Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_17 + ------------------------------------------------- --------------------------- + Total 6.046ns (0.937ns logic, 5.109ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.900ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_18 (FF) + Requirement: 8.000ns + Data Path Delay: 6.046ns (Levels of Logic = 4) + Clock Path Skew: -0.019ns (0.761 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X118Y12.CE net (fanout=9) 1.117 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X118Y12.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_18 + ------------------------------------------------- --------------------------- + Total 6.046ns (0.937ns logic, 5.109ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.901ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 6.048ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X121Y12.CE net (fanout=9) 1.085 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X121Y12.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 6.048ns (0.971ns logic, 5.077ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.901ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_15 (FF) + Requirement: 8.000ns + Data Path Delay: 6.048ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X121Y12.CE net (fanout=9) 1.085 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X121Y12.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_15 + ------------------------------------------------- --------------------------- + Total 6.048ns (0.971ns logic, 5.077ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.901ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 6.048ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X121Y12.CE net (fanout=9) 1.085 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X121Y12.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 6.048ns (0.971ns logic, 5.077ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.901ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_14 (FF) + Requirement: 8.000ns + Data Path Delay: 6.048ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X121Y12.CE net (fanout=9) 1.085 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X121Y12.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_14 + ------------------------------------------------- --------------------------- + Total 6.048ns (0.971ns logic, 5.077ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.908ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 6.049ns (Levels of Logic = 4) + Clock Path Skew: -0.008ns (0.772 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y11.CE net (fanout=9) 1.120 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y11.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 6.049ns (0.937ns logic, 5.112ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.908ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_6 (FF) + Requirement: 8.000ns + Data Path Delay: 6.049ns (Levels of Logic = 4) + Clock Path Skew: -0.008ns (0.772 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y11.CE net (fanout=9) 1.120 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y11.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + ------------------------------------------------- --------------------------- + Total 6.049ns (0.937ns logic, 5.112ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.908ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.049ns (Levels of Logic = 4) + Clock Path Skew: -0.008ns (0.772 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y11.CE net (fanout=9) 1.120 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y11.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + ------------------------------------------------- --------------------------- + Total 6.049ns (0.937ns logic, 5.112ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.908ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.049ns (Levels of Logic = 4) + Clock Path Skew: -0.008ns (0.772 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X124Y11.CE net (fanout=9) 1.120 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X124Y11.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 6.049ns (0.937ns logic, 5.112ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.912ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_20 (FF) + Requirement: 8.000ns + Data Path Delay: 6.037ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X120Y13.CE net (fanout=9) 1.108 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X120Y13.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<23> + ftop/gbe0/gmac/rxRS_crc/rRemainder_20 + ------------------------------------------------- --------------------------- + Total 6.037ns (0.937ns logic, 5.100ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.912ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_23 (FF) + Requirement: 8.000ns + Data Path Delay: 6.037ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X120Y13.CE net (fanout=9) 1.108 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X120Y13.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<23> + ftop/gbe0/gmac/rxRS_crc/rRemainder_23 + ------------------------------------------------- --------------------------- + Total 6.037ns (0.937ns logic, 5.100ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.912ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_21 (FF) + Requirement: 8.000ns + Data Path Delay: 6.037ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X120Y13.CE net (fanout=9) 1.108 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X120Y13.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<23> + ftop/gbe0/gmac/rxRS_crc/rRemainder_21 + ------------------------------------------------- --------------------------- + Total 6.037ns (0.937ns logic, 5.100ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.912ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_22 (FF) + Requirement: 8.000ns + Data Path Delay: 6.037ns (Levels of Logic = 4) + Clock Path Skew: -0.016ns (0.764 - 0.780) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y6.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X101Y3.D4 net (fanout=18) 0.833 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X101Y3.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X101Y3.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/N2 + SLICE_X101Y3.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C4 net (fanout=13) 1.357 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X119Y12.C Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X103Y7.C2 net (fanout=33) 1.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X103Y7.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X120Y13.CE net (fanout=9) 1.108 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X120Y13.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<23> + ftop/gbe0/gmac/rxRS_crc/rRemainder_22 + ------------------------------------------------- --------------------------- + Total 6.037ns (0.937ns logic, 5.100ns route) + (15.5% logic, 84.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.082ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.063 - 0.050) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y11.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 + SLICE_X88Y9.BX net (fanout=1) 0.097 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<1> + SLICE_X88Y9.CLK Tckdi (-Th) 0.113 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.082ns (-0.015ns logic, 0.097ns route) + (-18.3% logic, 118.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.087ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.098ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + SLICE_X86Y9.DX net (fanout=3) 0.102 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + SLICE_X86Y9.CLK Tckdi (-Th) 0.102 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.098ns (-0.004ns logic, 0.102ns route) + (-4.1% logic, 104.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.090ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.101ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y9.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_1 + SLICE_X87Y9.A6 net (fanout=6) 0.058 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<1> + SLICE_X87Y9.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_3_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.101ns (0.043ns logic, 0.058ns route) + (42.6% logic, 57.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.063 - 0.050) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_0 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y11.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_0 + SLICE_X88Y9.AX net (fanout=1) 0.097 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<0> + SLICE_X88Y9.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.106ns (0.009ns logic, 0.097ns route) + (8.5% logic, 91.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.063 - 0.050) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y11.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 + SLICE_X88Y9.DX net (fanout=1) 0.097 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + SLICE_X88Y9.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.106ns (0.009ns logic, 0.097ns route) + (8.5% logic, 91.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.063 - 0.050) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_2 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y11.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_2 + SLICE_X88Y9.CX net (fanout=1) 0.097 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<2> + SLICE_X88Y9.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_2 + ------------------------------------------------- --------------------------- + Total 0.106ns (0.009ns logic, 0.097ns route) + (8.5% logic, 91.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_19 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_27 (FF) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.007ns (0.053 - 0.046) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_19 to ftop/gbe0/gmac/rxRS_rxPipe_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X119Y16.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<19> + ftop/gbe0/gmac/rxRS_rxPipe_19 + SLICE_X119Y17.DX net (fanout=2) 0.098 ftop/gbe0/gmac/rxRS_rxPipe<19> + SLICE_X119Y17.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<27> + ftop/gbe0/gmac/rxRS_rxPipe_27 + ------------------------------------------------- --------------------------- + Total 0.120ns (0.022ns logic, 0.098ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_14 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_14 to ftop/gbe0/gmac/rxRS_rxPipe_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y15.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxPipe<12> + ftop/gbe0/gmac/rxRS_rxPipe_14 + SLICE_X118Y14.CX net (fanout=2) 0.098 ftop/gbe0/gmac/rxRS_rxPipe<14> + SLICE_X118Y14.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/rxRS_rxPipe_22 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + SLICE_X87Y9.A5 net (fanout=3) 0.071 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + SLICE_X87Y9.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_3_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.043ns logic, 0.071ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.060 - 0.052) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y9.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X88Y12.D1 net (fanout=3) 0.308 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X88Y12.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.127ns (-0.181ns logic, 0.308ns route) + (-142.5% logic, 242.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y5.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + SLICE_X98Y5.C5 net (fanout=3) 0.082 ftop/gbe0/gmac/rxRS_preambleCnt_value<2> + SLICE_X98Y5.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_rxRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.042ns logic, 0.082ns route) + (33.9% logic, 66.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.125ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/rxRS_rxAPipe_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.138ns (Levels of Logic = 1) + Clock Path Skew: 0.013ns (0.066 - 0.053) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_crcEnd to ftop/gbe0/gmac/rxRS_rxAPipe_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y4.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_crcEnd + ftop/gbe0/gmac/rxRS_crcEnd + SLICE_X100Y3.A6 net (fanout=11) 0.116 ftop/gbe0/gmac/rxRS_crcEnd + SLICE_X100Y3.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxAPipe<5> + ftop/gbe0/gmac/Mmux_rxRS_rxAPipe_D_IN41 + ftop/gbe0/gmac/rxRS_rxAPipe_3 + ------------------------------------------------- --------------------------- + Total 0.138ns (0.022ns logic, 0.116ns route) + (15.9% logic, 84.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.128ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_8 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_8 to ftop/gbe0/gmac/rxRS_rxPipe_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y16.DQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxPipe<8> + ftop/gbe0/gmac/rxRS_rxPipe_8 + SLICE_X119Y16.AX net (fanout=2) 0.098 ftop/gbe0/gmac/rxRS_rxPipe<8> + SLICE_X119Y16.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxPipe<19> + ftop/gbe0/gmac/rxRS_rxPipe_16 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.039ns logic, 0.098ns route) + (28.5% logic, 71.5% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 4.668ns (period - min period limit) + Period: 8.000ns + Min period limit: 3.332ns (300.120MHz) (Tbrper_I) + Physical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Logical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Location pin: BUFR_X2Y3.I + Clock network: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X88Y12.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X88Y13.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X88Y13.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X88Y13.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 6107 paths analyzed, 683 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.857ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.143ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 5.557ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y83.CE net (fanout=14) 1.092 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 5.557ns (0.757ns logic, 4.800ns route) + (13.6% logic, 86.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.143ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.557ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y83.CE net (fanout=14) 1.092 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 5.557ns (0.757ns logic, 4.800ns route) + (13.6% logic, 86.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.143ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_0 (FF) + Requirement: 8.000ns + Data Path Delay: 5.557ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y83.CE net (fanout=14) 1.092 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder_0 + ------------------------------------------------- --------------------------- + Total 5.557ns (0.757ns logic, 4.800ns route) + (13.6% logic, 86.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.175ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_14 (FF) + Requirement: 8.000ns + Data Path Delay: 5.507ns (Levels of Logic = 5) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X125Y73.B4 net (fanout=38) 2.325 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X125Y73.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X126Y74.A5 net (fanout=13) 0.359 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X126Y74.A Tilo 0.068 ftop/gbe0/dcp_cpRespF/data1_reg<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y83.B1 net (fanout=8) 1.155 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y83.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data41 + SLICE_X131Y81.D4 net (fanout=14) 0.523 ftop/gbe0/gmac/txRS_crc_add_data<3> + SLICE_X131Y81.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>2 + SLICE_X131Y81.C2 net (fanout=1) 0.463 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>2 + SLICE_X131Y81.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_14 + ------------------------------------------------- --------------------------- + Total 5.507ns (0.682ns logic, 4.825ns route) + (12.4% logic, 87.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.183ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 5.499ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y85.CE net (fanout=14) 1.034 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y85.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 5.499ns (0.757ns logic, 4.742ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.183ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 5.499ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y85.CE net (fanout=14) 1.034 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y85.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 5.499ns (0.757ns logic, 4.742ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.183ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 5.499ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y85.CE net (fanout=14) 1.034 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y85.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 5.499ns (0.757ns logic, 4.742ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.211ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.489ns (Levels of Logic = 5) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X125Y73.B4 net (fanout=38) 2.325 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X125Y73.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X126Y74.A5 net (fanout=13) 0.359 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X126Y74.A Tilo 0.068 ftop/gbe0/dcp_cpRespF/data1_reg<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y81.A5 net (fanout=8) 0.737 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y81.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data81 + SLICE_X134Y83.B2 net (fanout=13) 1.179 ftop/gbe0/gmac/txRS_crc_add_data<7> + SLICE_X134Y83.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X134Y83.C6 net (fanout=2) 0.250 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X134Y83.CLK Tas 0.030 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 5.489ns (0.639ns logic, 4.850ns route) + (11.6% logic, 88.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.230ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Requirement: 8.000ns + Data Path Delay: 5.452ns (Levels of Logic = 5) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X125Y73.B4 net (fanout=38) 2.325 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X125Y73.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X126Y74.A5 net (fanout=13) 0.359 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X126Y74.A Tilo 0.068 ftop/gbe0/dcp_cpRespF/data1_reg<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y83.B1 net (fanout=8) 1.155 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X130Y83.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data41 + SLICE_X130Y80.B2 net (fanout=14) 0.850 ftop/gbe0/gmac/txRS_crc_add_data<3> + SLICE_X130Y80.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>1 + SLICE_X130Y80.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>1 + SLICE_X130Y80.CLK Tas 0.030 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_5 + ------------------------------------------------- --------------------------- + Total 5.452ns (0.639ns logic, 4.813ns route) + (11.7% logic, 88.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.271ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_25 (FF) + Requirement: 8.000ns + Data Path Delay: 5.429ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y82.CE net (fanout=14) 0.964 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y82.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_25 + ------------------------------------------------- --------------------------- + Total 5.429ns (0.757ns logic, 4.672ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.271ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_24 (FF) + Requirement: 8.000ns + Data Path Delay: 5.429ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y82.CE net (fanout=14) 0.964 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y82.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_24 + ------------------------------------------------- --------------------------- + Total 5.429ns (0.757ns logic, 4.672ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.271ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 5.429ns (Levels of Logic = 2) + Clock Path Skew: -0.265ns (1.469 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X134Y82.CE net (fanout=14) 0.964 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X134Y82.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 5.429ns (0.757ns logic, 4.672ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.289ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_9 (FF) + Requirement: 8.000ns + Data Path Delay: 5.407ns (Levels of Logic = 2) + Clock Path Skew: -0.269ns (1.465 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X132Y83.CE net (fanout=14) 0.942 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X132Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder_9 + ------------------------------------------------- --------------------------- + Total 5.407ns (0.757ns logic, 4.650ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.289ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 5.407ns (Levels of Logic = 2) + Clock Path Skew: -0.269ns (1.465 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X132Y83.CE net (fanout=14) 0.942 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X132Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 5.407ns (0.757ns logic, 4.650ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.289ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_8 (FF) + Requirement: 8.000ns + Data Path Delay: 5.407ns (Levels of Logic = 2) + Clock Path Skew: -0.269ns (1.465 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X132Y83.CE net (fanout=14) 0.942 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X132Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder_8 + ------------------------------------------------- --------------------------- + Total 5.407ns (0.757ns logic, 4.650ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.295ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_27 (FF) + Requirement: 8.000ns + Data Path Delay: 5.387ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y84.CE net (fanout=14) 0.922 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y84.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<28> + ftop/gbe0/gmac/txRS_crc/rRemainder_27 + ------------------------------------------------- --------------------------- + Total 5.387ns (0.757ns logic, 4.630ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.295ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_28 (FF) + Requirement: 8.000ns + Data Path Delay: 5.387ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_28 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y84.CE net (fanout=14) 0.922 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y84.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<28> + ftop/gbe0/gmac/txRS_crc/rRemainder_28 + ------------------------------------------------- --------------------------- + Total 5.387ns (0.757ns logic, 4.630ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.309ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.373ns (Levels of Logic = 5) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X125Y73.B4 net (fanout=38) 2.325 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X125Y73.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X126Y74.A5 net (fanout=13) 0.359 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X126Y74.A Tilo 0.068 ftop/gbe0/dcp_cpRespF/data1_reg<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X129Y75.B1 net (fanout=8) 0.606 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X129Y75.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X131Y84.C4 net (fanout=15) 0.825 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X131Y84.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X131Y84.B1 net (fanout=1) 0.579 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X131Y84.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.373ns (0.679ns logic, 4.694ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_19 (FF) + Requirement: 8.000ns + Data Path Delay: 5.372ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y83.CE net (fanout=14) 0.907 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 5.372ns (0.757ns logic, 4.615ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_20 (FF) + Requirement: 8.000ns + Data Path Delay: 5.372ns (Levels of Logic = 2) + Clock Path Skew: -0.283ns (1.451 - 1.734) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y54.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X130Y82.C3 net (fanout=38) 3.078 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X130Y82.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_11 + SLICE_X127Y77.B5 net (fanout=33) 0.630 ftop/gbe0/gmac/MUX_txRS_ifgCnt_value_write_1__SEL_1 + SLICE_X127Y77.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X130Y83.CE net (fanout=14) 0.907 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X130Y83.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder_20 + ------------------------------------------------- --------------------------- + Total 5.372ns (0.757ns logic, 4.615ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/phyRst/rstSync/reset_hold_0 (FF) + Destination: ftop/gbe0/phyRst/rstSync/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.091ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/phyRst/rstSync/reset_hold_0 to ftop/gbe0/phyRst/rstSync/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y41.AQ Tcko 0.098 ftop/gbe0/phyRst/rstSync/reset_hold<0> + ftop/gbe0/phyRst/rstSync/reset_hold_0 + SLICE_X90Y41.A5 net (fanout=1) 0.075 ftop/gbe0/phyRst/rstSync/reset_hold<0> + SLICE_X90Y41.CLK Tah (-Th) 0.082 ftop/gbe0/phyRst/rstSync/reset_hold<0> + ftop/gbe0/phyRst/rstSync/reset_hold<0>_rt + ftop/gbe0/phyRst/rstSync/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.091ns (0.016ns logic, 0.075ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y70.DQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X129Y70.B6 net (fanout=4) 0.051 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X129Y70.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.058ns logic, 0.051ns route) + (53.2% logic, 46.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.103ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.060 - 0.048) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X131Y66.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 + SLICE_X131Y67.AX net (fanout=1) 0.093 ftop/gbe0/gmac/txRS_txF/dSyncReg1<0> + SLICE_X131Y67.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.022ns logic, 0.093ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.103ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y70.BQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + SLICE_X129Y70.A6 net (fanout=6) 0.054 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<1> + SLICE_X129Y70.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.060ns logic, 0.054ns route) + (52.6% logic, 47.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.112ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 (FF) + Destination: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.121ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.057 - 0.048) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 to ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y53.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X99Y54.DX net (fanout=1) 0.099 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X99Y54.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + ------------------------------------------------- --------------------------- + Total 0.121ns (0.022ns logic, 0.099ns route) + (18.2% logic, 81.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y70.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + SLICE_X128Y70.C5 net (fanout=5) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<2> + SLICE_X128Y70.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_1_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.117ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y76.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + SLICE_X125Y76.C5 net (fanout=5) 0.075 ftop/gbe0/gmac/txRS_preambleCnt_value<2> + SLICE_X125Y76.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.042ns logic, 0.075ns route) + (35.9% logic, 64.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.119ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_23 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_31 (FF) + Requirement: 0.000ns + Data Path Delay: 0.155ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.463 - 0.427) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_23 to ftop/gbe0/gmac/txRS_crc/rRemainder_31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X130Y81.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/txRS_crc/rRemainder_23 + SLICE_X129Y80.B6 net (fanout=2) 0.097 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + SLICE_X129Y80.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<31>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_31 + ------------------------------------------------- --------------------------- + Total 0.155ns (0.058ns logic, 0.097ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.121ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.156ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.465 - 0.430) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y75.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_2 + SLICE_X124Y75.A6 net (fanout=39) 0.134 ftop/gbe0/gmac/txRS_emitFCS<2> + SLICE_X124Y75.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<0>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + ------------------------------------------------- --------------------------- + Total 0.156ns (0.022ns logic, 0.134ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.122ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X124Y75.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + SLICE_X124Y75.C5 net (fanout=4) 0.083 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + SLICE_X124Y75.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.122ns (0.039ns logic, 0.083ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.123ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y70.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X128Y70.DX net (fanout=2) 0.149 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X128Y70.CLK Tckdi (-Th) 0.113 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.134ns (-0.015ns logic, 0.149ns route) + (-11.2% logic, 111.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X124Y75.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + SLICE_X124Y75.D5 net (fanout=6) 0.086 ftop/gbe0/gmac/txRS_ifgCnt_value<0> + SLICE_X124Y75.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>12 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.038ns logic, 0.086ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.126ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y70.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X128Y70.A5 net (fanout=6) 0.087 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X128Y70.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_INV_4055_o1_INV_0 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.039ns logic, 0.087ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.129ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y70.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X128Y70.D5 net (fanout=6) 0.091 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X128Y70.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_2_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.038ns logic, 0.091ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.130ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.165ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.465 - 0.430) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_ifgCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y75.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X124Y75.B6 net (fanout=44) 0.144 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X124Y75.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<1>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_1 + ------------------------------------------------- --------------------------- + Total 0.165ns (0.021ns logic, 0.144ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.134ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txData_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.174ns (Levels of Logic = 1) + Clock Path Skew: 0.040ns (0.464 - 0.424) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_1 to ftop/gbe0/gmac/txRS_txData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y75.BQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF_dD_OUT<3> + ftop/gbe0/gmac/txRS_txF/dDoutReg_1 + SLICE_X127Y75.B5 net (fanout=2) 0.116 ftop/gbe0/gmac/txRS_txF_dD_OUT<1> + SLICE_X127Y75.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txData<3> + ftop/gbe0/gmac/Mmux_txRS_txData_D_IN23 + ftop/gbe0/gmac/txRS_txData_1 + ------------------------------------------------- --------------------------- + Total 0.174ns (0.058ns logic, 0.116ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y70.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + SLICE_X129Y70.B4 net (fanout=2) 0.096 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + SLICE_X129Y70.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.173ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.466 - 0.430) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y75.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_2 + SLICE_X125Y76.B6 net (fanout=39) 0.132 ftop/gbe0/gmac/txRS_emitFCS<2> + SLICE_X125Y76.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<1>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_1 + ------------------------------------------------- --------------------------- + Total 0.173ns (0.041ns logic, 0.132ns route) + (23.7% logic, 76.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.138ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.174ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.466 - 0.430) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_0 to ftop/gbe0/gmac/txRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y75.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_0 + SLICE_X125Y76.A6 net (fanout=35) 0.131 ftop/gbe0/gmac/txRS_emitFCS<0> + SLICE_X125Y76.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<0>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 0.174ns (0.043ns logic, 0.131ns route) + (24.7% logic, 75.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.140ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.140ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_emitFCS_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y75.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X123Y75.C5 net (fanout=44) 0.098 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X123Y75.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN22 + ftop/gbe0/gmac/txRS_emitFCS_1 + ------------------------------------------------- --------------------------- + Total 0.140ns (0.042ns logic, 0.098ns route) + (30.0% logic, 70.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 6.571ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys1_clk/I0 + Logical resource: ftop/sys1_clk/I0 + Location pin: BUFGCTRL_X0Y24.I0 + Clock network: ftop/sys1_clki_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_en_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxEna/CK + Location pin: OLOGIC_X2Y63.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_er_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxErr/CK + Location pin: OLOGIC_X2Y62.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_0_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData/CK + Location pin: OLOGIC_X2Y64.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_1_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_1/CK + Location pin: OLOGIC_X2Y65.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_2_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_2/CK + Location pin: OLOGIC_X2Y66.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_3_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_3/CK + Location pin: OLOGIC_X2Y67.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_4_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_4/CK + Location pin: OLOGIC_X2Y68.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_5_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_5/CK + Location pin: OLOGIC_X2Y69.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_6_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_6/CK + Location pin: OLOGIC_X2Y70.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_7_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_7/CK + Location pin: OLOGIC_X2Y71.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_gtx_clk_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxClk/CK + Location pin: OLOGIC_X2Y46.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/phyRst/rstSync/reset_hold<0>/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_1/SR + Location pin: SLICE_X90Y41.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/phyRst/rstSync/reset_hold<0>/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_0/SR + Location pin: SLICE_X90Y41.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Location pin: SLICE_X98Y53.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2/SR + Location pin: SLICE_X99Y54.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst_OUT_RST/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_1/SR + Location pin: SLICE_X104Y67.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_0/SR + Location pin: SLICE_X105Y67.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Location pin: SLICE_X111Y66.SR + Clock network: ftop/gbe0/gmac/txRS_unfBit/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF_dEMPTY_N/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg/SR + Location pin: SLICE_X126Y73.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD +TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 75766 paths analyzed, 22660 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.988ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.012ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_8 (FF) + Destination: ftop/dram0/dbg_rd_clkdly_cnt/sDataSyncIn_8 (FF) + Requirement: 5.000ns + Data Path Delay: 4.702ns (Levels of Logic = 0) + Clock Path Skew: -0.228ns (1.514 - 1.742) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_8 to ftop/dram0/dbg_rd_clkdly_cnt/sDataSyncIn_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y221.AQ Tcko 0.337 ftop/dram0/memc_memc_dbg_rd_clkdly_cnt<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_8 + SLICE_X104Y164.AX net (fanout=33) 4.350 ftop/dram0/memc_memc_dbg_rd_clkdly_cnt<8> + SLICE_X104Y164.CLK Tdick 0.015 ftop/dram0/dbg_rd_clkdly_cnt/sDataSyncIn<11> + ftop/dram0/dbg_rd_clkdly_cnt/sDataSyncIn_8 + ------------------------------------------------- --------------------------- + Total 4.702ns (0.352ns logic, 4.350ns route) + (7.5% logic, 92.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.043ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.742ns (Levels of Logic = 3) + Clock Path Skew: -0.157ns (1.537 - 1.694) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y201.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X102Y196.B5 net (fanout=144) 2.050 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X102Y196.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMB_D1 + SLICE_X93Y179.A6 net (fanout=1) 1.191 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<5> + SLICE_X93Y179.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/mask_data_rise0_r1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_n043661 + SLICE_X81Y178.D6 net (fanout=1) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mask_data_rise0<5> + SLICE_X81Y178.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/Mmux_wr_calib_dly[1]_mask_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/Mmux_wr_calib_dly[1]_mask_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + ------------------------------------------------- --------------------------- + Total 4.742ns (0.687ns logic, 4.055ns route) + (14.5% logic, 85.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.043ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_10 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_5 (FF) + Requirement: 5.000ns + Data Path Delay: 4.813ns (Levels of Logic = 2) + Clock Path Skew: -0.086ns (1.545 - 1.631) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_10 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y196.AQ Tcko 0.337 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_10 + SLICE_X70Y164.D1 net (fanout=80) 3.640 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<10> + SLICE_X70Y164.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<23> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[11]_wrdata_en_r2_Mux_54_o11 + SLICE_X70Y164.C6 net (fanout=1) 0.121 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[11]_wrdata_en_r2_Mux_54_o1 + SLICE_X70Y164.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<23> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[11]_wrdata_en_r2_Mux_54_o12 + SLICE_X71Y170.CX net (fanout=1) 0.545 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[11]_wrdata_en_r2_Mux_54_o + SLICE_X71Y170.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<21> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_dq4_5 + ------------------------------------------------- --------------------------- + Total 4.813ns (0.507ns logic, 4.306ns route) + (10.5% logic, 89.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.046ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.852ns (Levels of Logic = 3) + Clock Path Skew: -0.044ns (1.535 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X96Y196.A2 net (fanout=144) 2.285 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X96Y196.AMUX Tilo 0.196 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMA + SLICE_X77Y179.B6 net (fanout=1) 1.635 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<46> + SLICE_X77Y179.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0411 + SLICE_X77Y179.D6 net (fanout=1) 0.117 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<46> + SLICE_X77Y179.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.852ns (0.815ns logic, 4.037ns route) + (16.8% logic, 83.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.056ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.596ns (Levels of Logic = 1) + Clock Path Skew: -0.290ns (1.470 - 1.760) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y199.AQ Tcko 0.337 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_0 + SLICE_X118Y155.D2 net (fanout=80) 4.087 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<0> + SLICE_X118Y155.CLK Tas 0.172 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.596ns (0.509ns logic, 4.087ns route) + (11.1% logic, 88.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.077ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_122 (FF) + Requirement: 5.000ns + Data Path Delay: 4.859ns (Levels of Logic = 1) + Clock Path Skew: -0.006ns (1.062 - 1.068) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_122 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y180.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr<2> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 + SLICE_X60Y152.B1 net (fanout=83) 3.192 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr<0> + SLICE_X60Y152.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/n0591<136> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/gen_ram[138].u_RAM64X1D/DP + SLICE_X64Y167.CX net (fanout=1) 1.203 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/n0591<138> + SLICE_X64Y167.CLK Tdick 0.015 ftop/dram0/memc_memc_app_rd_data<123> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_122 + ------------------------------------------------- --------------------------- + Total 4.859ns (0.464ns logic, 4.395ns route) + (9.5% logic, 90.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.084ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/out_d4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_oserdes_dm (FF) + Requirement: 5.000ns + Data Path Delay: 4.705ns (Levels of Logic = 0) + Clock Path Skew: -0.153ns (1.593 - 1.746) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/out_d4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_oserdes_dm + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y167.CQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/out_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/out_d4 + OLOGIC_X1Y120.D4 net (fanout=1) 4.017 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/out_d4 + OLOGIC_X1Y120.CLKDIV Tosdck_D 0.307 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_oserdes_dm + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_oserdes_dm + ------------------------------------------------- --------------------------- + Total 4.705ns (0.688ns logic, 4.017ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.085ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_123 (FF) + Requirement: 5.000ns + Data Path Delay: 4.851ns (Levels of Logic = 1) + Clock Path Skew: -0.006ns (1.062 - 1.068) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_123 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y180.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr<2> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr_0 + SLICE_X60Y152.B1 net (fanout=83) 3.192 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/RdAdrsCntr<0> + SLICE_X60Y152.BMUX Tilo 0.205 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/n0591<136> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/gen_c1.u_rddata_sync_c1/gen_ram[139].u_RAM64X1D/DP + SLICE_X64Y167.DX net (fanout=1) 1.058 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/n0591<139> + SLICE_X64Y167.CLK Tdick 0.015 ftop/dram0/memc_memc_app_rd_data<123> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata_sync/dfi_rddata_123 + ------------------------------------------------- --------------------------- + Total 4.851ns (0.601ns logic, 4.250ns route) + (12.4% logic, 87.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.089ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.645ns (Levels of Logic = 3) + Clock Path Skew: -0.208ns (1.550 - 1.758) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y193.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X90Y194.A6 net (fanout=294) 0.246 ftop/dram0/memc_memc/rst + SLICE_X90Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_4 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A6 net (fanout=10) 1.667 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X89Y146.D6 net (fanout=8) 1.269 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X89Y146.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_7 + SLICE_X91Y154.BX net (fanout=7) 0.888 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_7 + SLICE_X91Y154.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.645ns (0.575ns logic, 4.070ns route) + (12.4% logic, 87.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.093ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.700ns (Levels of Logic = 3) + Clock Path Skew: -0.149ns (1.545 - 1.694) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y201.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X96Y196.B5 net (fanout=144) 2.493 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X96Y196.BMUX Tilo 0.205 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMB + SLICE_X77Y188.B6 net (fanout=1) 1.266 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<44> + SLICE_X77Y188.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0391 + SLICE_X77Y188.D6 net (fanout=1) 0.117 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<44> + SLICE_X77Y188.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.700ns (0.824ns logic, 3.876ns route) + (17.5% logic, 82.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.101ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.690ns (Levels of Logic = 3) + Clock Path Skew: -0.151ns (1.543 - 1.694) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y201.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X96Y196.B5 net (fanout=144) 2.493 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X96Y196.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMB_D1 + SLICE_X77Y185.B6 net (fanout=1) 1.393 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<45> + SLICE_X77Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0401 + SLICE_X77Y185.D6 net (fanout=1) 0.117 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<45> + SLICE_X77Y185.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.690ns (0.687ns logic, 4.003ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.103ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.797ns (Levels of Logic = 3) + Clock Path Skew: -0.042ns (1.537 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 + SLICE_X96Y196.C4 net (fanout=144) 2.415 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + SLICE_X96Y196.CMUX Tilo 0.194 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMC + SLICE_X76Y181.B6 net (fanout=1) 1.446 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<42> + SLICE_X76Y181.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0371 + SLICE_X76Y181.D6 net (fanout=1) 0.123 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<42> + SLICE_X76Y181.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.797ns (0.813ns logic, 3.984ns route) + (16.9% logic, 83.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.104ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.794ns (Levels of Logic = 3) + Clock Path Skew: -0.044ns (1.535 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X96Y196.A3 net (fanout=144) 2.234 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X96Y196.AMUX Tilo 0.189 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMA + SLICE_X77Y179.B6 net (fanout=1) 1.635 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<46> + SLICE_X77Y179.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0411 + SLICE_X77Y179.D6 net (fanout=1) 0.117 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<46> + SLICE_X77Y179.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.794ns (0.808ns logic, 3.986ns route) + (16.9% logic, 83.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.109ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.792ns (Levels of Logic = 2) + Clock Path Skew: -0.041ns (1.538 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 + SLICE_X88Y193.A1 net (fanout=144) 2.992 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<0> + SLICE_X88Y193.AMUX Tilo 0.196 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<241> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMA + SLICE_X79Y178.A6 net (fanout=1) 1.194 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<244> + SLICE_X79Y178.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1481 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.792ns (0.606ns logic, 4.186ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.110ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.790ns (Levels of Logic = 3) + Clock Path Skew: -0.042ns (1.537 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X102Y196.B3 net (fanout=144) 2.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X102Y196.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMB_D1 + SLICE_X93Y179.A6 net (fanout=1) 1.191 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<5> + SLICE_X93Y179.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/mask_data_rise0_r1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_n043661 + SLICE_X81Y178.D6 net (fanout=1) 0.814 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mask_data_rise0<5> + SLICE_X81Y178.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/Mmux_wr_calib_dly[1]_mask_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/Mmux_wr_calib_dly[1]_mask_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/out_d4 + ------------------------------------------------- --------------------------- + Total 4.790ns (0.687ns logic, 4.103ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.115ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.787ns (Levels of Logic = 3) + Clock Path Skew: -0.040ns (1.539 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X92Y195.C2 net (fanout=144) 2.462 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X92Y195.CMUX Tilo 0.198 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<49> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMC + SLICE_X78Y177.B6 net (fanout=1) 1.385 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<48> + SLICE_X78Y177.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0431 + SLICE_X78Y177.D6 net (fanout=1) 0.123 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<48> + SLICE_X78Y177.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.787ns (0.817ns logic, 3.970ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.122ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.596ns (Levels of Logic = 3) + Clock Path Skew: -0.224ns (1.534 - 1.758) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y193.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X90Y194.A6 net (fanout=294) 0.246 ftop/dram0/memc_memc/rst + SLICE_X90Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_4 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A6 net (fanout=10) 1.667 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X71Y137.A6 net (fanout=8) 1.267 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X71Y137.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y126.AX net (fanout=6) 0.841 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y126.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.596ns (0.575ns logic, 4.021ns route) + (12.5% logic, 87.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.125ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.572ns (Levels of Logic = 3) + Clock Path Skew: -0.245ns (1.513 - 1.758) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y193.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X90Y194.A6 net (fanout=294) 0.246 ftop/dram0/memc_memc/rst + SLICE_X90Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_4 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A6 net (fanout=10) 1.667 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X71Y137.A6 net (fanout=8) 1.267 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X71Y137.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X63Y132.CX net (fanout=6) 0.817 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X63Y132.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.572ns (0.575ns logic, 3.997ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.135ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.689ns (Levels of Logic = 3) + Clock Path Skew: -0.118ns (1.525 - 1.643) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X91Y193.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X90Y194.A6 net (fanout=294) 0.246 ftop/dram0/memc_memc/rst + SLICE_X90Y194.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_4 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A6 net (fanout=10) 1.667 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X75Y161.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X63Y187.D6 net (fanout=8) 1.552 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X63Y187.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y194.CX net (fanout=8) 0.649 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y194.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.689ns (0.575ns logic, 4.114ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.135ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.769ns (Levels of Logic = 2) + Clock Path Skew: -0.038ns (1.541 - 1.579) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y197.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 + SLICE_X88Y193.C1 net (fanout=144) 2.982 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<0> + SLICE_X88Y193.CMUX Tilo 0.198 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<241> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMC + SLICE_X82Y176.A6 net (fanout=1) 1.179 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<240> + SLICE_X82Y176.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1431 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.769ns (0.608ns logic, 4.161ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume (FF) + Requirement: 0.000ns + Data Path Delay: 0.067ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y201.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + SLICE_X96Y201.D6 net (fanout=1) 0.046 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + SLICE_X96Y201.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rdlvl_pat_resume + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r_rdlvl_resume_r2_OR_7764_o1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume + ------------------------------------------------- --------------------------- + Total 0.067ns (0.021ns logic, 0.046ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.059ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.071ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X115Y234.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_3 + SLICE_X114Y234.B6 net (fanout=4) 0.050 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r<3> + SLICE_X114Y234.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/Result<5>11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r_5 + ------------------------------------------------- --------------------------- + Total 0.071ns (0.021ns logic, 0.050ns route) + (29.6% logic, 70.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.063ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.171ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.807 - 0.699) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y199.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_4 + SLICE_X86Y200.AX net (fanout=3) 0.149 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r<4> + SLICE_X86Y200.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc_dbg_rd_bitslip_cnt<10> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_6 + ------------------------------------------------- --------------------------- + Total 0.171ns (0.022ns logic, 0.149ns route) + (12.9% logic, 87.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.065ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_cnt_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_inhbt_config_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.076ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.062 - 0.051) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_cnt_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_inhbt_config_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y229.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_cnt_r<2> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_cnt_r_1 + SLICE_X124Y229.D6 net (fanout=5) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_cnt_r<1> + SLICE_X124Y229.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/wtr_inhbt_config_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_timer.wtr_inhbt_config_ns1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/wtr_inhbt_config_r + ------------------------------------------------- --------------------------- + Total 0.076ns (0.021ns logic, 0.055ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_5 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.176ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.807 - 0.699) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_5 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y199.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r_5 + SLICE_X86Y200.BX net (fanout=3) 0.154 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_bitslip_cnt_r<5> + SLICE_X86Y200.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc_dbg_rd_bitslip_cnt<10> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_bitslip_cnt_7 + ------------------------------------------------- --------------------------- + Total 0.176ns (0.022ns logic, 0.154ns route) + (12.5% logic, 87.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_18 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.486 - 0.447) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_18 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X115Y192.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<21> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_18 + SLICE_X112Y193.AI net (fanout=1) 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<18> + SLICE_X112Y193.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<15> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.109ns (0.011ns logic, 0.098ns route) + (10.1% logic, 89.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMB + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.064 - 0.053) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X31Y192.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<2> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_0 + SLICE_X30Y192.A6 net (fanout=6) 0.059 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<0> + SLICE_X30Y192.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/Mcount_wc_oserdes_cnt_r_xor<3>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 + ------------------------------------------------- --------------------------- + Total 0.081ns (0.022ns logic, 0.059ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMC + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMA + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X84Y159.D1 net (fanout=23) 0.288 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X84Y159.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMD + ------------------------------------------------- --------------------------- + Total 0.107ns (-0.181ns logic, 0.288ns route) + (-169.2% logic, 269.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem6_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem6_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X88Y158.D1 net (fanout=23) 0.289 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X88Y158.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<35> + ftop/dram0/lrespF/Mram_fifoMem6_RAMB + ------------------------------------------------- --------------------------- + Total 0.108ns (-0.181ns logic, 0.289ns route) + (-167.6% logic, 267.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem6_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem6_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X88Y158.D1 net (fanout=23) 0.289 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X88Y158.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<35> + ftop/dram0/lrespF/Mram_fifoMem6_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.108ns (-0.181ns logic, 0.289ns route) + (-167.6% logic, 267.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem6_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem6_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X88Y158.D1 net (fanout=23) 0.289 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X88Y158.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<35> + ftop/dram0/lrespF/Mram_fifoMem6_RAMA + ------------------------------------------------- --------------------------- + Total 0.108ns (-0.181ns logic, 0.289ns route) + (-167.6% logic, 267.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem6_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem6_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X88Y158.D1 net (fanout=23) 0.289 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X88Y158.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<35> + ftop/dram0/lrespF/Mram_fifoMem6_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.108ns (-0.181ns logic, 0.289ns route) + (-167.6% logic, 267.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem6_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.108ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.521 - 0.484) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem6_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y158.AQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X88Y158.D1 net (fanout=23) 0.289 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X88Y158.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<35> + ftop/dram0/lrespF/Mram_fifoMem6_RAMC + ------------------------------------------------- --------------------------- + Total 0.108ns (-0.181ns logic, 0.289ns route) + (-167.6% logic, 267.6% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMA/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMA/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMA_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMA_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMB/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMB/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMB_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMB_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMC/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMC/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMC_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMC_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMD/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMD/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<41>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1/CLK + Location pin: SLICE_X68Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA/CLK + Location pin: SLICE_X68Y156.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA/CLK + Location pin: SLICE_X68Y156.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA_D1/CLK + Location pin: SLICE_X68Y156.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA_D1/CLK + Location pin: SLICE_X68Y156.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = +PERIOD TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" +TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.429ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" TS_SYS0CLK * 2 + HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.071ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 997.500ns (max period limit - period) + Period: 2.500ns + Max period limit: 1000.000ns (1.000MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD TIMEGRP +"ftop_dram0_memc_memc_clk_wr_i" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.232ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.268ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.523ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.369 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X98Y27.DX net (fanout=1) 1.150 gmii_rxd_7_IBUF + SLICE_X98Y27.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.523ns (0.373ns logic, 1.150ns route) + (24.5% logic, 75.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 2.161ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.256ns (Levels of Logic = 1) + Clock Path Delay: 2.570ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.669 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X98Y27.DX net (fanout=1) 1.726 gmii_rxd_7_IBUF + SLICE_X98Y27.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 2.256ns (0.530ns logic, 1.726ns route) + (23.5% logic, 76.5% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.959 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.570ns (1.227ns logic, 1.343ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.196ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.304ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.487ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.374 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X98Y27.CX net (fanout=1) 1.109 gmii_rxd_6_IBUF + SLICE_X98Y27.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.487ns (0.378ns logic, 1.109ns route) + (25.4% logic, 74.6% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 2.103ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.198ns (Levels of Logic = 1) + Clock Path Delay: 2.570ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.672 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X98Y27.CX net (fanout=1) 1.665 gmii_rxd_6_IBUF + SLICE_X98Y27.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 2.198ns (0.533ns logic, 1.665ns route) + (24.2% logic, 75.8% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.959 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.570ns (1.227ns logic, 1.343ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.116ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.384ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.407ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.390 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X98Y27.BX net (fanout=1) 1.013 gmii_rxd_5_IBUF + SLICE_X98Y27.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.407ns (0.394ns logic, 1.013ns route) + (28.0% logic, 72.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.996ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.091ns (Levels of Logic = 1) + Clock Path Delay: 2.570ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.686 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X98Y27.BX net (fanout=1) 1.544 gmii_rxd_5_IBUF + SLICE_X98Y27.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 2.091ns (0.547ns logic, 1.544ns route) + (26.2% logic, 73.8% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.959 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.570ns (1.227ns logic, 1.343ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.038ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.462ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.329ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.433 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X98Y27.AX net (fanout=1) 0.892 gmii_rxd_4_IBUF + SLICE_X98Y27.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.329ns (0.437ns logic, 0.892ns route) + (32.9% logic, 67.1% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.832ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.927ns (Levels of Logic = 1) + Clock Path Delay: 2.570ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.723 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X98Y27.AX net (fanout=1) 1.343 gmii_rxd_4_IBUF + SLICE_X98Y27.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.927ns (0.584ns logic, 1.343ns route) + (30.3% logic, 69.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y27.CLK net (fanout=43) 0.959 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.570ns (1.227ns logic, 1.343ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.010ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.510ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.285ns (Levels of Logic = 1) + Clock Path Delay: 1.320ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.435 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X98Y31.DX net (fanout=1) 0.846 gmii_rxd_3_IBUF + SLICE_X98Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.285ns (0.439ns logic, 0.846ns route) + (34.2% logic, 65.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.405 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.320ns (0.774ns logic, 0.546ns route) + (58.6% logic, 41.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.819ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.919ns (Levels of Logic = 1) + Clock Path Delay: 2.575ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.725 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X98Y31.DX net (fanout=1) 1.333 gmii_rxd_3_IBUF + SLICE_X98Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.919ns (0.586ns logic, 1.333ns route) + (30.5% logic, 69.5% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.964 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.575ns (1.227ns logic, 1.348ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.042ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.542ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.253ns (Levels of Logic = 1) + Clock Path Delay: 1.320ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.375 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X98Y31.CX net (fanout=1) 0.874 gmii_rxd_2_IBUF + SLICE_X98Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.253ns (0.379ns logic, 0.874ns route) + (30.2% logic, 69.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.405 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.320ns (0.774ns logic, 0.546ns route) + (58.6% logic, 41.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.759ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.859ns (Levels of Logic = 1) + Clock Path Delay: 2.575ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.673 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X98Y31.CX net (fanout=1) 1.325 gmii_rxd_2_IBUF + SLICE_X98Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.859ns (0.534ns logic, 1.325ns route) + (28.7% logic, 71.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.964 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.575ns (1.227ns logic, 1.348ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.033ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.533ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.262ns (Levels of Logic = 1) + Clock Path Delay: 1.320ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.381 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X98Y31.BX net (fanout=1) 0.877 gmii_rxd_1_IBUF + SLICE_X98Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.262ns (0.385ns logic, 0.877ns route) + (30.5% logic, 69.5% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.405 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.320ns (0.774ns logic, 0.546ns route) + (58.6% logic, 41.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.759ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.859ns (Levels of Logic = 1) + Clock Path Delay: 2.575ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.678 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X98Y31.BX net (fanout=1) 1.320 gmii_rxd_1_IBUF + SLICE_X98Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.859ns (0.539ns logic, 1.320ns route) + (29.0% logic, 71.0% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.964 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.575ns (1.227ns logic, 1.348ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.152ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.348ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.447ns (Levels of Logic = 1) + Clock Path Delay: 1.320ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.435 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X98Y31.AX net (fanout=1) 1.008 gmii_rxd_0_IBUF + SLICE_X98Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.447ns (0.439ns logic, 1.008ns route) + (30.3% logic, 69.7% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.405 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.320ns (0.774ns logic, 0.546ns route) + (58.6% logic, 41.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.947ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.047ns (Levels of Logic = 1) + Clock Path Delay: 2.575ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.725 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X98Y31.AX net (fanout=1) 1.461 gmii_rxd_0_IBUF + SLICE_X98Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 2.047ns (0.586ns logic, 1.461ns route) + (28.6% logic, 71.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X98Y31.CLK net (fanout=43) 0.964 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.575ns (1.227ns logic, 1.348ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.264ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.236ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.545ns (Levels of Logic = 1) + Clock Path Delay: 1.306ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.425 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X92Y26.BX net (fanout=1) 1.125 gmii_rx_dv_IBUF + SLICE_X92Y26.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.545ns (0.420ns logic, 1.125ns route) + (27.2% logic, 72.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y26.CLK net (fanout=43) 0.391 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.306ns (0.774ns logic, 0.532ns route) + (59.3% logic, 40.7% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 2.040ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.116ns (Levels of Logic = 1) + Clock Path Delay: 2.551ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.716 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X92Y26.BX net (fanout=1) 1.568 gmii_rx_dv_IBUF + SLICE_X92Y26.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 2.116ns (0.548ns logic, 1.568ns route) + (25.9% logic, 74.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y26.CLK net (fanout=43) 0.940 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.551ns (1.227ns logic, 1.324ns route) + (48.1% logic, 51.9% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.323ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.823ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.964ns (Levels of Logic = 1) + Clock Path Delay: 1.312ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.393 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y36.AX net (fanout=1) 0.567 gmii_rx_er_IBUF + SLICE_X93Y36.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 0.964ns (0.397ns logic, 0.567ns route) + (41.2% logic, 58.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y36.CLK net (fanout=43) 0.397 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.312ns (0.774ns logic, 0.538ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.353ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.437ns (Levels of Logic = 1) + Clock Path Delay: 2.559ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.689 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y36.AX net (fanout=1) 0.887 gmii_rx_er_IBUF + SLICE_X93Y36.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 1.437ns (0.550ns logic, 0.887ns route) + (38.3% logic, 61.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y36.CLK net (fanout=43) 0.948 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.559ns (1.227ns logic, 1.332ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Pin to Pin Skew Constraint; + + 1 path analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- +Slack: 0.108ns (maxskew - uncertainty - (arrival1 - arrival2)) + Max skew: 0.450ns + Arrival 1: 2.658ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Arrival 2: 2.505ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/USERCLK + Clock Uncertainty: 0.189ns + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 4.988ns| 0| 0| 91995| 75766| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 4.988ns| N/A| 0| 0| 75766| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.307ns| 0| 158| 0| 12943666| +| TS_CLK_125 | 8.000ns| 8.287ns| N/A| 68| 0| 12924369| 0| +| TS_CLK_250 | 4.000ns| 4.307ns| N/A| 90| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +2 constraints not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock gmii_rx_clk +------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +------------+------------+------------+------------+------------+------------------+--------+ +gmii_rx_dv | 0.264(R)| FAST | 0.460(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rx_er | -0.323(R)| FAST | 1.147(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<0> | 0.152(R)| FAST | 0.553(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<1> | -0.033(R)| FAST | 0.741(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<2> | -0.042(R)| FAST | 0.741(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<3> | -0.010(R)| FAST | 0.681(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<4> | 0.038(R)| FAST | 0.668(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<5> | 0.116(R)| FAST | 0.504(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<6> | 0.196(R)| FAST | 0.397(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<7> | 0.232(R)| FAST | 0.339(R)| SLOW |ftop/rxclkBnd | 0.000| +------------+------------+------------+------------+------------+------------------+--------+ + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 6.212| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 4.988| | | | +sys0_clkp | 4.988| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 4.988| | | | +sys0_clkp | 4.988| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.857| | | | +sys1_clkp | 5.857| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.857| | | | +sys1_clkp | 5.857| | | | +---------------+---------+---------+---------+---------+ + +COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.571; Ideal Clock Offset To Actual Clock 0.947; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<7> | 0.232(R)| FAST | 0.339(R)| SLOW | 0.268| 2.161| -0.947| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.232| - | 0.339| - | 0.268| 2.161| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.593; Ideal Clock Offset To Actual Clock 0.900; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<6> | 0.196(R)| FAST | 0.397(R)| SLOW | 0.304| 2.103| -0.900| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.196| - | 0.397| - | 0.304| 2.103| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.620; Ideal Clock Offset To Actual Clock 0.806; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<5> | 0.116(R)| FAST | 0.504(R)| SLOW | 0.384| 1.996| -0.806| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.116| - | 0.504| - | 0.384| 1.996| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.706; Ideal Clock Offset To Actual Clock 0.685; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<4> | 0.038(R)| FAST | 0.668(R)| SLOW | 0.462| 1.832| -0.685| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.038| - | 0.668| - | 0.462| 1.832| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.671; Ideal Clock Offset To Actual Clock 0.655; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<3> | -0.010(R)| FAST | 0.681(R)| SLOW | 0.510| 1.819| -0.655| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.010| - | 0.681| - | 0.510| 1.819| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.699; Ideal Clock Offset To Actual Clock 0.608; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<2> | -0.042(R)| FAST | 0.741(R)| SLOW | 0.542| 1.759| -0.608| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.042| - | 0.741| - | 0.542| 1.759| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.708; Ideal Clock Offset To Actual Clock 0.613; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<1> | -0.033(R)| FAST | 0.741(R)| SLOW | 0.533| 1.759| -0.613| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.033| - | 0.741| - | 0.533| 1.759| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.705; Ideal Clock Offset To Actual Clock 0.800; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<0> | 0.152(R)| FAST | 0.553(R)| SLOW | 0.348| 1.947| -0.800| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.152| - | 0.553| - | 0.348| 1.947| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.724; Ideal Clock Offset To Actual Clock 0.902; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_dv | 0.264(R)| FAST | 0.460(R)| SLOW | 0.236| 2.040| -0.902| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.264| - | 0.460| - | 0.236| 2.040| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.824; Ideal Clock Offset To Actual Clock 0.265; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_er | -0.323(R)| FAST | 1.147(R)| SLOW | 0.823| 1.353| -0.265| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.323| - | 1.147| - | 0.823| 1.353| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + + +Timing summary: +--------------- + +Timing errors: 158 Score: 20558 (Setup/Max: 20558, Hold: 0) + +Constraints cover 13119986 paths, 0 nets, and 213483 connections + +Design statistics: + Minimum period: 8.287ns{1} (Maximum frequency: 120.671MHz) + Minimum input required time before clock: 0.264ns + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Mon Jan 27 11:39:54 2014 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 1651 MB + + + diff --git a/logs/ml605-20140127_1142/fpgaTop_map.mrp b/logs/ml605-20140127_1142/fpgaTop_map.mrp new file mode 100644 index 00000000..96b2252c --- /dev/null +++ b/logs/ml605-20140127_1142/fpgaTop_map.mrp @@ -0,0 +1,8368 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc6vlx240t-ff1156-1 -w -logic_opt on -xe n -mt on -t 1 -register_duplication on -ir off -pr off +-lc off -power off -o fpgaTop_map.ncd fpgaTop.ngd fpgaTop.pcf +Target Device : xc6vlx240t +Target Package : ff1156 +Target Speed : -1 +Mapper Version : virtex6 -- $Revision: 1.55 $ +Mapped Date : Mon Jan 27 11:16:54 2014 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 600 +Slice Logic Utilization: + Number of Slice Registers: 33,952 out of 301,440 11% + Number used as Flip Flops: 33,945 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 42,089 out of 150,720 27% + Number used as logic: 36,207 out of 150,720 24% + Number using O6 output only: 32,631 + Number using O5 output only: 2,408 + Number using O5 and O6: 1,168 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 799 + Number with same-slice register load: 667 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,438 out of 37,680 43% + Number of LUT Flip Flop pairs used: 49,974 + Number with an unused Flip Flop: 17,072 out of 49,974 34% + Number with an unused LUT: 7,885 out of 49,974 15% + Number of fully used LUT-FF pairs: 25,017 out of 49,974 50% + Number of unique control sets: 1,960 + Number of slice register sites lost + to control set restrictions: 9,491 out of 301,440 3% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + +Average Fanout of Non-Clock Nets: 4.08 + +Peak Memory Usage: 2434 MB +Total REAL time to MAP completion: 15 mins 49 secs +Total CPU time to MAP completion (all processors): 16 mins 35 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_10_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_11_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_12_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_13_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_14_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_15_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_0_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_1_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_2_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_3_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_4_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_5_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_6_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_7_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_8_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_9_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. + The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:2045 - The MMCM_ADV block has CLKOUT pins + that do not drive the same kind of BUFFER load. Routing from the different buffer types will not be phase aligned. + +Section 3 - Informational +------------------------- +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network N100 has no load. +INFO:LIT:395 - The above info message is repeated 4271 more times for the + following (max. 5 shown): + N101, + N102, + N103, + N104, + N105 + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to + 1.050 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_221" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_221) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_222" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_222) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_223" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_223) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_224" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_224) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_225" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_225) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_226" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_226) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_227" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_227) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_228" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_228) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_229" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_229) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_230" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_230) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_231" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_231) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_232" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_232) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_233" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_233) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_234" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_234) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_235" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_235) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_236" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_236) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_237" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_237) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_238" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_238) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_239" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_239) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_240" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_240) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_241" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_241) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_242" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_242) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_243" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_243) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_244" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_244) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_245" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_245) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_246" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_246) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_247" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_247) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 378 block(s) removed + 419 block(s) optimized away +1789 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +Loadless block "ftop/ctop/inf/cpTlp/Msub_byteCount__h207611" (ROM) removed. +Loadless block "ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block "ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram +[0].RAM32M0" (RAM32M) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<4>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<3>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<2>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<1>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<0>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_0" (FF) removed. +Loadless block "ftop/gbe0/gmac/gmii_rx_clk" (BUFIODQS) removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<31>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<30>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<29>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<28>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<27>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<26>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<25>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<24>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<23>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<22>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<21>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<20>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<19>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<18>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<17>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<16>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<7>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<6>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<5>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<4>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<3>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<2>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tcfg_req_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_terr_drop_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rsrc_dsc_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rerrfwd_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_rd_wr_done_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_err_cpl_rdy_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_rdy_n" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msienable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixenable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixfm" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_en" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_status" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_gen2_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_partner_gen2_supported" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_upcfg_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_received_hot_rst" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCCHECKEN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCGENEN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGERRAERHEADERLOGSETN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRCOR" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRNONFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMASNAK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETO" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETOACK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMPME" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDSETSLOTPOWERLIMIT" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDUNLOCK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVASREQL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL23N" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVREQACKN" is sourceless +and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGSLOTCONTROLELECTROMECHILCTLPULSE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTION" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONTYPE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRA" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRB" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRC" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRD" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRE" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRF" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRG" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRH" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRI" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRJ" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRK" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDRDY" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/LNKCLKEN" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRESET" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLPHYLNKUPN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/RECEIVEDFUNCLVLRSTN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNRECRCERRN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNTDLLPDSTRDYN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<15>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<14>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<13>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<12>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<11>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<10>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<9>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<8>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<7>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<0>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<31>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<30>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<29>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<28>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<27>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<26>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<25>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<24>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<23>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<22>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<21>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<20>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<19>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<18>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<17>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<16>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<47>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<46>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<45>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<44>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<43>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<42>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<41>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<40>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<39>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<38>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<37>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<36>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<35>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<34>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<33>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<32>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<63>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<62>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<61>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<60>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<59>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<58>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<57>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<56>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<55>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<54>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<53>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<52>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<51>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<50>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<49>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<48>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<68>" +is sourceless and has been removed. +The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n008211" (ROM) removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n0082" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" (SFF) removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" (ROM) +removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" is sourceless and +has been removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<23>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<22>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<21>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<20>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<19>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<18>" is sourceless and has been +removed. +The signal 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is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<31>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<30>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<29>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<28>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<27>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<26>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<25>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<24>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<23>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<22>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<21>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<20>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<19>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<18>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<17>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<16>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dqs_n_tap_cnt<32>" is sourceless and has +been removed. + Sourceless block "ftop/dram0/memc_memc/scl_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/scl" is sourceless and has been removed. + Sourceless block "ftop/dram0/memc_memc/sda_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/sda" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/N1" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<39>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<38>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<37>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<36>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<35>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<34>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<33>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<32>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<31>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<30>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<29>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<28>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<27>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<26>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<25>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<24>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<23>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<22>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<21>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<20>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<19>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<18>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<17>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<16>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<15>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<14>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<13>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<12>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<11>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<10>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<9>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<8>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<7>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<6>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<5>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<4>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<3>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<2>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<1>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<0>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/ddr_parity" is sourceless and has +been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<9>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<8>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<7>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<6>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<5>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<4>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<3>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<2>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<1>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<0>" +is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/inv_dqs<0>1 +" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<97>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<99>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<100>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<101>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<102>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<103>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<104>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<105>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<106>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<107>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<160>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<161>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<162>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<163>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<164>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<165>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<166>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<167>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<168>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<169>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<170>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<171>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<172>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<173>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<174>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<175>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<176>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<177>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<178>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<179>" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_infrastructure/PSDONE" is sourceless and has +been removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[100].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[101].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[102].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[103].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[104].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[105].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[106].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[107].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[97].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[99].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[160].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[161].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[162].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[163].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[164].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[165].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[166].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[167].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[168].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[169].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[170].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[171].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[172].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[173].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[174].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[175].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[176].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[177].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[178].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[179].u_RAM64X1D" (RAM64X1D) removed. +Unused block "ftop/dram0/memc_memc/XST_GND" (ZERO) removed. +Unused block "ftop/dram0/memc_memc/XST_VCC" (ONE) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/u_out_ +parity" (OSERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. + +Optimized Block(s): +TYPE BLOCK +VCC XST_VCC +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/cap0/XST_GND +VCC ftop/cap0/XST_VCC +GND ftop/cap0/dataBram_0_memory/XST_GND +VCC ftop/cap0/dataBram_0_memory/XST_VCC +GND ftop/cap0/dataBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_0_memory/XST_GND +VCC ftop/cap0/metaBram_0_memory/XST_VCC +GND ftop/cap0/metaBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_1_memory/XST_GND +VCC ftop/cap0/metaBram_1_memory/XST_VCC +GND ftop/cap0/metaBram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_2_memory/XST_GND +VCC ftop/cap0/metaBram_2_memory/XST_VCC +GND ftop/cap0/metaBram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_3_memory/XST_GND +VCC ftop/cap0/metaBram_3_memory/XST_VCC +GND ftop/cap0/metaBram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/wci_wslv_reqF/XST_GND +GND ftop/cap0/wsiS_reqFifo/XST_GND +VCC ftop/cap0/wsiS_reqFifo/XST_VCC +GND ftop/ctop/app/XST_GND +GND ftop/ctop/app/appW1/XST_GND +VCC ftop/ctop/app/appW1/XST_VCC +GND ftop/ctop/app/appW1/rgen_gsF/XST_GND +GND ftop/ctop/app/appW1/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW2/XST_GND +VCC ftop/ctop/app/appW2/XST_VCC +GND ftop/ctop/app/appW2/respF_memory/XST_GND +VCC ftop/ctop/app/appW2/respF_memory/XST_VCC +GND ftop/ctop/app/appW2/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/XST_GND +VCC ftop/ctop/app/appW3/XST_VCC +GND ftop/ctop/app/appW3/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/appW4/XST_GND +VCC ftop/ctop/app/appW4/XST_VCC +GND ftop/ctop/app/appW4/respF_memory/XST_GND +VCC ftop/ctop/app/appW4/respF_memory/XST_VCC +GND ftop/ctop/app/appW4/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW4/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/id/XST_GND +VCC ftop/ctop/app/id/XST_VCC +GND ftop/ctop/inf/cp/XST_GND +VCC ftop/ctop/inf/cp/XST_VCC +GND ftop/ctop/inf/cp/bluart/XST_GND +VCC ftop/ctop/inf/cp/bluart/XST_VCC +GND ftop/ctop/inf/cp/bluart/rxF/XST_GND +GND ftop/ctop/inf/cp/rom_memory/XST_GND +VCC ftop/ctop/inf/cp/rom_memory/XST_VCC +GND ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/ctop/inf/cp/timeServ_setRefF/XST_GND +VCC ftop/ctop/inf/cp/wci_10_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_11_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_12_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_13_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_14_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_1_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_2_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_3_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_4_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_8_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_9_mReset/rstSync/XST_VCC +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h207610 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20762 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20763 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20764 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20765 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20766 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20767 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20768 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20769 + optimized to 1 +GND ftop/ctop/inf/cpTlp/XST_GND +VCC ftop/ctop/inf/cpTlp/XST_VCC +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp0/XST_GND +VCC ftop/ctop/inf/dp0/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/wci_reqF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_reqF/XST_GND +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp1/XST_GND +VCC ftop/ctop/inf/dp1/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/wci_reqF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_dhF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_reqF/XST_GND +GND ftop/dram0/XST_GND +VCC ftop/dram0/XST_VCC +GND ftop/dram0/dbg_dqs_n_tap_cnt/XST_GND +GND ftop/dram0/dbg_dqs_p_tap_cnt/XST_GND +GND ftop/dram0/dbg_rdlvl_err/XST_GND +GND ftop/dram0/lreqF/XST_GND +GND ftop/dram0/lrespF/XST_GND +GND ftop/dram0/memc_memc/u_infrastructure/XST_GND +VCC ftop/dram0/memc_memc/u_infrastructure/XST_VCC +GND ftop/dram0/memc_memc/u_iodelay_ctrl/XST_GND +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_state0/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd +_top/gen_pd[0].gen_pd_inst.u_phy_pd/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wr +lvl/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_G +ND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_V +CC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctr +l_sync/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_VCC +VCC ftop/dram0/memc_rst_stretch_n/XST_VCC +GND ftop/dram0/wci_wslv_reqF/XST_GND +GND ftop/flash0/XST_GND +VCC ftop/flash0/XST_VCC +GND ftop/flash0/wci_wslv_reqF/XST_GND +GND ftop/fmc150/XST_GND +VCC ftop/fmc150/XST_VCC +VCC ftop/fmc150/fcCdc_testRst/XST_VCC +VCC ftop/fmc150/spiCDC_slowReset/XST_VCC +VCC ftop/fmc150/spiDAC_slowReset/XST_VCC +GND ftop/fmc150/wci_wslv_reqF/XST_GND +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/rxRS_rxRst/XST_VCC +GND ftop/gbe0/gmac/txRS_txF/XST_GND +VCC ftop/gbe0/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbe0/wci_wslv_reqF/XST_GND +GND ftop/lcd_ctrl/XST_GND +VCC ftop/lcd_ctrl/XST_VCC +GND ftop/pciw_fI2P/XST_GND +GND ftop/pciw_fP2I/XST_GND +VCC ftop/pciw_p125rst/XST_VCC +VCC ftop/pciw_p250rst/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_VCC +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/XS +T_GND +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_VCC +VCC ftop/sys0_rst/XST_VCC +LUT2 ftop/ctop/inf/noc_sm2/pktFork/fo1/Result<2>_SW0 + optimized to 0 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ddr3_addr<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<8> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<9> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<10> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<11> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<12> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cas_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ck_n<0> | IOBS | OUTPUT | DIFF_SSTL15 | | | | | | | +| ddr3_ck_p<0> | IOBM | OUTPUT | DIFF_SSTL15 | | | | OSERDES | | | +| ddr3_cke<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cs_n<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_dm<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dq<0> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<1> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<2> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<3> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<4> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<5> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<6> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<7> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<8> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<9> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<10> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<11> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<12> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<13> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<14> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<15> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<16> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<17> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<18> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<19> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<20> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<21> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<22> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<23> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<24> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<25> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<26> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<27> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<28> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<29> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<30> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<31> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<32> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<33> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<34> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<35> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<36> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<37> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<38> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<39> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<40> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<41> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<42> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<43> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<44> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<45> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<46> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<47> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<48> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<49> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<50> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<51> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<52> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<53> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<54> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<55> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<56> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<57> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<58> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<59> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<60> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<61> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<62> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<63> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_n<0> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<1> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<2> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<3> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<4> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<5> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<6> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<7> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_p<0> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_p<1> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<2> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<3> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<4> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<5> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<6> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<7> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_odt<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ras_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_reset_n | IOB | OUTPUT | SSTL15 | | | | ODDR | | | +| ddr3_we_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| flash_addr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_ce_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_oe_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_wait | IOB | INPUT | LVCMOS25 | | | | | | | +| flash_we_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_clk_n | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_clk_p | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_pdn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_refen | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| flp_com_sclk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_com_sdc2m | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| gmii_rx_clk | IOB | INPUT | LVCMOS25 | | | | | | FIXED | +| gmii_rx_dv | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rx_er | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<7> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| lcd_db<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_e | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rw | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdd | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| pci0_clkn | IPAD | INPUT | | | | | | | | +| pci0_clkp | IPAD | INPUT | | | | | | | | +| pci0_reset_n | IOB | INPUT | LVCMOS25 | | | | | PULLUP | | +| pci_exp_rxn<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<3> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<3> | IPAD | INPUT | | | | | | | | +| pci_exp_txn<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<3> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<3> | OPAD | OUTPUT | | | | | | | | +| ppsExtIn | IOB | INPUT | LVCMOS25 | | | | | | | +| ppsOut | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| sys0_clkn | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys0_clkp | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys1_clkn | IPAD | INPUT | | | | | | | | +| sys1_clkp | IPAD | INPUT | | | | | | | | +| upads_cts_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_rts | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| upads_rx_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_tx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_pcie0" + No COMPRESSION specified for Area Group "AG_pcie0" + RANGE: SLICE_X136Y147:SLICE_X155Y120 + Slice Logic Utilization: + Number of Slice Registers: 458 out of 4,480 10% + Number of Slice LUTs: 674 out of 2,240 30% + Number used as logic: 670 + Number used as Memory: 4 + Slice Logic Distribution: + Number of occupied Slices: 259 out of 560 46% + Number of LUT Flip Flop pairs used: 745 + Number with an unused Flip Flop: 315 out of 745 42% + Number with an unused LUT: 64 out of 745 8% + Number of fully used LUT-FF pairs: 366 out of 745 49% + Number of RAMB36E1/FIFO36E1s: 8 + Number using RAMB36E1 only: 8 + Number using FIFO36E1 only: 0 + + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/rtl/mkBLUART.v b/rtl/mkBLUART.v index aed44977..51e36e2a 100644 --- a/rtl/mkBLUART.v +++ b/rtl/mkBLUART.v @@ -1,15 +1,15 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:20:45 EST 2014 +// On Mon Jan 27 10:59:26 EST 2014 // // // Ports: // Name I/O size props // RDY_setClkDiv_put O 1 const -// txLevel O 16 +// txLevel O 8 // RDY_txLevel O 1 const -// rxLevel O 16 +// rxLevel O 8 // RDY_rxLevel O 1 const // RDY_txChar_put O 1 reg // rxChar_get O 8 reg @@ -80,11 +80,11 @@ module mkBLUART(CLK, output RDY_setClkDiv_put; // value method txLevel - output [15 : 0] txLevel; + output [7 : 0] txLevel; output RDY_txLevel; // value method rxLevel - output [15 : 0] rxLevel; + output [7 : 0] rxLevel; output RDY_rxLevel; // action method txChar_put @@ -110,8 +110,7 @@ module mkBLUART(CLK, input pads_rx_arg; // signals for module outputs - wire [15 : 0] rxLevel, txLevel; - wire [7 : 0] rxChar_get; + wire [7 : 0] rxChar_get, rxLevel, txLevel; wire RDY_rxChar_get, RDY_rxLevel, RDY_setClkDiv_put, @@ -184,23 +183,22 @@ module mkBLUART(CLK, wire WILL_FIRE_RL_update_txBitCnt; // remaining internal signals - reg CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1, - CASE_txBitCnt_2_txFEMPTY_N_3_txFEMPTY_N_4_tx_ETC__q2; - wire [15 : 0] IF_rxBitCnt_9_EQ_10_3_AND_rxBaudCnt_4_EQ_clkDi_ETC___d87; - wire rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76, - rxBaudCnt_4_ULT_clkDiv___d80, - rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d84, - rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d91; + wire [15 : 0] IF_rxBitCnt_7_EQ_10_1_AND_rxBaudCnt_2_EQ_clkDi_ETC___d45; + wire [9 : 0] txa__h2921; + wire rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34, + rxBaudCnt_2_ULT_clkDiv___d38, + rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d42, + rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d49; // action method setClkDiv_put assign RDY_setClkDiv_put = 1'd1 ; // value method txLevel - assign txLevel = txF_EMPTY_N ? 16'd1 : 16'd0 ; + assign txLevel = txF_EMPTY_N ? 8'd1 : 8'd0 ; assign RDY_txLevel = 1'd1 ; // value method rxLevel - assign rxLevel = rxF_EMPTY_N ? 16'd1 : 16'd0 ; + assign rxLevel = rxF_EMPTY_N ? 8'd1 : 8'd0 ; assign RDY_rxLevel = 1'd1 ; // action method txChar_put @@ -217,15 +215,18 @@ module mkBLUART(CLK, assign pads_tx = txData ; // submodule rxF - FIFO2 #(.width(32'd8), .guarded(32'd1)) rxF(.RST(RST_N), - .CLK(CLK), - .D_IN(rxF_D_IN), - .ENQ(rxF_ENQ), - .DEQ(rxF_DEQ), - .CLR(rxF_CLR), - .D_OUT(rxF_D_OUT), - .FULL_N(rxF_FULL_N), - .EMPTY_N(rxF_EMPTY_N)); + SizedFIFO #(.p1width(32'd8), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd1)) rxF(.RST(RST_N), + .CLK(CLK), + .D_IN(rxF_D_IN), + .ENQ(rxF_ENQ), + .DEQ(rxF_DEQ), + .CLR(rxF_CLR), + .D_OUT(rxF_D_OUT), + .FULL_N(rxF_FULL_N), + .EMPTY_N(rxF_EMPTY_N)); // submodule txF FIFO2 #(.width(32'd8), .guarded(32'd1)) txF(.RST(RST_N), @@ -250,19 +251,19 @@ module mkBLUART(CLK, assign rxBaudCnt_D_IN = (rxBitCnt == 4'd0 && rxD == 2'b10) ? 16'd1 : - IF_rxBitCnt_9_EQ_10_3_AND_rxBaudCnt_4_EQ_clkDi_ETC___d87 ; + IF_rxBitCnt_7_EQ_10_1_AND_rxBaudCnt_2_EQ_clkDi_ETC___d45 ; assign rxBaudCnt_EN = - rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d84 ; + rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d42 ; // register rxBitCnt assign rxBitCnt_D_IN = (rxBitCnt == 4'd0 && rxD == 2'b10) ? 4'd1 : - ((rxBitCnt == 4'd10 && rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76) ? + ((rxBitCnt == 4'd10 && rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34) ? 4'd0 : rxBitCnt + 4'd1) ; assign rxBitCnt_EN = - rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d91 ; + rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d49 ; // register rxCtsReg assign rxCtsReg_D_IN = pads_cts_arg ; @@ -278,7 +279,7 @@ module mkBLUART(CLK, // register rxV assign rxV_D_IN = { rxD[1], rxV[7:1] } ; - assign rxV_EN = rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76 ; + assign rxV_EN = rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34 ; // register txBaudCnt assign txBaudCnt_D_IN = (txBaudCnt < clkDiv) ? txBaudCnt + 16'd1 : 16'd0 ; @@ -298,20 +299,8 @@ module mkBLUART(CLK, (txF_EMPTY_N || txBitCnt != 4'd0) ; // register txData - assign txData_D_IN = - txBitCnt == 4'd0 || - txBitCnt != 4'd1 && - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 ; - assign txData_EN = - CASE_txBitCnt_2_txFEMPTY_N_3_txFEMPTY_N_4_tx_ETC__q2 && - (txBitCnt == 4'd0 || txBitCnt == 4'd1 || txBitCnt == 4'd2 || - txBitCnt == 4'd3 || - txBitCnt == 4'd4 || - txBitCnt == 4'd5 || - txBitCnt == 4'd6 || - txBitCnt == 4'd7 || - txBitCnt == 4'd8 || - txBitCnt == 4'd9) ; + assign txData_D_IN = txa__h2921[txBitCnt] ; + assign txData_EN = txF_EMPTY_N ; // register txSendPtr assign txSendPtr_D_IN = 8'h0 ; @@ -321,7 +310,7 @@ module mkBLUART(CLK, assign rxF_D_IN = rxV ; assign rxF_ENQ = rxF_FULL_N && rxD[1] && rxBitCnt == 4'd10 && - rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76 ; + rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34 ; assign rxF_DEQ = EN_rxChar_get ; assign rxF_CLR = 1'b0 ; @@ -332,51 +321,22 @@ module mkBLUART(CLK, assign txF_CLR = 1'b0 ; // remaining internal signals - assign IF_rxBitCnt_9_EQ_10_3_AND_rxBaudCnt_4_EQ_clkDi_ETC___d87 = - (rxBitCnt == 4'd10 && rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76) ? + assign IF_rxBitCnt_7_EQ_10_1_AND_rxBaudCnt_2_EQ_clkDi_ETC___d45 = + (rxBitCnt == 4'd10 && rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34) ? 16'd0 : - (rxBaudCnt_4_ULT_clkDiv___d80 ? rxBaudCnt + 16'd1 : 16'd1) ; - assign rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76 = rxBaudCnt == clkDiv >> 1 ; - assign rxBaudCnt_4_ULT_clkDiv___d80 = rxBaudCnt < clkDiv ; - assign rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d84 = + (rxBaudCnt_2_ULT_clkDiv___d38 ? rxBaudCnt + 16'd1 : 16'd1) ; + assign rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34 = rxBaudCnt == clkDiv >> 1 ; + assign rxBaudCnt_2_ULT_clkDiv___d38 = rxBaudCnt < clkDiv ; + assign rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d42 = rxBitCnt == 4'd0 && rxD == 2'b10 || - rxBitCnt == 4'd10 && rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76 || + rxBitCnt == 4'd10 && rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34 || rxBaudCnt != 16'd0 || - !rxBaudCnt_4_ULT_clkDiv___d80 ; - assign rxBitCnt_9_EQ_0_0_AND_rxD_5_EQ_0b10_1_2_OR_rxB_ETC___d91 = + !rxBaudCnt_2_ULT_clkDiv___d38 ; + assign rxBitCnt_7_EQ_0_8_AND_rxD_3_EQ_0b10_9_0_OR_rxB_ETC___d49 = rxBitCnt == 4'd0 && rxD == 2'b10 || - rxBitCnt == 4'd10 && rxBaudCnt_4_EQ_clkDiv_SRL_1_5___d76 || + rxBitCnt == 4'd10 && rxBaudCnt_2_EQ_clkDiv_SRL_1_3___d34 || rxBaudCnt == clkDiv ; - always@(txBitCnt or txF_D_OUT) - begin - case (txBitCnt) - 4'd2: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[0]; - 4'd3: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[1]; - 4'd4: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[2]; - 4'd5: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[3]; - 4'd6: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[4]; - 4'd7: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[5]; - 4'd8: - CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = txF_D_OUT[6]; - default: CASE_txBitCnt_2_txFD_OUT_BIT_0_3_txFD_OUT_BI_ETC__q1 = - txF_D_OUT[7]; - endcase - end - always@(txBitCnt or txF_EMPTY_N) - begin - case (txBitCnt) - 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8: - CASE_txBitCnt_2_txFEMPTY_N_3_txFEMPTY_N_4_tx_ETC__q2 = txF_EMPTY_N; - default: CASE_txBitCnt_2_txFEMPTY_N_3_txFEMPTY_N_4_tx_ETC__q2 = - txBitCnt != 4'd9 || txF_EMPTY_N; - endcase - end + assign txa__h2921 = { txF_D_OUT, 2'b01 } ; // handling of inlined registers diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index d24df0e4..fc577ae8 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:40 EST 2014 +// On Mon Jan 27 11:00:21 EST 2014 // // // Ports: diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index 9a3f08e9..fdfbd22b 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:43 EST 2014 +// On Mon Jan 27 11:00:24 EST 2014 // // // Ports: diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index 900bcb20..d83b1955 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:41 EST 2014 +// On Mon Jan 27 11:00:22 EST 2014 // // // Ports: diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index 4b591a91..ddbc60aa 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:42 EST 2014 +// On Mon Jan 27 11:00:23 EST 2014 // // // Ports: diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v index 7d74653a..3dc2121a 100644 --- a/rtl/mkCTop16B.v +++ b/rtl/mkCTop16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 15:29:09 EST 2014 +// On Mon Jan 27 11:02:50 EST 2014 // // // Ports: diff --git a/rtl/mkDramServer_v6.v b/rtl/mkDramServer_v6.v index 48bf76dc..3b120dd9 100644 --- a/rtl/mkDramServer_v6.v +++ b/rtl/mkDramServer_v6.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:17 EST 2014 +// On Mon Jan 27 10:59:58 EST 2014 // // // Ports: diff --git a/rtl/mkFMC150.v b/rtl/mkFMC150.v index c6c2494b..0365bd60 100644 --- a/rtl/mkFMC150.v +++ b/rtl/mkFMC150.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:27 EST 2014 +// On Mon Jan 27 11:00:09 EST 2014 // // // Ports: diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v index 25e0b385..7728cb5b 100644 --- a/rtl/mkFTop_ml605.v +++ b/rtl/mkFTop_ml605.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 15:29:13 EST 2014 +// On Mon Jan 27 11:02:54 EST 2014 // // // Ports: @@ -2138,10 +2138,10 @@ module mkFTop_ml605(sys0_clkp, !pciw_i2pAF_sInReset_isInReset && ctop_RDY_server_response_get ; assign ctop_EN_cpServer_request_put = - ctop_RDY_cpServer_request_put && gbe0_RDY_cpClient_request_get ; + gbe0_RDY_cpClient_request_get && ctop_RDY_cpServer_request_put ; assign ctop_EN_cpServer_response_get = - ctop_RDY_cpServer_response_get && - gbe0_RDY_cpClient_response_put ; + gbe0_RDY_cpClient_response_put && + ctop_RDY_cpServer_response_get ; assign ctop_wci_m_0_SThreadBusy = fmc150_wciS0_SThreadBusy ; assign ctop_wci_m_1_SThreadBusy = flash0_wciS0_SThreadBusy ; assign ctop_wci_m_2_SThreadBusy = gbe0_wciS0_SThreadBusy ; @@ -2218,10 +2218,10 @@ module mkFTop_ml605(sys0_clkp, assign gbe0_wsiS0_MBurstPrecise = 1'b0 ; assign gbe0_wsiS0_MReset_n = 1'b0 ; assign gbe0_EN_cpClient_request_get = - ctop_RDY_cpServer_request_put && gbe0_RDY_cpClient_request_get ; + gbe0_RDY_cpClient_request_get && ctop_RDY_cpServer_request_put ; assign gbe0_EN_cpClient_response_put = - ctop_RDY_cpServer_response_get && - gbe0_RDY_cpClient_response_put ; + gbe0_RDY_cpClient_response_put && + ctop_RDY_cpServer_response_get ; // submodule lcd_ctrl assign lcd_ctrl_setLine1_text = 128'h202073656C75522063696D6F74412020 ; diff --git a/rtl/mkFlashController2416.v b/rtl/mkFlashController2416.v index ac41e078..007efe6f 100644 --- a/rtl/mkFlashController2416.v +++ b/rtl/mkFlashController2416.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:03 EST 2014 +// On Mon Jan 27 10:59:44 EST 2014 // // // Ports: diff --git a/rtl/mkFlashWorker.v b/rtl/mkFlashWorker.v index 94049552..83726325 100644 --- a/rtl/mkFlashWorker.v +++ b/rtl/mkFlashWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:22 EST 2014 +// On Mon Jan 27 11:00:03 EST 2014 // // // Ports: diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index 9b93b4c8..3271d4e5 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:20:59 EST 2014 +// On Mon Jan 27 10:59:40 EST 2014 // // // Ports: diff --git a/rtl/mkGbeWorker.v b/rtl/mkGbeWorker.v index a9d14aa0..1fdfeb4f 100644 --- a/rtl/mkGbeWorker.v +++ b/rtl/mkGbeWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:32 EST 2014 +// On Mon Jan 27 11:00:13 EST 2014 // // // Ports: diff --git a/rtl/mkICAPWorker.v b/rtl/mkICAPWorker.v index 25ff4590..22e2f9a1 100644 --- a/rtl/mkICAPWorker.v +++ b/rtl/mkICAPWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:24 EST 2014 +// On Mon Jan 27 11:00:05 EST 2014 // // // Ports: diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v index ca9b4823..2ca33e29 100644 --- a/rtl/mkMemiTestWorker.v +++ b/rtl/mkMemiTestWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:44 EST 2014 +// On Mon Jan 27 11:00:25 EST 2014 // // // Ports: diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v index c4d592e3..eadd3d32 100644 --- a/rtl/mkOCApp16B.v +++ b/rtl/mkOCApp16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:56 EST 2014 +// On Mon Jan 27 11:00:37 EST 2014 // // // Ports: diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index f5787f57..9c9d8bfe 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 15:28:47 EST 2014 +// On Mon Jan 27 11:02:15 EST 2014 // // // Ports: @@ -3308,8 +3308,11 @@ module mkOCCP(pciDevice, adminRespF_FULL_N; // ports of submodule bluart - wire [15 : 0] bluart_rxLevel, bluart_setClkDiv_put, bluart_txLevel; - wire [7 : 0] bluart_rxChar_get, bluart_txChar_put; + wire [15 : 0] bluart_setClkDiv_put; + wire [7 : 0] bluart_rxChar_get, + bluart_rxLevel, + bluart_txChar_put, + bluart_txLevel; wire bluart_EN_rxChar_get, bluart_EN_setClkDiv_put, bluart_EN_txChar_put, @@ -3943,21 +3946,21 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_9_wrkBusy; // inputs to muxes for submodule ports - reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, + reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, MUX_wci_10_reqF_q_0_write_1__VAL_1, MUX_wci_11_reqF_q_0_write_1__VAL_1, MUX_wci_12_reqF_q_0_write_1__VAL_1, MUX_wci_13_reqF_q_0_write_1__VAL_1, MUX_wci_14_reqF_q_0_write_1__VAL_1, - MUX_wci_1_reqF_q_0_write_1__VAL_1, - MUX_wci_2_reqF_q_0_write_1__VAL_1, - MUX_wci_3_reqF_q_0_write_1__VAL_1, - MUX_wci_4_reqF_q_0_write_1__VAL_1, - MUX_wci_5_reqF_q_0_write_1__VAL_1, - MUX_wci_6_reqF_q_0_write_1__VAL_1, - MUX_wci_7_reqF_q_0_write_1__VAL_1, - MUX_wci_8_reqF_q_0_write_1__VAL_1, - MUX_wci_9_reqF_q_0_write_1__VAL_1; + MUX_wci_1_reqF_q_0_write_1__VAL_2, + MUX_wci_2_reqF_q_0_write_1__VAL_2, + MUX_wci_3_reqF_q_0_write_1__VAL_2, + MUX_wci_4_reqF_q_0_write_1__VAL_2, + MUX_wci_5_reqF_q_0_write_1__VAL_2, + MUX_wci_6_reqF_q_0_write_1__VAL_2, + MUX_wci_7_reqF_q_0_write_1__VAL_2, + MUX_wci_8_reqF_q_0_write_1__VAL_2, + MUX_wci_9_reqF_q_0_write_1__VAL_2; reg [7 : 0] MUX_bluart_txChar_put_1__VAL_2; reg [2 : 0] MUX_wci_0_reqERR_write_1__VAL_1, MUX_wci_0_reqFAIL_write_1__VAL_1, @@ -4004,7 +4007,7 @@ module mkOCCP(pciDevice, MUX_wci_9_reqERR_write_1__VAL_1, MUX_wci_9_reqFAIL_write_1__VAL_1, MUX_wci_9_reqTO_write_1__VAL_1; - wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, + wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, MUX_wci_0_reqF_x_wire_wset_1__VAL_1, MUX_wci_0_reqF_x_wire_wset_1__VAL_2, MUX_wci_0_reqF_x_wire_wset_1__VAL_3, @@ -4023,31 +4026,31 @@ module mkOCCP(pciDevice, MUX_wci_14_reqF_q_0_write_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_3, - MUX_wci_1_reqF_q_0_write_1__VAL_2, + MUX_wci_1_reqF_q_0_write_1__VAL_1, MUX_wci_1_reqF_x_wire_wset_1__VAL_2, MUX_wci_1_reqF_x_wire_wset_1__VAL_3, - MUX_wci_2_reqF_q_0_write_1__VAL_2, + MUX_wci_2_reqF_q_0_write_1__VAL_1, MUX_wci_2_reqF_x_wire_wset_1__VAL_2, MUX_wci_2_reqF_x_wire_wset_1__VAL_3, - MUX_wci_3_reqF_q_0_write_1__VAL_2, + MUX_wci_3_reqF_q_0_write_1__VAL_1, MUX_wci_3_reqF_x_wire_wset_1__VAL_2, MUX_wci_3_reqF_x_wire_wset_1__VAL_3, - MUX_wci_4_reqF_q_0_write_1__VAL_2, + MUX_wci_4_reqF_q_0_write_1__VAL_1, MUX_wci_4_reqF_x_wire_wset_1__VAL_2, MUX_wci_4_reqF_x_wire_wset_1__VAL_3, - MUX_wci_5_reqF_q_0_write_1__VAL_2, + MUX_wci_5_reqF_q_0_write_1__VAL_1, MUX_wci_5_reqF_x_wire_wset_1__VAL_2, MUX_wci_5_reqF_x_wire_wset_1__VAL_3, - MUX_wci_6_reqF_q_0_write_1__VAL_2, + MUX_wci_6_reqF_q_0_write_1__VAL_1, MUX_wci_6_reqF_x_wire_wset_1__VAL_2, MUX_wci_6_reqF_x_wire_wset_1__VAL_3, - MUX_wci_7_reqF_q_0_write_1__VAL_2, + MUX_wci_7_reqF_q_0_write_1__VAL_1, MUX_wci_7_reqF_x_wire_wset_1__VAL_2, MUX_wci_7_reqF_x_wire_wset_1__VAL_3, - MUX_wci_8_reqF_q_0_write_1__VAL_2, + MUX_wci_8_reqF_q_0_write_1__VAL_1, MUX_wci_8_reqF_x_wire_wset_1__VAL_2, MUX_wci_8_reqF_x_wire_wset_1__VAL_3, - MUX_wci_9_reqF_q_0_write_1__VAL_2, + MUX_wci_9_reqF_q_0_write_1__VAL_1, MUX_wci_9_reqF_x_wire_wset_1__VAL_2, MUX_wci_9_reqF_x_wire_wset_1__VAL_3; wire [64 : 0] MUX_cpReq_write_1__VAL_4; @@ -4154,7 +4157,7 @@ module mkOCCP(pciDevice, MUX_wci_0_reqFAIL_write_1__SEL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_2, - MUX_wci_0_reqF_q_0_write_1__SEL_1, + MUX_wci_0_reqF_q_0_write_1__SEL_2, MUX_wci_0_reqPend_write_1__SEL_1, MUX_wci_0_reqTO_write_1__SEL_1, MUX_wci_0_respF_enq_1__SEL_6, @@ -4220,7 +4223,7 @@ module mkOCCP(pciDevice, MUX_wci_1_reqFAIL_write_1__SEL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_2, - MUX_wci_1_reqF_q_0_write_1__SEL_1, + MUX_wci_1_reqF_q_0_write_1__SEL_2, MUX_wci_1_reqPend_write_1__SEL_1, MUX_wci_1_reqTO_write_1__SEL_1, MUX_wci_1_respF_enq_1__SEL_6, @@ -4231,7 +4234,7 @@ module mkOCCP(pciDevice, MUX_wci_2_reqFAIL_write_1__SEL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_2, - MUX_wci_2_reqF_q_0_write_1__SEL_1, + MUX_wci_2_reqF_q_0_write_1__SEL_2, MUX_wci_2_reqPend_write_1__SEL_1, MUX_wci_2_reqTO_write_1__SEL_1, MUX_wci_2_respF_enq_1__SEL_6, @@ -4242,7 +4245,7 @@ module mkOCCP(pciDevice, MUX_wci_3_reqFAIL_write_1__SEL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_2, - MUX_wci_3_reqF_q_0_write_1__SEL_1, + MUX_wci_3_reqF_q_0_write_1__SEL_2, MUX_wci_3_reqPend_write_1__SEL_1, MUX_wci_3_reqTO_write_1__SEL_1, MUX_wci_3_respF_enq_1__SEL_6, @@ -4253,7 +4256,7 @@ module mkOCCP(pciDevice, MUX_wci_4_reqFAIL_write_1__SEL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_2, - MUX_wci_4_reqF_q_0_write_1__SEL_1, + MUX_wci_4_reqF_q_0_write_1__SEL_2, MUX_wci_4_reqPend_write_1__SEL_1, MUX_wci_4_reqTO_write_1__SEL_1, MUX_wci_4_respF_enq_1__SEL_6, @@ -4264,7 +4267,7 @@ module mkOCCP(pciDevice, MUX_wci_5_reqFAIL_write_1__SEL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_2, - MUX_wci_5_reqF_q_0_write_1__SEL_1, + MUX_wci_5_reqF_q_0_write_1__SEL_2, MUX_wci_5_reqPend_write_1__SEL_1, MUX_wci_5_reqTO_write_1__SEL_1, MUX_wci_5_respF_enq_1__SEL_6, @@ -4275,7 +4278,7 @@ module mkOCCP(pciDevice, MUX_wci_6_reqFAIL_write_1__SEL_1, MUX_wci_6_reqF_cntr_r_write_1__VAL_1, MUX_wci_6_reqF_cntr_r_write_1__VAL_2, - MUX_wci_6_reqF_q_0_write_1__SEL_1, + MUX_wci_6_reqF_q_0_write_1__SEL_2, MUX_wci_6_reqPend_write_1__SEL_1, MUX_wci_6_reqTO_write_1__SEL_1, MUX_wci_6_respF_enq_1__SEL_6, @@ -4286,7 +4289,7 @@ module mkOCCP(pciDevice, MUX_wci_7_reqFAIL_write_1__SEL_1, MUX_wci_7_reqF_cntr_r_write_1__VAL_1, MUX_wci_7_reqF_cntr_r_write_1__VAL_2, - MUX_wci_7_reqF_q_0_write_1__SEL_1, + MUX_wci_7_reqF_q_0_write_1__SEL_2, MUX_wci_7_reqPend_write_1__SEL_1, MUX_wci_7_reqTO_write_1__SEL_1, MUX_wci_7_respF_enq_1__SEL_6, @@ -4297,7 +4300,7 @@ module mkOCCP(pciDevice, MUX_wci_8_reqFAIL_write_1__SEL_1, MUX_wci_8_reqF_cntr_r_write_1__VAL_1, MUX_wci_8_reqF_cntr_r_write_1__VAL_2, - MUX_wci_8_reqF_q_0_write_1__SEL_1, + MUX_wci_8_reqF_q_0_write_1__SEL_2, MUX_wci_8_reqPend_write_1__SEL_1, MUX_wci_8_reqTO_write_1__SEL_1, MUX_wci_8_respF_enq_1__SEL_6, @@ -4308,7 +4311,7 @@ module mkOCCP(pciDevice, MUX_wci_9_reqFAIL_write_1__SEL_1, MUX_wci_9_reqF_cntr_r_write_1__VAL_1, MUX_wci_9_reqF_cntr_r_write_1__VAL_2, - MUX_wci_9_reqF_q_0_write_1__SEL_1, + MUX_wci_9_reqF_q_0_write_1__SEL_2, MUX_wci_9_reqPend_write_1__SEL_1, MUX_wci_9_reqTO_write_1__SEL_1, MUX_wci_9_respF_enq_1__SEL_6, @@ -8605,7 +8608,7 @@ module mkOCCP(pciDevice, wci_0_wciResponse_wget[33:32] == 2'd2 && (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || wci_0_reqPend == 2'd3) ; - assign MUX_wci_0_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_0_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r ; assign MUX_wci_0_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_0_wrkBusy && @@ -8833,7 +8836,7 @@ module mkOCCP(pciDevice, wci_1_wciResponse_wget[33:32] == 2'd2 && (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || wci_1_reqPend == 2'd3) ; - assign MUX_wci_1_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_1_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r ; assign MUX_wci_1_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_1_wrkBusy && @@ -8871,7 +8874,7 @@ module mkOCCP(pciDevice, wci_2_wciResponse_wget[33:32] == 2'd2 && (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || wci_2_reqPend == 2'd3) ; - assign MUX_wci_2_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_2_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r ; assign MUX_wci_2_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_2_wrkBusy && @@ -8909,7 +8912,7 @@ module mkOCCP(pciDevice, wci_3_wciResponse_wget[33:32] == 2'd2 && (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || wci_3_reqPend == 2'd3) ; - assign MUX_wci_3_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_3_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r ; assign MUX_wci_3_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_3_wrkBusy && @@ -8947,7 +8950,7 @@ module mkOCCP(pciDevice, wci_4_wciResponse_wget[33:32] == 2'd2 && (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || wci_4_reqPend == 2'd3) ; - assign MUX_wci_4_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_4_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r ; assign MUX_wci_4_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_4_wrkBusy && @@ -8985,7 +8988,7 @@ module mkOCCP(pciDevice, wci_5_wciResponse_wget[33:32] == 2'd2 && (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || wci_5_reqPend == 2'd3) ; - assign MUX_wci_5_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_5_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r ; assign MUX_wci_5_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_5_wrkBusy && @@ -9023,7 +9026,7 @@ module mkOCCP(pciDevice, wci_6_wciResponse_wget[33:32] == 2'd2 && (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || wci_6_reqPend == 2'd3) ; - assign MUX_wci_6_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_6_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r ; assign MUX_wci_6_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_6_wrkBusy && @@ -9061,7 +9064,7 @@ module mkOCCP(pciDevice, wci_7_wciResponse_wget[33:32] == 2'd2 && (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || wci_7_reqPend == 2'd3) ; - assign MUX_wci_7_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_7_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r ; assign MUX_wci_7_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_7_wrkBusy && @@ -9099,7 +9102,7 @@ module mkOCCP(pciDevice, wci_8_wciResponse_wget[33:32] == 2'd2 && (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || wci_8_reqPend == 2'd3) ; - assign MUX_wci_8_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_8_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r ; assign MUX_wci_8_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_8_wrkBusy && @@ -9137,7 +9140,7 @@ module mkOCCP(pciDevice, wci_9_wciResponse_wget[33:32] == 2'd2 && (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || wci_9_reqPend == 2'd3) ; - assign MUX_wci_9_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_9_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r ; assign MUX_wci_9_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_9_wrkBusy && @@ -9517,6 +9520,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_0_reqF_cntr_r_write_1__VAL_1 = wci_0_reqF_cntr_r + 1'd1 ; assign MUX_wci_0_reqF_cntr_r_write_1__VAL_2 = wci_0_reqF_cntr_r - 1'd1 ; + assign MUX_wci_0_reqF_q_0_write_1__VAL_1 = + wci_0_reqF_cntr_r ? + MUX_wci_0_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or @@ -9526,22 +9533,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_0_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_0_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_0_reqF_q_0_write_1__VAL_2 = - wci_0_reqF_cntr_r ? - MUX_wci_0_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_1 = { 8'd79, x_addr__h99156, 32'hAAAAAAAA } ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_2 = @@ -9980,6 +9983,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_1_reqF_cntr_r_write_1__VAL_1 = wci_1_reqF_cntr_r + 1'd1 ; assign MUX_wci_1_reqF_cntr_r_write_1__VAL_2 = wci_1_reqF_cntr_r - 1'd1 ; + assign MUX_wci_1_reqF_q_0_write_1__VAL_1 = + wci_1_reqF_cntr_r ? + MUX_wci_1_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or @@ -9989,22 +9996,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_1_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_1_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_1_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_1_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_1_reqF_q_0_write_1__VAL_2 = - wci_1_reqF_cntr_r ? - MUX_wci_1_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79655, cpReq[59:28] } ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_3 = @@ -10056,6 +10059,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_2_reqF_cntr_r_write_1__VAL_1 = wci_2_reqF_cntr_r + 1'd1 ; assign MUX_wci_2_reqF_cntr_r_write_1__VAL_2 = wci_2_reqF_cntr_r - 1'd1 ; + assign MUX_wci_2_reqF_q_0_write_1__VAL_1 = + wci_2_reqF_cntr_r ? + MUX_wci_2_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or @@ -10065,22 +10072,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_2_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_2_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_2_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_2_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_2_reqF_q_0_write_1__VAL_2 = - wci_2_reqF_cntr_r ? - MUX_wci_2_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79723, cpReq[59:28] } ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_3 = @@ -10132,6 +10135,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_3_reqF_cntr_r_write_1__VAL_1 = wci_3_reqF_cntr_r + 1'd1 ; assign MUX_wci_3_reqF_cntr_r_write_1__VAL_2 = wci_3_reqF_cntr_r - 1'd1 ; + assign MUX_wci_3_reqF_q_0_write_1__VAL_1 = + wci_3_reqF_cntr_r ? + MUX_wci_3_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or @@ -10141,22 +10148,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_3_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_3_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_3_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_3_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_3_reqF_q_0_write_1__VAL_2 = - wci_3_reqF_cntr_r ? - MUX_wci_3_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79791, cpReq[59:28] } ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_3 = @@ -10208,6 +10211,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_4_reqF_cntr_r_write_1__VAL_1 = wci_4_reqF_cntr_r + 1'd1 ; assign MUX_wci_4_reqF_cntr_r_write_1__VAL_2 = wci_4_reqF_cntr_r - 1'd1 ; + assign MUX_wci_4_reqF_q_0_write_1__VAL_1 = + wci_4_reqF_cntr_r ? + MUX_wci_4_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or @@ -10217,22 +10224,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_4_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_4_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_4_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_4_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_4_reqF_q_0_write_1__VAL_2 = - wci_4_reqF_cntr_r ? - MUX_wci_4_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79859, cpReq[59:28] } ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_3 = @@ -10284,6 +10287,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_5_reqF_cntr_r_write_1__VAL_1 = wci_5_reqF_cntr_r + 1'd1 ; assign MUX_wci_5_reqF_cntr_r_write_1__VAL_2 = wci_5_reqF_cntr_r - 1'd1 ; + assign MUX_wci_5_reqF_q_0_write_1__VAL_1 = + wci_5_reqF_cntr_r ? + MUX_wci_5_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or @@ -10293,22 +10300,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_5_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_5_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_5_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_5_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_5_reqF_q_0_write_1__VAL_2 = - wci_5_reqF_cntr_r ? - MUX_wci_5_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79927, cpReq[59:28] } ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_3 = @@ -10360,6 +10363,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_6_reqF_cntr_r_write_1__VAL_1 = wci_6_reqF_cntr_r + 1'd1 ; assign MUX_wci_6_reqF_cntr_r_write_1__VAL_2 = wci_6_reqF_cntr_r - 1'd1 ; + assign MUX_wci_6_reqF_q_0_write_1__VAL_1 = + wci_6_reqF_cntr_r ? + MUX_wci_6_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T or @@ -10369,22 +10376,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_1 = + MUX_wci_6_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_1 = + MUX_wci_6_reqF_q_0_write_1__VAL_2 = MUX_wci_6_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_1 = + MUX_wci_6_reqF_q_0_write_1__VAL_2 = MUX_wci_6_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_6_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_6_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_6_reqF_q_0_write_1__VAL_2 = - wci_6_reqF_cntr_r ? - MUX_wci_6_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_6_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h79995, cpReq[59:28] } ; assign MUX_wci_6_reqF_x_wire_wset_1__VAL_3 = @@ -10436,6 +10439,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_7_reqF_cntr_r_write_1__VAL_1 = wci_7_reqF_cntr_r + 1'd1 ; assign MUX_wci_7_reqF_cntr_r_write_1__VAL_2 = wci_7_reqF_cntr_r - 1'd1 ; + assign MUX_wci_7_reqF_q_0_write_1__VAL_1 = + wci_7_reqF_cntr_r ? + MUX_wci_7_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T or @@ -10445,22 +10452,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_1 = + MUX_wci_7_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_1 = + MUX_wci_7_reqF_q_0_write_1__VAL_2 = MUX_wci_7_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_1 = + MUX_wci_7_reqF_q_0_write_1__VAL_2 = MUX_wci_7_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_7_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_7_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_7_reqF_q_0_write_1__VAL_2 = - wci_7_reqF_cntr_r ? - MUX_wci_7_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_7_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h80063, cpReq[59:28] } ; assign MUX_wci_7_reqF_x_wire_wset_1__VAL_3 = @@ -10512,6 +10515,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_8_reqF_cntr_r_write_1__VAL_1 = wci_8_reqF_cntr_r + 1'd1 ; assign MUX_wci_8_reqF_cntr_r_write_1__VAL_2 = wci_8_reqF_cntr_r - 1'd1 ; + assign MUX_wci_8_reqF_q_0_write_1__VAL_1 = + wci_8_reqF_cntr_r ? + MUX_wci_8_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T or @@ -10521,22 +10528,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_1 = + MUX_wci_8_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_1 = + MUX_wci_8_reqF_q_0_write_1__VAL_2 = MUX_wci_8_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_1 = + MUX_wci_8_reqF_q_0_write_1__VAL_2 = MUX_wci_8_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_8_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_8_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_8_reqF_q_0_write_1__VAL_2 = - wci_8_reqF_cntr_r ? - MUX_wci_8_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_8_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h80131, cpReq[59:28] } ; assign MUX_wci_8_reqF_x_wire_wset_1__VAL_3 = @@ -10588,6 +10591,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_9_reqF_cntr_r_write_1__VAL_1 = wci_9_reqF_cntr_r + 1'd1 ; assign MUX_wci_9_reqF_cntr_r_write_1__VAL_2 = wci_9_reqF_cntr_r - 1'd1 ; + assign MUX_wci_9_reqF_q_0_write_1__VAL_1 = + wci_9_reqF_cntr_r ? + MUX_wci_9_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T or @@ -10597,22 +10604,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_1 = + MUX_wci_9_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_1 = + MUX_wci_9_reqF_q_0_write_1__VAL_2 = MUX_wci_9_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_1 = + MUX_wci_9_reqF_q_0_write_1__VAL_2 = MUX_wci_9_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_9_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_9_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_9_reqF_q_0_write_1__VAL_2 = - wci_9_reqF_cntr_r ? - MUX_wci_9_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_9_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h80199, cpReq[59:28] } ; assign MUX_wci_9_reqF_x_wire_wset_1__VAL_3 = @@ -10689,7 +10692,7 @@ module mkOCCP(pciDevice, assign dna_shftReg_1_whas = dna_cnt >= 7'd3 && dna_cnt <= 7'd116 ; assign uuidV_wget = uuid_arg ; assign uuidV_whas = 1'd1 ; - assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_1 ; + assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_2 ; assign wci_0_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || @@ -10702,7 +10705,7 @@ module mkOCCP(pciDevice, assign wci_0_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; - assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_1 ; + assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_2 ; assign wci_1_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || @@ -10715,7 +10718,7 @@ module mkOCCP(pciDevice, assign wci_1_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; - assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_1 ; + assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_2 ; assign wci_2_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || @@ -10728,7 +10731,7 @@ module mkOCCP(pciDevice, assign wci_2_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; - assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_1 ; + assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_2 ; assign wci_3_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || @@ -10741,7 +10744,7 @@ module mkOCCP(pciDevice, assign wci_3_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; - assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_1 ; + assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_2 ; assign wci_4_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || @@ -10754,7 +10757,7 @@ module mkOCCP(pciDevice, assign wci_4_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; - assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_1 ; + assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_2 ; assign wci_5_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || @@ -10767,7 +10770,7 @@ module mkOCCP(pciDevice, assign wci_5_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; - assign wci_6_reqF_x_wire_wget = MUX_wci_6_reqF_q_0_write_1__VAL_1 ; + assign wci_6_reqF_x_wire_wget = MUX_wci_6_reqF_q_0_write_1__VAL_2 ; assign wci_6_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || @@ -10780,7 +10783,7 @@ module mkOCCP(pciDevice, assign wci_6_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; - assign wci_7_reqF_x_wire_wget = MUX_wci_7_reqF_q_0_write_1__VAL_1 ; + assign wci_7_reqF_x_wire_wget = MUX_wci_7_reqF_q_0_write_1__VAL_2 ; assign wci_7_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || @@ -10793,7 +10796,7 @@ module mkOCCP(pciDevice, assign wci_7_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; - assign wci_8_reqF_x_wire_wget = MUX_wci_8_reqF_q_0_write_1__VAL_1 ; + assign wci_8_reqF_x_wire_wget = MUX_wci_8_reqF_q_0_write_1__VAL_2 ; assign wci_8_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || @@ -10806,7 +10809,7 @@ module mkOCCP(pciDevice, assign wci_8_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; - assign wci_9_reqF_x_wire_wget = MUX_wci_9_reqF_q_0_write_1__VAL_1 ; + assign wci_9_reqF_x_wire_wget = MUX_wci_9_reqF_q_0_write_1__VAL_2 ; assign wci_9_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || @@ -12316,15 +12319,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqF_q_0 - always@(MUX_wci_0_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_0_reqF_both or MUX_wci_0_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_0_reqF_both or + MUX_wci_0_reqF_q_0_write_1__SEL_2 or MUX_wci_0_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_0_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_0_reqF_q_0_write_1__SEL_1: - wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_0_reqF_both: + wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_1; + MUX_wci_0_reqF_q_0_write_1__SEL_2: wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_0_reqF_decCtr: wci_0_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -12333,8 +12336,8 @@ module mkOCCP(pciDevice, endcase end assign wci_0_reqF_q_0_EN = - WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || WILL_FIRE_RL_wci_0_reqF_both || + WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqPend @@ -13442,15 +13445,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqF_q_0 - always@(MUX_wci_1_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_1_reqF_both or MUX_wci_1_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_1_reqF_both or + MUX_wci_1_reqF_q_0_write_1__SEL_2 or MUX_wci_1_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_1_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_1_reqF_q_0_write_1__SEL_1: - wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_1_reqF_both: + wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_1; + MUX_wci_1_reqF_q_0_write_1__SEL_2: wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_1_reqF_decCtr: wci_1_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13459,8 +13462,8 @@ module mkOCCP(pciDevice, endcase end assign wci_1_reqF_q_0_EN = - WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || WILL_FIRE_RL_wci_1_reqF_both || + WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqPend @@ -13628,15 +13631,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqF_q_0 - always@(MUX_wci_2_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_2_reqF_both or MUX_wci_2_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_2_reqF_both or + MUX_wci_2_reqF_q_0_write_1__SEL_2 or MUX_wci_2_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_2_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_2_reqF_q_0_write_1__SEL_1: - wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_2_reqF_both: + wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_1; + MUX_wci_2_reqF_q_0_write_1__SEL_2: wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_2_reqF_decCtr: wci_2_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13645,8 +13648,8 @@ module mkOCCP(pciDevice, endcase end assign wci_2_reqF_q_0_EN = - WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || WILL_FIRE_RL_wci_2_reqF_both || + WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqPend @@ -13814,15 +13817,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqF_q_0 - always@(MUX_wci_3_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_3_reqF_both or MUX_wci_3_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_3_reqF_both or + MUX_wci_3_reqF_q_0_write_1__SEL_2 or MUX_wci_3_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_3_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_3_reqF_q_0_write_1__SEL_1: - wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_3_reqF_both: + wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_1; + MUX_wci_3_reqF_q_0_write_1__SEL_2: wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_3_reqF_decCtr: wci_3_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13831,8 +13834,8 @@ module mkOCCP(pciDevice, endcase end assign wci_3_reqF_q_0_EN = - WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || WILL_FIRE_RL_wci_3_reqF_both || + WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqPend @@ -14000,15 +14003,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqF_q_0 - always@(MUX_wci_4_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_4_reqF_both or MUX_wci_4_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_4_reqF_both or + MUX_wci_4_reqF_q_0_write_1__SEL_2 or MUX_wci_4_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_4_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_4_reqF_q_0_write_1__SEL_1: - wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_4_reqF_both: + wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_1; + MUX_wci_4_reqF_q_0_write_1__SEL_2: wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_4_reqF_decCtr: wci_4_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14017,8 +14020,8 @@ module mkOCCP(pciDevice, endcase end assign wci_4_reqF_q_0_EN = - WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || WILL_FIRE_RL_wci_4_reqF_both || + WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqPend @@ -14186,15 +14189,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqF_q_0 - always@(MUX_wci_5_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_5_reqF_both or MUX_wci_5_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_5_reqF_both or + MUX_wci_5_reqF_q_0_write_1__SEL_2 or MUX_wci_5_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_5_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_5_reqF_q_0_write_1__SEL_1: - wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_5_reqF_both: + wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_1; + MUX_wci_5_reqF_q_0_write_1__SEL_2: wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_5_reqF_decCtr: wci_5_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14203,8 +14206,8 @@ module mkOCCP(pciDevice, endcase end assign wci_5_reqF_q_0_EN = - WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || WILL_FIRE_RL_wci_5_reqF_both || + WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqPend @@ -14372,15 +14375,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_6_reqF_decCtr ; // register wci_6_reqF_q_0 - always@(MUX_wci_6_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_6_reqF_both or MUX_wci_6_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_6_reqF_both or + MUX_wci_6_reqF_q_0_write_1__SEL_2 or MUX_wci_6_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_6_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_6_reqF_q_0_write_1__SEL_1: - wci_6_reqF_q_0_D_IN = MUX_wci_6_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_6_reqF_both: + wci_6_reqF_q_0_D_IN = MUX_wci_6_reqF_q_0_write_1__VAL_1; + MUX_wci_6_reqF_q_0_write_1__SEL_2: wci_6_reqF_q_0_D_IN = MUX_wci_6_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_6_reqF_decCtr: wci_6_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14389,8 +14392,8 @@ module mkOCCP(pciDevice, endcase end assign wci_6_reqF_q_0_EN = - WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r || WILL_FIRE_RL_wci_6_reqF_both || + WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r || WILL_FIRE_RL_wci_6_reqF_decCtr ; // register wci_6_reqPend @@ -14558,15 +14561,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_7_reqF_decCtr ; // register wci_7_reqF_q_0 - always@(MUX_wci_7_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_7_reqF_both or MUX_wci_7_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_7_reqF_both or + MUX_wci_7_reqF_q_0_write_1__SEL_2 or MUX_wci_7_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_7_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_7_reqF_q_0_write_1__SEL_1: - wci_7_reqF_q_0_D_IN = MUX_wci_7_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_7_reqF_both: + wci_7_reqF_q_0_D_IN = MUX_wci_7_reqF_q_0_write_1__VAL_1; + MUX_wci_7_reqF_q_0_write_1__SEL_2: wci_7_reqF_q_0_D_IN = MUX_wci_7_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_7_reqF_decCtr: wci_7_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14575,8 +14578,8 @@ module mkOCCP(pciDevice, endcase end assign wci_7_reqF_q_0_EN = - WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r || WILL_FIRE_RL_wci_7_reqF_both || + WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r || WILL_FIRE_RL_wci_7_reqF_decCtr ; // register wci_7_reqPend @@ -14744,15 +14747,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_8_reqF_decCtr ; // register wci_8_reqF_q_0 - always@(MUX_wci_8_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_8_reqF_both or MUX_wci_8_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_8_reqF_both or + MUX_wci_8_reqF_q_0_write_1__SEL_2 or MUX_wci_8_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_8_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_8_reqF_q_0_write_1__SEL_1: - wci_8_reqF_q_0_D_IN = MUX_wci_8_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_8_reqF_both: + wci_8_reqF_q_0_D_IN = MUX_wci_8_reqF_q_0_write_1__VAL_1; + MUX_wci_8_reqF_q_0_write_1__SEL_2: wci_8_reqF_q_0_D_IN = MUX_wci_8_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_8_reqF_decCtr: wci_8_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14761,8 +14764,8 @@ module mkOCCP(pciDevice, endcase end assign wci_8_reqF_q_0_EN = - WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r || WILL_FIRE_RL_wci_8_reqF_both || + WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r || WILL_FIRE_RL_wci_8_reqF_decCtr ; // register wci_8_reqPend @@ -14930,15 +14933,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_9_reqF_decCtr ; // register wci_9_reqF_q_0 - always@(MUX_wci_9_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_9_reqF_both or MUX_wci_9_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_9_reqF_both or + MUX_wci_9_reqF_q_0_write_1__SEL_2 or MUX_wci_9_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_9_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_9_reqF_q_0_write_1__SEL_1: - wci_9_reqF_q_0_D_IN = MUX_wci_9_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_9_reqF_both: + wci_9_reqF_q_0_D_IN = MUX_wci_9_reqF_q_0_write_1__VAL_1; + MUX_wci_9_reqF_q_0_write_1__SEL_2: wci_9_reqF_q_0_D_IN = MUX_wci_9_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_9_reqF_decCtr: wci_9_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14947,8 +14950,8 @@ module mkOCCP(pciDevice, endcase end assign wci_9_reqF_q_0_EN = - WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r || WILL_FIRE_RL_wci_9_reqF_both || + WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r || WILL_FIRE_RL_wci_9_reqF_decCtr ; // register wci_9_reqPend @@ -17869,7 +17872,7 @@ module mkOCCP(pciDevice, case (x__h9243) 6'd0: put__h9199 = 8'd79; 6'd1: put__h9199 = 8'd112; - 6'd2: put__h9199 = 8'd101; + 6'd2, 6'd38: put__h9199 = 8'd101; 6'd3: put__h9199 = 8'd110; 6'd4: put__h9199 = 8'd67; 6'd5: put__h9199 = 8'd80; @@ -17887,12 +17890,11 @@ module mkOCCP(pciDevice, 6'd19: put__h9199 = 8'd46; 6'd21, 6'd25, 6'd29: put__h9199 = 8'd49; 6'd23, 6'd31: put__h9199 = 8'd50; - 6'd26: put__h9199 = 8'd52; - 6'd32: put__h9199 = 8'd54; + 6'd26, 6'd32: put__h9199 = 8'd52; 6'd34, 6'd39: put__h9199 = 8'd42; - 6'd35: put__h9199 = 8'd103; - 6'd36, 6'd37: put__h9199 = 8'd111; - 6'd38: put__h9199 = 8'd100; + 6'd35: put__h9199 = 8'd115; + 6'd36: put__h9199 = 8'd97; + 6'd37: put__h9199 = 8'd102; default: put__h9199 = 8'b10101010 /* unspecified value */ ; endcase end @@ -24581,7 +24583,7 @@ module mkOCCP(pciDevice, 32'h00000001; 8'h0C: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = - 32'd1390768038; + 32'd1390838362; 8'h10: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = { 17'd0, x__h106938 }; @@ -24663,10 +24665,10 @@ module mkOCCP(pciDevice, devDNAV_wget[63:32]; 8'h60: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = - { 16'd0, bluart_txLevel }; + { 24'd0, bluart_txLevel }; 8'h64: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = - { 16'd0, bluart_rxLevel }; + { 24'd0, bluart_rxLevel }; 8'h68: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = { 24'd0, bluart_rxChar_get }; diff --git a/rtl/mkOCDP16B.v b/rtl/mkOCDP16B.v index 7f744243..fea9b946 100644 --- a/rtl/mkOCDP16B.v +++ b/rtl/mkOCDP16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:28:04 EST 2014 +// On Mon Jan 27 11:02:41 EST 2014 // // // Ports: @@ -1594,6 +1594,7 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq, WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq, @@ -2380,6 +2381,11 @@ module mkOCDP16B(pciDevice, .FULL_N(wmi_wmi_reqF_FULL_N), .EMPTY_N(wmi_wmi_reqF_EMPTY_N)); + // rule RL_bram_2_serverAdapterA_outData_setFirstEnq + assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq = + !bram_2_serverAdapterA_outDataCore_EMPTY_N && + bram_2_serverAdapterA_outData_enqData_whas ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N && @@ -2797,7 +2803,7 @@ module mkOCDP16B(pciDevice, // rule RL_wci_respF_incCtr assign WILL_FIRE_RL_wci_respF_incCtr = - wci_respF_x_wire_whas && wci_respF_enqueueing_whas && + wci_respF_enqueueing_whas && wci_respF_enqueueing_whas && !(wci_respF_cntr_r != 2'd0) ; // rule RL_wci_respF_decCtr @@ -2806,7 +2812,7 @@ module mkOCDP16B(pciDevice, // rule RL_wci_respF_both assign WILL_FIRE_RL_wci_respF_both = - wci_respF_x_wire_whas && wci_respF_cntr_r != 2'd0 && + wci_respF_enqueueing_whas && wci_respF_cntr_r != 2'd0 && wci_respF_enqueueing_whas ; // rule RL_wmi_wmi_reqF_reset @@ -3665,13 +3671,12 @@ module mkOCDP16B(pciDevice, bram_2_serverAdapterA_s1[1] && bram_2_serverAdapterA_s1[0] ; assign bram_2_serverAdapterA_outData_outData_wget = - bram_2_serverAdapterA_outDataCore_EMPTY_N ? - bram_2_serverAdapterA_outDataCore_D_OUT : - bram_2_memory_DOA ; + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ? + bram_2_memory_DOA : + bram_2_serverAdapterA_outDataCore_D_OUT ; assign bram_2_serverAdapterA_outData_outData_whas = - bram_2_serverAdapterA_outDataCore_EMPTY_N || - !bram_2_serverAdapterA_outDataCore_EMPTY_N && - bram_2_serverAdapterA_outData_enqData_whas ; + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq || + bram_2_serverAdapterA_outDataCore_EMPTY_N ; assign bram_2_serverAdapterA_cnt_1_wget = 3'd1 ; assign bram_2_serverAdapterA_cnt_1_whas = (MUX_bram_2_memory_a_put_1__SEL_1 || @@ -3802,9 +3807,7 @@ module mkOCDP16B(pciDevice, wci_s_MData } ; assign wci_wciReq_whas = 1'd1 ; assign wci_respF_x_wire_wget = MUX_wci_respF_q_0_write_1__VAL_2 ; - assign wci_respF_x_wire_whas = - WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || - WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_x_wire_whas = wci_respF_enqueueing_whas ; assign wci_wEdge_wget = wci_reqF_D_OUT[36:34] ; assign wci_wEdge_whas = WILL_FIRE_RL_wci_ctl_op_start ; assign wci_sFlagReg_1_wget = 1'b0 ; @@ -3976,12 +3979,12 @@ module mkOCDP16B(pciDevice, bram_0_serverAdapterB_outData_deqCalled_whas ; assign wci_reqF_r_enq_whas = wci_wciReq_wget[71:69] != 3'd0 ; assign wci_reqF_r_deq_whas = - WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || - WILL_FIRE_RL_wci_ctl_op_start ; + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; assign wci_reqF_r_clr_whas = 1'b0 ; assign wci_respF_enqueueing_whas = - WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || - WILL_FIRE_RL_wci_ctl_op_complete ; + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; assign wci_respF_dequeueing_whas = wci_respF_cntr_r != 2'd0 ; assign wci_sThreadBusy_pw_whas = 1'b0 ; assign wci_wci_cfwr_pw_whas = diff --git a/rtl/mkOCInf16B.v b/rtl/mkOCInf16B.v index 21329d75..b03cc3d4 100644 --- a/rtl/mkOCInf16B.v +++ b/rtl/mkOCInf16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 15:29:04 EST 2014 +// On Mon Jan 27 11:02:46 EST 2014 // // // Ports: @@ -2699,9 +2699,9 @@ module mkOCInf16B(pciDevice, assign cpTlp_client_response_put = cpMux_respAF_D_OUT ; assign cpTlp_server_request_put = noc_sm0_c0_request_get ; assign cpTlp_EN_server_request_put = - noc_sm0_RDY_c0_request_get && cpTlp_RDY_server_request_put ; + cpTlp_RDY_server_request_put && noc_sm0_RDY_c0_request_get ; assign cpTlp_EN_server_response_get = - noc_sm0_RDY_c0_response_put && cpTlp_RDY_server_response_get ; + cpTlp_RDY_server_response_get && noc_sm0_RDY_c0_response_put ; assign cpTlp_EN_client_request_get = cpTlp_RDY_client_request_get && cpMux_reqAF_FULL_N ; assign cpTlp_EN_client_response_put = @@ -2729,9 +2729,9 @@ module mkOCInf16B(pciDevice, assign dp0_wmiS0_MDataLast = wmiDP0_MDataLast ; assign dp0_wmiS0_MReset_n = wmiDP0_MReset_n ; assign dp0_EN_server_request_put = - noc_sm1_RDY_c0_request_get && dp0_RDY_server_request_put ; + dp0_RDY_server_request_put && noc_sm1_RDY_c0_request_get ; assign dp0_EN_server_response_get = - noc_sm1_RDY_c0_response_put && dp0_RDY_server_response_get ; + dp0_RDY_server_response_get && noc_sm1_RDY_c0_response_put ; // submodule dp1 assign dp1_server_request_put = noc_sm2_c0_request_get ; @@ -2755,9 +2755,9 @@ module mkOCInf16B(pciDevice, assign dp1_wmiS0_MDataLast = wmiDP1_MDataLast ; assign dp1_wmiS0_MReset_n = wmiDP1_MReset_n ; assign dp1_EN_server_request_put = - noc_sm2_RDY_c0_request_get && dp1_RDY_server_request_put ; + dp1_RDY_server_request_put && noc_sm2_RDY_c0_request_get ; assign dp1_EN_server_response_get = - noc_sm2_RDY_c0_response_put && dp1_RDY_server_response_get ; + dp1_RDY_server_response_get && noc_sm2_RDY_c0_response_put ; // submodule itc0 assign itc0_gpsTime_arg = cp_cpNow ; @@ -2778,43 +2778,43 @@ module mkOCInf16B(pciDevice, assign noc_sm0_EN_s_request_put = EN_server_request_put ; assign noc_sm0_EN_s_response_get = EN_server_response_get ; assign noc_sm0_EN_c0_request_get = - noc_sm0_RDY_c0_request_get && cpTlp_RDY_server_request_put ; + cpTlp_RDY_server_request_put && noc_sm0_RDY_c0_request_get ; assign noc_sm0_EN_c0_response_put = - noc_sm0_RDY_c0_response_put && cpTlp_RDY_server_response_get ; + cpTlp_RDY_server_response_get && noc_sm0_RDY_c0_response_put ; assign noc_sm0_EN_c1_request_get = - noc_sm1_RDY_s_request_put && noc_sm0_RDY_c1_request_get ; + noc_sm0_RDY_c1_request_get && noc_sm1_RDY_s_request_put ; assign noc_sm0_EN_c1_response_put = - noc_sm1_RDY_s_response_get && noc_sm0_RDY_c1_response_put ; + noc_sm0_RDY_c1_response_put && noc_sm1_RDY_s_response_get ; // submodule noc_sm1 assign noc_sm1_c0_response_put = dp0_server_response_get ; assign noc_sm1_c1_response_put = noc_sm2_s_response_get ; assign noc_sm1_s_request_put = noc_sm0_c1_request_get ; assign noc_sm1_EN_s_request_put = - noc_sm1_RDY_s_request_put && noc_sm0_RDY_c1_request_get ; + noc_sm0_RDY_c1_request_get && noc_sm1_RDY_s_request_put ; assign noc_sm1_EN_s_response_get = - noc_sm1_RDY_s_response_get && noc_sm0_RDY_c1_response_put ; + noc_sm0_RDY_c1_response_put && noc_sm1_RDY_s_response_get ; assign noc_sm1_EN_c0_request_get = - noc_sm1_RDY_c0_request_get && dp0_RDY_server_request_put ; + dp0_RDY_server_request_put && noc_sm1_RDY_c0_request_get ; assign noc_sm1_EN_c0_response_put = - noc_sm1_RDY_c0_response_put && dp0_RDY_server_response_get ; + dp0_RDY_server_response_get && noc_sm1_RDY_c0_response_put ; assign noc_sm1_EN_c1_request_get = - noc_sm2_RDY_s_request_put && noc_sm1_RDY_c1_request_get ; + noc_sm1_RDY_c1_request_get && noc_sm2_RDY_s_request_put ; assign noc_sm1_EN_c1_response_put = - noc_sm2_RDY_s_response_get && noc_sm1_RDY_c1_response_put ; + noc_sm1_RDY_c1_response_put && noc_sm2_RDY_s_response_get ; // submodule noc_sm2 assign noc_sm2_c0_response_put = dp1_server_response_get ; assign noc_sm2_c1_response_put = 153'h0 ; assign noc_sm2_s_request_put = noc_sm1_c1_request_get ; assign noc_sm2_EN_s_request_put = - noc_sm2_RDY_s_request_put && noc_sm1_RDY_c1_request_get ; + noc_sm1_RDY_c1_request_get && noc_sm2_RDY_s_request_put ; assign noc_sm2_EN_s_response_get = - noc_sm2_RDY_s_response_get && noc_sm1_RDY_c1_response_put ; + noc_sm1_RDY_c1_response_put && noc_sm2_RDY_s_response_get ; assign noc_sm2_EN_c0_request_get = - noc_sm2_RDY_c0_request_get && dp1_RDY_server_request_put ; + dp1_RDY_server_request_put && noc_sm2_RDY_c0_request_get ; assign noc_sm2_EN_c0_response_put = - noc_sm2_RDY_c0_response_put && dp1_RDY_server_response_get ; + dp1_RDY_server_response_get && noc_sm2_RDY_c0_response_put ; assign noc_sm2_EN_c1_request_get = noc_sm2_RDY_c1_request_get ; assign noc_sm2_EN_c1_response_put = 1'b0 ; diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index aaea5bcf..b6a7eda9 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index 1449b711..c42c1584 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index 3e055f59..499be5a7 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:20:56 EST 2014 +// On Mon Jan 27 10:59:37 EST 2014 // // // Ports: diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index a66beac7..171db45b 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:20:57 EST 2014 +// On Mon Jan 27 10:59:38 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index 62c389cc..b22972e7 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:47 EST 2014 +// On Mon Jan 27 11:00:28 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index 91b0cfb1..7ad22860 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:52 EST 2014 +// On Mon Jan 27 11:00:34 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index 844871c4..f5a6e353 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:49 EST 2014 +// On Mon Jan 27 11:00:30 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index 319ec776..4bd05a26 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:51 EST 2014 +// On Mon Jan 27 11:00:32 EST 2014 // // // Ports: diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index 65886371..daff14c2 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index 10cd547c..adafefab 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index c0cdcafc..85984787 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSerializer.v b/rtl/mkTLPSerializer.v index 94f434cc..64ff6ee9 100644 --- a/rtl/mkTLPSerializer.v +++ b/rtl/mkTLPSerializer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:27:55 EST 2014 +// On Mon Jan 27 11:02:32 EST 2014 // // // Ports: diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index 5f26d646..adf868cc 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:22:09 EST 2014 +// On Mon Jan 27 11:00:50 EST 2014 // // // Ports: diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index fd6c9d2b..17989480 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:25 EST 2014 +// On Mon Jan 27 11:00:07 EST 2014 // // // Ports: diff --git a/rtl/mkUUID.v b/rtl/mkUUID.v index 952c63e2..1cc25873 100644 --- a/rtl/mkUUID.v +++ b/rtl/mkUUID.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:05 EST 2014 +// On Mon Jan 27 10:59:47 EST 2014 // // // Ports: diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index e5c3ec07..c3dc4a1d 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:35 EST 2014 +// On Mon Jan 27 11:00:16 EST 2014 // // // Ports: diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index fe593b6e..dda652a5 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:10 EST 2014 +// On Mon Jan 27 10:59:51 EST 2014 // // // Ports: diff --git a/rtl/mkWciMonitor.v b/rtl/mkWciMonitor.v index a641241c..d43f8d34 100644 --- a/rtl/mkWciMonitor.v +++ b/rtl/mkWciMonitor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:12 EST 2014 +// On Mon Jan 27 10:59:53 EST 2014 // // // Ports: diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index 1b8a6c28..09486427 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:11 EST 2014 +// On Mon Jan 27 10:59:52 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter16B4B.v b/rtl/mkWsiAdapter16B4B.v index 5f211ee4..3fa3eb0c 100644 --- a/rtl/mkWsiAdapter16B4B.v +++ b/rtl/mkWsiAdapter16B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:38 EST 2014 +// On Mon Jan 27 11:00:19 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter32B4B.v b/rtl/mkWsiAdapter32B4B.v index 2c4adafc..c8fbf9d4 100644 --- a/rtl/mkWsiAdapter32B4B.v +++ b/rtl/mkWsiAdapter32B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:39 EST 2014 +// On Mon Jan 27 11:00:20 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B16B.v b/rtl/mkWsiAdapter4B16B.v index 237b2a22..8aff7fbd 100644 --- a/rtl/mkWsiAdapter4B16B.v +++ b/rtl/mkWsiAdapter4B16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:37 EST 2014 +// On Mon Jan 27 11:00:19 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B32B.v b/rtl/mkWsiAdapter4B32B.v index 4f976c5f..e38f5d5f 100644 --- a/rtl/mkWsiAdapter4B32B.v +++ b/rtl/mkWsiAdapter4B32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Sun Jan 26 14:21:38 EST 2014 +// On Mon Jan 27 11:00:19 EST 2014 // // // Ports: From 574eb6806e674cb647f1544e0daffafdc9b6e099 Mon Sep 17 00:00:00 2001 From: Shepard Siegel Date: Thu, 30 Jan 2014 15:36:27 -0500 Subject: [PATCH 2/3] BUILD BROKEN while working on WmemiTap --- bsv/inf/CTop.bsv | 6 +- bsv/inf/OCCP.bsv | 48 +- bsv/inf/OCInf.bsv | 6 +- bsv/inf/WmemiTap.bsv | 89 + bsv/top/FTop_ml605.bsv | 6 +- bsv/utl/CompileTime.bsv | 2 +- rtl/mkBLUART.v | 2 +- rtl/mkBiasWorker16B.v | 57 +- rtl/mkBiasWorker32B.v | 57 +- rtl/mkBiasWorker4B.v | 57 +- rtl/mkBiasWorker8B.v | 57 +- rtl/mkCTop16B.v | 44 +- rtl/mkDramServer_v6.v | 2 +- rtl/mkFMC150.v | 2 +- rtl/mkFlashController2416.v | 2 +- rtl/mkFlashWorker.v | 2 +- rtl/mkGMAC.v | 2 +- rtl/mkGbeWorker.v | 2 +- rtl/mkICAPWorker.v | 2 +- rtl/mkMemiTestWorker.v | 80 +- rtl/mkOCApp16B.v | 2 +- rtl/mkOCCP.v | 15744 +++++++++++++++++----------------- rtl/mkOCDP16B.v | 19 +- rtl/mkOCInf16B.v | 100 +- rtl/mkPktFork.v | 2 +- rtl/mkPktMerge.v | 2 +- rtl/mkQABSMF.v | 2 +- rtl/mkQABSMF3.v | 2 +- rtl/mkSMAdapter16B.v | 82 +- rtl/mkSMAdapter32B.v | 72 +- rtl/mkSMAdapter4B.v | 72 +- rtl/mkSMAdapter8B.v | 82 +- rtl/mkTLPCM.v | 2 +- rtl/mkTLPClientNode.v | 2 +- rtl/mkTLPSM.v | 2 +- rtl/mkTLPSerializer.v | 2 +- rtl/mkTLPServerNode.v | 2 +- rtl/mkTimeClient.v | 2 +- rtl/mkUUID.v | 2 +- rtl/mkWSICaptureWorker4B.v | 2 +- rtl/mkWciInitiator.v | 2 +- rtl/mkWciMonitor.v | 2 +- rtl/mkWciTarget.v | 2 +- rtl/mkWmemiTap.v | 1916 +++++ rtl/mkWsiAdapter16B4B.v | 2 +- rtl/mkWsiAdapter32B4B.v | 2 +- rtl/mkWsiAdapter4B16B.v | 2 +- rtl/mkWsiAdapter4B32B.v | 2 +- 48 files changed, 10154 insertions(+), 8498 deletions(-) create mode 100644 bsv/inf/WmemiTap.bsv create mode 100644 rtl/mkWmemiTap.v diff --git a/bsv/inf/CTop.bsv b/bsv/inf/CTop.bsv index d0da2fac..d4593fc1 100644 --- a/bsv/inf/CTop.bsv +++ b/bsv/inf/CTop.bsv @@ -3,7 +3,7 @@ package CTop; -import BLUART ::*; +//import BLUART ::*; import OCInf ::*; import OCApp ::*; import TLPMF ::*; @@ -33,7 +33,7 @@ interface CTopIfc#(numeric type ndw); interface Wsi_Em#(12,TMul#(ndw,32),TMul#(ndw,4),8,0) wsi_m_dac; interface WmemiEM16B wmemiM0; interface GPSIfc gps; - interface UART_pads upads; +// interface UART_pads upads; endinterface module mkCTop#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (CTopIfc#(ndw)) @@ -130,7 +130,7 @@ module mkCTop#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (CTopIfc#(ndw)) //interface Wsi_s wsi_s_adc = app.wsi_s_adc; // The ADC device-worker to the application // FIXME Poly Width //interface Wsi_m wsi_m_dac = app.wsi_m_dac; // The DAC device-worker to the application // FIXME Poly Width interface WmemiEM16B wmemiM0 = app.wmemiM0; - interface UART_pads upads = inf.upads; +// interface UART_pads upads = inf.upads; endmodule : mkCTop // Synthesizeable, non-polymorphic modules that use the poly module above... diff --git a/bsv/inf/OCCP.bsv b/bsv/inf/OCCP.bsv index 8a723c18..e1a1dacf 100644 --- a/bsv/inf/OCCP.bsv +++ b/bsv/inf/OCCP.bsv @@ -3,7 +3,7 @@ package OCCP; -import BLUART ::*; +//import BLUART ::*; import CPDefs ::*; import OCWip ::*; import TimeService ::*; @@ -48,7 +48,7 @@ interface OCCPIfc#(numeric type nWci); (* always_ready *) method Bit#(2) led; (* always_ready, always_enabled *) method Action switch (Bit#(3) x); (* always_ready, always_enabled *) method Action uuid (Bit#(512) arg); - interface UART_pads upads; + // interface UART_pads upads; endinterface typedef union tagged { @@ -98,9 +98,9 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) FIFOF#(DWordM) adminResp4F <- mkFIFOF1; // Admin region read-response FIFO - region 4 FIFO#(DWordM) adminRespF <- mkFIFO1; // Admin region read-response FIFO - aggregate - BLUARTIfc bluart <- mkBLUART; // Instance our tiny UART - Reg#(Bool) uartInited <- mkReg(False); - Reg#(UInt#(6)) uartTxtP <- mkReg(0); + //BLUARTIfc bluart <- mkBLUART; // Instance our tiny UART + //Reg#(Bool) uartInited <- mkReg(False); + //Reg#(UInt#(6)) uartTxtP <- mkReg(0); BRAM_Configure cfg = defaultValue; cfg.memorySize = 1024; // Number of DWORD entries in 4KB ROM @@ -133,16 +133,16 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) return text; endfunction - rule init_uart_text (!uartInited); - Vector#(40,Bit#(8)) initText = uartLine("OpenCPI USB-UART v0.01 2014-01-24 *safe*"); - case (uartTxtP) - 0,42 : bluart.txChar.put(8'h0d); // CR - 1,43 : bluart.txChar.put(8'h0a); // LF - default: bluart.txChar.put(initText[uartTxtP-2]); - endcase - uartTxtP <= uartTxtP + 1; - if (uartTxtP==43) uartInited <= True; - endrule +// rule init_uart_text (!uartInited); +// Vector#(40,Bit#(8)) initText = uartLine("OpenCPI USB-UART v0.01 2014-01-24 *safe*"); +// case (uartTxtP) +// 0,42 : bluart.txChar.put(8'h0d); // CR +// 1,43 : bluart.txChar.put(8'h0a); // LF +// default: bluart.txChar.put(initText[uartTxtP-2]); +// endcase +// uartTxtP <= uartTxtP + 1; +// if (uartTxtP==43) uartInited <= True; +// endrule function makeWciMaster (Integer i); //return (i<5||i>12) ? mkWciMaster : mkWciMasterNull; // only instance the 7 (0:4,13:14) we need @@ -187,8 +187,8 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) 'h4C : readCntReg <= unpack(wd); - 'h6C : bluart.setClkDiv.put(truncate(unpack(wd))); - 'h70 : bluart.txChar.put(truncate(unpack(wd))); + // 'h6C : bluart.setClkDiv.put(truncate(unpack(wd))); + // 'h70 : bluart.txChar.put(truncate(unpack(wd))); endcase cpReq <= tagged Idle; @@ -248,12 +248,12 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) 'h50 : rv = Valid(pack(devDNAV[0])); // LSBs of devDNA 'h54 : rv = Valid(pack(devDNAV[1])); // MSBs of devDNA - 'h60 : rv = Valid(extend(pack(bluart.txLevel))); - 'h64 : rv = Valid(extend(pack(bluart.rxLevel))); - 'h68 : action - let d <- bluart.rxChar.get(); - rv = Valid(extend(unpack(d))); - endaction +// 'h60 : rv = Valid(extend(pack(bluart.txLevel))); +// 'h64 : rv = Valid(extend(pack(bluart.rxLevel))); +// 'h68 : action +// let d <- bluart.rxChar.get(); +// rv = Valid(extend(unpack(d))); +// endaction 'h7C : rv = Valid(32'd2); // DP Mem Region Descriptors... 'h80 : rv = Valid(pack(dpMemRegion0)); @@ -389,7 +389,7 @@ module mkOCCP#(PciId pciDevice, Clock time_clk, Reset time_rst) (OCCPIfc#(Nwcit) method led = scratch24[1:0]; method Action switch (Bit#(3) x); switch_d <= x; endmethod method Action uuid (Bit#(512) arg); uuidV <= unpack(arg); endmethod - interface UART_pads upads = bluart.pads; +// interface UART_pads upads = bluart.pads; endmodule: mkOCCP endpackage: OCCP diff --git a/bsv/inf/OCInf.bsv b/bsv/inf/OCInf.bsv index f08c753a..342e976a 100644 --- a/bsv/inf/OCInf.bsv +++ b/bsv/inf/OCInf.bsv @@ -3,7 +3,7 @@ package OCInf; -import BLUART ::*; +//import BLUART ::*; import Config ::*; import OCWip ::*; import CPMux ::*; @@ -48,7 +48,7 @@ interface OCInfIfc#(numeric type nWci_ctop, numeric type ndw); method GPS64_t cpNow; interface GPSIfc gps; method Action uuid (Bit#(512) arg); - interface UART_pads upads; + // interface UART_pads upads; endinterface module mkOCInf_poly#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (OCInfIfc#(Nwci_ctop,ndw)) @@ -134,7 +134,7 @@ module mkOCInf_poly#(PciId pciDevice, Clock sys0_clk, Reset sys0_rst) (OCInfIfc# interface wmiDP0 = dp0.wmiS0; interface wmiDP1 = dp1.wmiS0; method Action uuid (Bit#(512) arg) = cp.uuid(arg); // Pass the UUID from the infrastrucrture down to the control plane - interface UART_pads upads = cp.upads; +// interface UART_pads upads = cp.upads; endmodule : mkOCInf_poly diff --git a/bsv/inf/WmemiTap.bsv b/bsv/inf/WmemiTap.bsv new file mode 100644 index 00000000..111dcdff --- /dev/null +++ b/bsv/inf/WmemiTap.bsv @@ -0,0 +1,89 @@ +// WmemiTap.bsv - A Wmemi Connector with an AXI4-MM-Lite tap +// Copyright (c) 2014 Atomic Rules LLC - ALL RIGHTS RESERVED + +package WmemiTap; + +import ARAXI4L ::*; +import OCWip ::*; + +import Connectable ::*; +import DReg ::*; +import FIFO ::*; +import GetPut ::*; +import Vector ::*; + +interface WmemiTapIfc; + interface WmemiES16B wmemiS0; // upstream WMemi Memory Slave Port + interface WmemiEM16B wmemiM0; // downstream WMemi Memory Master Port + interface A4LMIfc axiM0; // downstream AXI4-Lite Master Port +endinterface + +(* synthesize *) +module mkWmemiTap (WmemiTapIfc); + + WmemiSlaveIfc# (36,12,128,16) wmemiS <- mkWmemiSlave; // 2^36 = 64GB + WmemiMasterIfc#(36,12,128,16) wmemiM <- mkWmemiMaster; // 2^36 = 64GB + A4LMasterIfc a4l <- mkA4LMaster; // The AXI4-Lite Master Interface + Reg#(Bool) axiActive <- mkReg(False); // Used to block WMemi While Axi in flight + + rule operating_actions; + wmemiS.operate(); + wmemiM.operate(); + endrule + + function Bool isMemoryAddr(Bit#(36) a); + return !unpack(a[31]); //TODO; Make this function more interesting + endfunction + + rule advance_request (!axiActive); + let req <- wmemiS.req; + if (isMemoryAddr(req.addr)) begin + wmemiM.req((req.cmd==WR), req.addr, req.burstLength); // TODO: Go back and make WmemiMaster take WmemiReq + if (req.cmd==WR) begin + let dh <- wmemiS.dh; + wmemiM.dh(dh.data, dh.dataByteEn, dh.dataLast); + end + end else begin + axiActive <= True; + if (req.cmd==WR) begin + let dh <- wmemiS.dh; + a4l.f.wrAddr.enq(A4LAddrCmd{addr:truncate(req.addr), prot:aProtDflt}); + a4l.f.wrData.enq(A4LWrData {strb:truncate(dh.dataByteEn), data:truncate(dh.data)}); + $display("[%0d]: %m: AXI4-LITE WRITE REQUEST Addr:%0x BE:%0x Data:%0x", $time, req.addr, dh.dataByteEn, dh.data); + end else begin + a4l.f.rdAddr.enq(A4LAddrCmd{addr:truncate(req.addr), prot:aProtDflt}); + $display("[%0d]: %m: AXI4-LITE READ REQUEST Addr:%0x",$time, req.addr); + end + end + endrule + + rule wmemi_response (!axiActive); + let rsp <- wmemiM.resp; + wmemiS.respd(rsp.data, rsp.respLast); + endrule + + rule axi_write_response (axiActive); + let aw = a4l.f.wrResp.first; //TODO: look at AXI write response code (assume OKAY for now) + a4l.f.wrResp.deq; + // write response : Do Nothing, just swallow the write rsp + axiActive <= False; + $display("[%0d]: %m: AXI4-LITE WRITE RESPOSNE",$time); + endrule + + rule axi_read_response (axiActive); + let ar = a4l.f.rdResp.first; //TODO: look at AXI read response code (assume OKAY for now) + a4l.f.rdResp.deq; + wmemiS.respd(extend(ar.data), True); // Send the data back upstream + axiActive <= False; + $display("[%0d]: %m: AXI4-LITE READ RESPOSNE Data:%0x",$time, ar.data); + endrule + + + WmemiES16B wmemi_Es <- mkWmemiStoES(wmemiS.slv); + WmemiEM16B wmemi_Em <- mkWmemiMtoEm(wmemiM.mas); + interface WmemiES16B wmemiS0 = wmemi_Es; + interface WmemiEM16B wmemiM0 = wmemi_Em; + interface A4LMIfc axiM0 = a4l.a4lm; +endmodule + +endpackage diff --git a/bsv/top/FTop_ml605.bsv b/bsv/top/FTop_ml605.bsv index bf4b6644..0d0cfa37 100644 --- a/bsv/top/FTop_ml605.bsv +++ b/bsv/top/FTop_ml605.bsv @@ -22,6 +22,7 @@ import WsiAdapter ::*; import XilinxExtra ::*; import ProtocolMonitor ::*; import PCIEwrap ::*; +import WmemiTap ::*; // BSV Imports... import Clocks ::*; @@ -84,6 +85,8 @@ module mkFTop_ml605#(Clock sys0_clkp, Clock sys0_clkn, // 200 MHz Board Reg#(Bool) needs_init <- mkReg(True, clocked_by p125Clk, reset_by p125Rst); Reg#(UInt#(32)) freeCnt <- mkReg(0, clocked_by p125Clk, reset_by p125Rst); + WmemiTapIfc wmemiTap <- mkWmemiTap( clocked_by p125Clk, reset_by p125Rst); + rule inc_freecnt; freeCnt <= freeCnt + 1; endrule // Poly approach... @@ -138,7 +141,8 @@ module mkFTop_ml605#(Clock sys0_clkp, Clock sys0_clkn, // 200 MHz Board mkConnection(tcGbe0.wti_m, gbe0.wtiS0); // Wmemi... - mkConnection(ctop.wmemiM0, dram0.wmemiS0); + mkConnection(ctop.wmemiM0, wmemiTap.wmemiS0); + mkConnection(wmemiTap.wmemiM0, dram0.wmemiS0); rule init_lcd if (needs_init); // Paint the 16x2 LCD... Vector#(16,Bit#(8)) text1 = lcdLine(" Atomic Rules "); diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv index 301b6e16..e5f56613 100644 --- a/bsv/utl/CompileTime.bsv +++ b/bsv/utl/CompileTime.bsv @@ -1 +1 @@ -Bit#(32) compileTime = 1390838362; // Verilog Mon Jan 27 10:59:22 EST 2014 +Bit#(32) compileTime = 1391113942; // Verilog Thu Jan 30 15:32:22 EST 2014 diff --git a/rtl/mkBLUART.v b/rtl/mkBLUART.v index 51e36e2a..c33888a2 100644 --- a/rtl/mkBLUART.v +++ b/rtl/mkBLUART.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:26 EST 2014 +// On Thu Jan 30 14:50:31 EST 2014 // // // Ports: diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index fc577ae8..b4ce2886 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:21 EST 2014 +// On Thu Jan 30 15:27:17 EST 2014 // // // Ports: @@ -512,6 +512,7 @@ module mkBiasWorker16B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -536,13 +537,12 @@ module mkBiasWorker16B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, - MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -565,7 +565,8 @@ module mkBiasWorker16B(wciS0_Clk, rdat__h11601, rdat__h11609; wire [15 : 0] x__h11463; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wsiM_reqFifo_cntr_r_37_MINUS_1___d247; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -646,6 +647,13 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; + // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -728,14 +736,11 @@ module mkBiasWorker16B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; - assign MUX_biasValue_write_1__SEL_2 = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -769,7 +774,7 @@ module mkBiasWorker16B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -805,7 +810,6 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h11369 } ; - assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -839,7 +843,7 @@ module mkBiasWorker16B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -929,7 +933,7 @@ module mkBiasWorker16B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register controlReg assign controlReg_D_IN = @@ -938,7 +942,7 @@ module mkBiasWorker16B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -961,11 +965,11 @@ module mkBiasWorker16B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1112,7 +1116,7 @@ module mkBiasWorker16B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1303,10 +1307,10 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; assign rdat__h11459 = hasDebugLogic ? { 16'd0, x__h11463 } : 32'd0 ; assign rdat__h11559 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h11573 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1316,6 +1320,7 @@ module mkBiasWorker16B(wciS0_Clk, assign rdat__h11609 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; + assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h11463 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[151:120] + biasValue, @@ -1570,10 +1575,10 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1636,7 +1641,7 @@ module mkBiasWorker16B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1648,7 +1653,7 @@ module mkBiasWorker16B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index fdfbd22b..358c993d 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:24 EST 2014 +// On Thu Jan 30 15:27:20 EST 2014 // // // Ports: @@ -512,6 +512,7 @@ module mkBiasWorker32B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -536,13 +537,12 @@ module mkBiasWorker32B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, - MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -565,7 +565,8 @@ module mkBiasWorker32B(wciS0_Clk, rdat__h12397, rdat__h12405; wire [15 : 0] x__h12259; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wsiM_reqFifo_cntr_r_37_MINUS_1___d247; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -646,6 +647,13 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; + // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -728,14 +736,11 @@ module mkBiasWorker32B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; - assign MUX_biasValue_write_1__SEL_2 = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -769,7 +774,7 @@ module mkBiasWorker32B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -805,7 +810,6 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h12165 } ; - assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -839,7 +843,7 @@ module mkBiasWorker32B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -929,7 +933,7 @@ module mkBiasWorker32B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register controlReg assign controlReg_D_IN = @@ -938,7 +942,7 @@ module mkBiasWorker32B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -961,11 +965,11 @@ module mkBiasWorker32B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1112,7 +1116,7 @@ module mkBiasWorker32B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1303,10 +1307,10 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; assign rdat__h12255 = hasDebugLogic ? { 16'd0, x__h12259 } : 32'd0 ; assign rdat__h12355 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h12369 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1316,6 +1320,7 @@ module mkBiasWorker32B(wciS0_Clk, assign rdat__h12405 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; + assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h12259 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[295:264] + biasValue, @@ -1576,10 +1581,10 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1642,7 +1647,7 @@ module mkBiasWorker32B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1654,7 +1659,7 @@ module mkBiasWorker32B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index d83b1955..3d0eb245 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:22 EST 2014 +// On Thu Jan 30 15:27:18 EST 2014 // // // Ports: @@ -511,6 +511,7 @@ module mkBiasWorker4B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -535,13 +536,12 @@ module mkBiasWorker4B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, - MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -564,7 +564,8 @@ module mkBiasWorker4B(wciS0_Clk, rdat__h11011, x_data__h10099; wire [15 : 0] x__h10865; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wsiM_reqFifo_cntr_r_37_MINUS_1___d247; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -645,6 +646,13 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; + // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -727,14 +735,11 @@ module mkBiasWorker4B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; - assign MUX_biasValue_write_1__SEL_2 = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -768,7 +773,7 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -804,7 +809,6 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h10771 } ; - assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -838,7 +842,7 @@ module mkBiasWorker4B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -928,7 +932,7 @@ module mkBiasWorker4B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register controlReg assign controlReg_D_IN = @@ -937,7 +941,7 @@ module mkBiasWorker4B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -960,11 +964,11 @@ module mkBiasWorker4B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1111,7 +1115,7 @@ module mkBiasWorker4B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1301,10 +1305,10 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; assign rdat__h10861 = hasDebugLogic ? { 16'd0, x__h10865 } : 32'd0 ; assign rdat__h10961 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h10975 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1314,6 +1318,7 @@ module mkBiasWorker4B(wciS0_Clk, assign rdat__h11011 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; + assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h10865 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = wsiS_reqFifo_D_OUT[43:12] + biasValue ; always@(wci_wslv_reqF_D_OUT or @@ -1562,10 +1567,10 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1628,7 +1633,7 @@ module mkBiasWorker4B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1640,7 +1645,7 @@ module mkBiasWorker4B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index ddbc60aa..b419efb4 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:23 EST 2014 +// On Thu Jan 30 15:27:19 EST 2014 // // // Ports: @@ -510,6 +510,7 @@ module mkBiasWorker8B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -534,13 +535,12 @@ module mkBiasWorker8B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, - MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -563,7 +563,8 @@ module mkBiasWorker8B(wciS0_Clk, rdat__h11203, rdat__h11211; wire [15 : 0] x__h11065; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wsiM_reqFifo_cntr_r_37_MINUS_1___d247; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -644,6 +645,13 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; + // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -726,14 +734,11 @@ module mkBiasWorker8B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; - assign MUX_biasValue_write_1__SEL_2 = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -767,7 +772,7 @@ module mkBiasWorker8B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -803,7 +808,6 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h10971 } ; - assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -837,7 +841,7 @@ module mkBiasWorker8B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -927,7 +931,7 @@ module mkBiasWorker8B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register controlReg assign controlReg_D_IN = @@ -936,7 +940,7 @@ module mkBiasWorker8B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - MUX_biasValue_write_1__SEL_2 ; + WILL_FIRE_RL_wci_ctrl_EiI ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -959,11 +963,11 @@ module mkBiasWorker8B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1110,7 +1114,7 @@ module mkBiasWorker8B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1300,10 +1304,10 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; + wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; assign rdat__h11061 = hasDebugLogic ? { 16'd0, x__h11065 } : 32'd0 ; assign rdat__h11161 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h11175 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1313,6 +1317,7 @@ module mkBiasWorker8B(wciS0_Clk, assign rdat__h11211 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; + assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h11065 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[79:48] + biasValue, @@ -1565,10 +1570,10 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1631,7 +1636,7 @@ module mkBiasWorker8B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1643,7 +1648,7 @@ module mkBiasWorker8B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v index 3dc2121a..56a0e9f4 100644 --- a/rtl/mkCTop16B.v +++ b/rtl/mkCTop16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:50 EST 2014 +// On Thu Jan 30 15:34:10 EST 2014 // // // Ports: @@ -65,8 +65,6 @@ // wmemiM0_MDataByteEn O 16 reg // wmemiM0_MReset_n O 1 // gps_ppsSyncOut O 1 -// upads_rts O 1 const -// upads_tx O 1 reg // RST_N_wci_m_0 O 1 reset // RST_N_wci_m_1 O 1 reset // RST_N_wci_m_2 O 1 reset @@ -103,8 +101,6 @@ // wmemiM0_SResp I 2 // wmemiM0_SData I 128 // gps_ppsSyncIn_x I 1 reg -// upads_cts_arg I 1 reg -// upads_rx_arg I 1 reg // EN_server_request_put I 1 // EN_cpServer_request_put I 1 // wci_m_0_SThreadBusy I 1 reg @@ -341,14 +337,6 @@ module mkCTop16B(pciDevice, gps_ppsSyncOut, - upads_rts, - - upads_tx, - - upads_cts_arg, - - upads_rx_arg, - RST_N_wci_m_0, RST_N_wci_m_1, RST_N_wci_m_2, @@ -652,18 +640,6 @@ module mkCTop16B(pciDevice, // value method gps_ppsSyncOut output gps_ppsSyncOut; - // value method upads_rts - output upads_rts; - - // value method upads_tx - output upads_tx; - - // action method upads_cts - input upads_cts_arg; - - // action method upads_rx - input upads_rx_arg; - // output resets output RST_N_wci_m_0; output RST_N_wci_m_1; @@ -719,8 +695,6 @@ module mkCTop16B(pciDevice, RST_N_wci_m_3, RST_N_wci_m_4, gps_ppsSyncOut, - upads_rts, - upads_tx, wci_m_0_MAddrSpace, wci_m_1_MAddrSpace, wci_m_2_MAddrSpace, @@ -1094,10 +1068,6 @@ module mkCTop16B(pciDevice, inf_RST_N_wci_m_9, inf_gps_ppsSyncIn_x, inf_gps_ppsSyncOut, - inf_upads_cts_arg, - inf_upads_rts, - inf_upads_rx_arg, - inf_upads_tx, inf_wci_m_0_MAddrSpace, inf_wci_m_0_SThreadBusy, inf_wci_m_10_MAddrSpace, @@ -1323,12 +1293,6 @@ module mkCTop16B(pciDevice, // value method gps_ppsSyncOut assign gps_ppsSyncOut = inf_gps_ppsSyncOut ; - // value method upads_rts - assign upads_rts = inf_upads_rts ; - - // value method upads_tx - assign upads_tx = inf_upads_tx ; - // submodule app mkOCApp16B #(.hasDebugLogic(1'd1)) app(.RST_N_rst_0(inf_RST_N_wci_m_0), .RST_N_rst_1(inf_RST_N_wci_m_1), @@ -1525,8 +1489,6 @@ module mkCTop16B(pciDevice, .gps_ppsSyncIn_x(inf_gps_ppsSyncIn_x), .server_request_put(inf_server_request_put), .switch_x(inf_switch_x), - .upads_cts_arg(inf_upads_cts_arg), - .upads_rx_arg(inf_upads_rx_arg), .uuid_arg(inf_uuid_arg), .wci_m_0_SData(inf_wci_m_0_SData), .wci_m_0_SFlag(inf_wci_m_0_SFlag), @@ -1711,8 +1673,6 @@ module mkCTop16B(pciDevice, .RDY_cpNow(), .gps_ppsSyncOut(inf_gps_ppsSyncOut), .RDY_uuid(), - .upads_rts(inf_upads_rts), - .upads_tx(inf_upads_tx), .RST_N_wci_m_0(inf_RST_N_wci_m_0), .RST_N_wci_m_1(inf_RST_N_wci_m_1), .RST_N_wci_m_2(inf_RST_N_wci_m_2), @@ -1871,8 +1831,6 @@ module mkCTop16B(pciDevice, assign inf_gps_ppsSyncIn_x = gps_ppsSyncIn_x ; assign inf_server_request_put = server_request_put ; assign inf_switch_x = switch_x ; - assign inf_upads_cts_arg = upads_cts_arg ; - assign inf_upads_rx_arg = upads_rx_arg ; assign inf_uuid_arg = app_uuid ; assign inf_wci_m_0_SData = app_wci_s_0_SData ; assign inf_wci_m_0_SFlag = app_wci_s_0_SFlag ; diff --git a/rtl/mkDramServer_v6.v b/rtl/mkDramServer_v6.v index 3b120dd9..953ca5a2 100644 --- a/rtl/mkDramServer_v6.v +++ b/rtl/mkDramServer_v6.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:58 EST 2014 +// On Thu Jan 30 14:51:03 EST 2014 // // // Ports: diff --git a/rtl/mkFMC150.v b/rtl/mkFMC150.v index 0365bd60..de8600d4 100644 --- a/rtl/mkFMC150.v +++ b/rtl/mkFMC150.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:09 EST 2014 +// On Thu Jan 30 14:51:13 EST 2014 // // // Ports: diff --git a/rtl/mkFlashController2416.v b/rtl/mkFlashController2416.v index 007efe6f..edacd369 100644 --- a/rtl/mkFlashController2416.v +++ b/rtl/mkFlashController2416.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:44 EST 2014 +// On Thu Jan 30 14:50:49 EST 2014 // // // Ports: diff --git a/rtl/mkFlashWorker.v b/rtl/mkFlashWorker.v index 83726325..ce25db86 100644 --- a/rtl/mkFlashWorker.v +++ b/rtl/mkFlashWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:03 EST 2014 +// On Thu Jan 30 14:51:08 EST 2014 // // // Ports: diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index 3271d4e5..d3177a98 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:40 EST 2014 +// On Thu Jan 30 14:50:45 EST 2014 // // // Ports: diff --git a/rtl/mkGbeWorker.v b/rtl/mkGbeWorker.v index 1fdfeb4f..ceb6da0e 100644 --- a/rtl/mkGbeWorker.v +++ b/rtl/mkGbeWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:13 EST 2014 +// On Thu Jan 30 14:51:18 EST 2014 // // // Ports: diff --git a/rtl/mkICAPWorker.v b/rtl/mkICAPWorker.v index 22e2f9a1..41510aa4 100644 --- a/rtl/mkICAPWorker.v +++ b/rtl/mkICAPWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:05 EST 2014 +// On Thu Jan 30 14:51:10 EST 2014 // // // Ports: diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v index 2ca33e29..e1a186fd 100644 --- a/rtl/mkMemiTestWorker.v +++ b/rtl/mkMemiTestWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:25 EST 2014 +// On Thu Jan 30 15:27:21 EST 2014 // // // Ports: @@ -513,7 +513,7 @@ module mkMemiTestWorker(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; wire [145 : 0] MUX_wmemi_dhF_q_0_write_1__VAL_1, MUX_wmemi_dhF_q_0_write_1__VAL_2, - MUX_wmemi_dhF_q_1_write_1__VAL_2; + MUX_wmemi_dhF_q_1_write_1__VAL_1; wire [51 : 0] MUX_wmemi_reqF_q_0_write_1__VAL_1, MUX_wmemi_reqF_q_0_write_1__VAL_2, MUX_wmemi_reqF_q_1_write_1__VAL_1, @@ -555,15 +555,12 @@ module mkMemiTestWorker(wciS0_Clk, wmemi_dhF_cntr_r_84_MINUS_1___d193, wmemi_reqF_cntr_r_61_MINUS_1___d170; wire NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311, - NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264, _dfoo1, _dfoo11, _dfoo3, _dfoo5, _dfoo7, - _dfoo9, - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272, - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294; + _dfoo9; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -661,15 +658,23 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_write_req assign WILL_FIRE_RL_write_req = - wmemi_reqF_cntr_r != 2'd2 && - NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 && - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 ; + wmemi_reqF_cntr_r != 2'd2 && wmemi_dhF_cntr_r != 2'd2 && + wmemi_operateD && + wmemi_peerIsReady && + wgen_gsF_EMPTY_N && + wci_wslv_cState == 3'd2 && + isTesting && + isWriter && + !isReader ; // rule RL_read_req assign WILL_FIRE_RL_read_req = wmemi_reqF_cntr_r != 2'd2 && wmemi_operateD && wmemi_peerIsReady && - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 ; + wci_wslv_cState == 3'd2 && + isTesting && + !isWriter && + isReader ; // rule RL_read_resp assign WILL_FIRE_RL_read_resp = @@ -794,13 +799,13 @@ module mkMemiTestWorker(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wmemi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 ; - assign MUX_wmemi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 ; + assign MUX_wmemi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 ; assign MUX_wmemi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 ; - assign MUX_wmemi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 ; + assign MUX_wmemi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 ; assign MUX_wmemi_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 ; assign MUX_wmemi_reqF_q_0_write_1__SEL_2 = @@ -848,14 +853,14 @@ module mkMemiTestWorker(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h14736 } ; assign MUX_wmemi_dhF_cntr_r_write_1__VAL_2 = wmemi_dhF_cntr_r + 2'd1 ; assign MUX_wmemi_dhF_q_0_write_1__VAL_1 = - { 2'd3, wgen_gsF_D_OUT, 16'd65535 } ; - assign MUX_wmemi_dhF_q_0_write_1__VAL_2 = (wmemi_dhF_cntr_r == 2'd1) ? - MUX_wmemi_dhF_q_0_write_1__VAL_1 : + MUX_wmemi_dhF_q_0_write_1__VAL_2 : wmemi_dhF_q_1 ; - assign MUX_wmemi_dhF_q_1_write_1__VAL_2 = + assign MUX_wmemi_dhF_q_0_write_1__VAL_2 = + { 2'd3, wgen_gsF_D_OUT, 16'd65535 } ; + assign MUX_wmemi_dhF_q_1_write_1__VAL_1 = (wmemi_dhF_cntr_r == 2'd2) ? - MUX_wmemi_dhF_q_0_write_1__VAL_1 : + MUX_wmemi_dhF_q_0_write_1__VAL_2 : 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign MUX_wmemi_reqF_cntr_r_write_1__VAL_2 = wmemi_reqF_cntr_r + 2'd1 ; assign MUX_wmemi_reqF_q_0_write_1__VAL_1 = @@ -906,7 +911,7 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_reqF_x_wire_wget = MUX_wmemi_reqF_q_0_write_1__VAL_2 ; assign wmemi_reqF_x_wire_whas = WILL_FIRE_RL_write_req || WILL_FIRE_RL_read_req ; - assign wmemi_dhF_x_wire_wget = MUX_wmemi_dhF_q_0_write_1__VAL_1 ; + assign wmemi_dhF_x_wire_wget = MUX_wmemi_dhF_q_0_write_1__VAL_2 ; assign wmemi_dhF_x_wire_whas = WILL_FIRE_RL_write_req ; assign wmemi_wmemiResponse_wget = { wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ; @@ -1176,24 +1181,15 @@ module mkMemiTestWorker(wciS0_Clk, // register wmemiRdReq assign wmemiRdReq_D_IN = wmemiRdReq + 32'd1 ; - assign wmemiRdReq_EN = - wmemi_reqF_cntr_r != 2'd2 && wmemi_operateD && - wmemi_peerIsReady && - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 ; + assign wmemiRdReq_EN = WILL_FIRE_RL_read_req ; // register wmemiRdResp assign wmemiRdResp_D_IN = wmemiRdResp + 32'd1 ; - assign wmemiRdResp_EN = - rgen_gsF_EMPTY_N && wmemi_respF_EMPTY_N && - wci_wslv_cState == 3'd2 && - isTesting ; + assign wmemiRdResp_EN = WILL_FIRE_RL_read_resp ; // register wmemiWrReq assign wmemiWrReq_D_IN = wmemiWrReq + 32'd1 ; - assign wmemiWrReq_EN = - wmemi_reqF_cntr_r != 2'd2 && - NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 && - wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 ; + assign wmemiWrReq_EN = WILL_FIRE_RL_write_req ; // register wmemi_busyWithMessage assign wmemi_busyWithMessage_D_IN = 1'b0 ; @@ -1225,21 +1221,21 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_0_EN = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_dhF_q_1 always@(MUX_wmemi_dhF_q_1_write_1__SEL_1 or - MUX_wmemi_dhF_q_0_write_1__VAL_1 or + MUX_wmemi_dhF_q_1_write_1__VAL_1 or MUX_wmemi_dhF_q_1_write_1__SEL_2 or - MUX_wmemi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + MUX_wmemi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemi_dhF_q_1_write_1__SEL_1: - wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_0_write_1__VAL_1; + wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_1_write_1__VAL_1; MUX_wmemi_dhF_q_1_write_1__SEL_2: - wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_1_write_1__VAL_2; + wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_1_D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: wmemi_dhF_q_1_D_IN = @@ -1247,8 +1243,8 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_1_EN = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_errorSticky @@ -1370,10 +1366,6 @@ module mkMemiTestWorker(wciS0_Clk, // remaining internal signals assign NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 = rgen_gsF_D_OUT != wmemi_respF_D_OUT[127:0] ; - assign NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 = - wmemi_dhF_cntr_r != 2'd2 && wmemi_operateD && - wmemi_peerIsReady && - wgen_gsF_EMPTY_N ; assign _dfoo1 = wci_wslv_respF_cntr_r != 2'd2 || wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; @@ -1395,10 +1387,6 @@ module mkMemiTestWorker(wciS0_Clk, assign addr__h13592 = { hwordAddr, 4'h0 } ; assign rdat__h14758 = { 24'd0, wmemi_statusR } ; assign testStatus__h14232 = { 31'h0, isReader } ; - assign wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 = - wci_wslv_cState == 3'd2 && isTesting && isWriter && !isReader ; - assign wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 = - wci_wslv_cState == 3'd2 && isTesting && !isWriter && isReader ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; assign wmemi_dhF_cntr_r_84_MINUS_1___d193 = wmemi_dhF_cntr_r - 2'd1 ; diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v index eadd3d32..a7b7f2bf 100644 --- a/rtl/mkOCApp16B.v +++ b/rtl/mkOCApp16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:37 EST 2014 +// On Thu Jan 30 15:27:33 EST 2014 // // // Ports: diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index 9c9d8bfe..b37bbb4f 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:15 EST 2014 +// On Thu Jan 30 15:33:49 EST 2014 // // // Ports: @@ -103,8 +103,6 @@ // RDY_cpNow O 1 const // gps_ppsSyncOut O 1 // led O 2 reg -// upads_rts O 1 const -// upads_tx O 1 reg // RST_N_wci_Vm_0 O 1 reset // RST_N_wci_Vm_1 O 1 reset // RST_N_wci_Vm_2 O 1 reset @@ -174,8 +172,6 @@ // gps_ppsSyncIn_x I 1 reg // switch_x I 3 reg // uuid_arg I 512 -// upads_cts_arg I 1 reg -// upads_rx_arg I 1 reg // EN_server_request_put I 1 // wci_Vm_0_SThreadBusy I 1 reg // wci_Vm_1_SThreadBusy I 1 reg @@ -538,14 +534,6 @@ module mkOCCP(pciDevice, uuid_arg, - upads_rts, - - upads_tx, - - upads_cts_arg, - - upads_rx_arg, - RST_N_wci_Vm_0, RST_N_wci_Vm_1, RST_N_wci_Vm_2, @@ -1046,18 +1034,6 @@ module mkOCCP(pciDevice, // action method uuid input [511 : 0] uuid_arg; - // value method upads_rts - output upads_rts; - - // value method upads_tx - output upads_tx; - - // action method upads_cts - input upads_cts_arg; - - // action method upads_rx - input upads_rx_arg; - // output resets output RST_N_wci_Vm_0; output RST_N_wci_Vm_1; @@ -1173,8 +1149,6 @@ module mkOCCP(pciDevice, RST_N_wci_Vm_7, RST_N_wci_Vm_8, RST_N_wci_Vm_9, - upads_rts, - upads_tx, wci_Vm_0_MAddrSpace, wci_Vm_10_MAddrSpace, wci_Vm_11_MAddrSpace, @@ -1658,15 +1632,6 @@ module mkOCCP(pciDevice, reg timeServ_xo2; wire timeServ_xo2_D_IN, timeServ_xo2_EN; - // register uartInited - reg uartInited; - wire uartInited_D_IN, uartInited_EN; - - // register uartTxtP - reg [5 : 0] uartTxtP; - wire [5 : 0] uartTxtP_D_IN; - wire uartTxtP_EN; - // register warmResetP reg warmResetP; wire warmResetP_D_IN, warmResetP_EN; @@ -3307,22 +3272,6 @@ module mkOCCP(pciDevice, adminRespF_ENQ, adminRespF_FULL_N; - // ports of submodule bluart - wire [15 : 0] bluart_setClkDiv_put; - wire [7 : 0] bluart_rxChar_get, - bluart_rxLevel, - bluart_txChar_put, - bluart_txLevel; - wire bluart_EN_rxChar_get, - bluart_EN_setClkDiv_put, - bluart_EN_txChar_put, - bluart_RDY_rxChar_get, - bluart_RDY_txChar_put, - bluart_pads_cts_arg, - bluart_pads_rts, - bluart_pads_rx_arg, - bluart_pads_tx; - // ports of submodule cpReqF wire [58 : 0] cpReqF_D_IN, cpReqF_D_OUT; wire cpReqF_CLR, cpReqF_DEQ, cpReqF_EMPTY_N, cpReqF_ENQ, cpReqF_FULL_N; @@ -3578,6 +3527,7 @@ module mkOCCP(pciDevice, // rule scheduling signals wire CAN_FIRE_RL_cpDispatch_F_T_F_F, CAN_FIRE_RL_cpDispatch_F_T_T_F_F, + CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_F, CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_T, CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T, CAN_FIRE_RL_cpDispatch_F_T_T_T, @@ -3858,15 +3808,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_OOB, WILL_FIRE_RL_cpDispatch_F_T_F_T, WILL_FIRE_RL_cpDispatch_F_T_T_F_F, - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T, + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F, WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T, WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T, WILL_FIRE_RL_cpDispatch_F_T_T_T, - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F, WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T, WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T, WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T, @@ -3878,7 +3824,6 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_T_F_F_T, WILL_FIRE_RL_cpDispatch_T_F_T, WILL_FIRE_RL_cpDispatch_T_T, - WILL_FIRE_RL_init_uart_text, WILL_FIRE_RL_readAdminResponseCollect, WILL_FIRE_RL_reqRcv, WILL_FIRE_RL_responseAdminRd, @@ -3946,22 +3891,21 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_9_wrkBusy; // inputs to muxes for submodule ports - reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, + reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, MUX_wci_10_reqF_q_0_write_1__VAL_1, MUX_wci_11_reqF_q_0_write_1__VAL_1, MUX_wci_12_reqF_q_0_write_1__VAL_1, MUX_wci_13_reqF_q_0_write_1__VAL_1, MUX_wci_14_reqF_q_0_write_1__VAL_1, - MUX_wci_1_reqF_q_0_write_1__VAL_2, - MUX_wci_2_reqF_q_0_write_1__VAL_2, - MUX_wci_3_reqF_q_0_write_1__VAL_2, - MUX_wci_4_reqF_q_0_write_1__VAL_2, - MUX_wci_5_reqF_q_0_write_1__VAL_2, - MUX_wci_6_reqF_q_0_write_1__VAL_2, - MUX_wci_7_reqF_q_0_write_1__VAL_2, - MUX_wci_8_reqF_q_0_write_1__VAL_2, - MUX_wci_9_reqF_q_0_write_1__VAL_2; - reg [7 : 0] MUX_bluart_txChar_put_1__VAL_2; + MUX_wci_1_reqF_q_0_write_1__VAL_1, + MUX_wci_2_reqF_q_0_write_1__VAL_1, + MUX_wci_3_reqF_q_0_write_1__VAL_1, + MUX_wci_4_reqF_q_0_write_1__VAL_1, + MUX_wci_5_reqF_q_0_write_1__VAL_1, + MUX_wci_6_reqF_q_0_write_1__VAL_1, + MUX_wci_7_reqF_q_0_write_1__VAL_1, + MUX_wci_8_reqF_q_0_write_1__VAL_1, + MUX_wci_9_reqF_q_0_write_1__VAL_1; reg [2 : 0] MUX_wci_0_reqERR_write_1__VAL_1, MUX_wci_0_reqFAIL_write_1__VAL_1, MUX_wci_0_reqTO_write_1__VAL_1, @@ -4007,7 +3951,7 @@ module mkOCCP(pciDevice, MUX_wci_9_reqERR_write_1__VAL_1, MUX_wci_9_reqFAIL_write_1__VAL_1, MUX_wci_9_reqTO_write_1__VAL_1; - wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, + wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, MUX_wci_0_reqF_x_wire_wset_1__VAL_1, MUX_wci_0_reqF_x_wire_wset_1__VAL_2, MUX_wci_0_reqF_x_wire_wset_1__VAL_3, @@ -4026,31 +3970,31 @@ module mkOCCP(pciDevice, MUX_wci_14_reqF_q_0_write_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_3, - MUX_wci_1_reqF_q_0_write_1__VAL_1, + MUX_wci_1_reqF_q_0_write_1__VAL_2, MUX_wci_1_reqF_x_wire_wset_1__VAL_2, MUX_wci_1_reqF_x_wire_wset_1__VAL_3, - MUX_wci_2_reqF_q_0_write_1__VAL_1, + MUX_wci_2_reqF_q_0_write_1__VAL_2, MUX_wci_2_reqF_x_wire_wset_1__VAL_2, MUX_wci_2_reqF_x_wire_wset_1__VAL_3, - MUX_wci_3_reqF_q_0_write_1__VAL_1, + MUX_wci_3_reqF_q_0_write_1__VAL_2, MUX_wci_3_reqF_x_wire_wset_1__VAL_2, MUX_wci_3_reqF_x_wire_wset_1__VAL_3, - MUX_wci_4_reqF_q_0_write_1__VAL_1, + MUX_wci_4_reqF_q_0_write_1__VAL_2, MUX_wci_4_reqF_x_wire_wset_1__VAL_2, MUX_wci_4_reqF_x_wire_wset_1__VAL_3, - MUX_wci_5_reqF_q_0_write_1__VAL_1, + MUX_wci_5_reqF_q_0_write_1__VAL_2, MUX_wci_5_reqF_x_wire_wset_1__VAL_2, MUX_wci_5_reqF_x_wire_wset_1__VAL_3, - MUX_wci_6_reqF_q_0_write_1__VAL_1, + MUX_wci_6_reqF_q_0_write_1__VAL_2, MUX_wci_6_reqF_x_wire_wset_1__VAL_2, MUX_wci_6_reqF_x_wire_wset_1__VAL_3, - MUX_wci_7_reqF_q_0_write_1__VAL_1, + MUX_wci_7_reqF_q_0_write_1__VAL_2, MUX_wci_7_reqF_x_wire_wset_1__VAL_2, MUX_wci_7_reqF_x_wire_wset_1__VAL_3, - MUX_wci_8_reqF_q_0_write_1__VAL_1, + MUX_wci_8_reqF_q_0_write_1__VAL_2, MUX_wci_8_reqF_x_wire_wset_1__VAL_2, MUX_wci_8_reqF_x_wire_wset_1__VAL_3, - MUX_wci_9_reqF_q_0_write_1__VAL_1, + MUX_wci_9_reqF_q_0_write_1__VAL_2, MUX_wci_9_reqF_x_wire_wset_1__VAL_2, MUX_wci_9_reqF_x_wire_wset_1__VAL_3; wire [64 : 0] MUX_cpReq_write_1__VAL_4; @@ -4132,8 +4076,7 @@ module mkOCCP(pciDevice, MUX_wci_9_respF_enq_1__VAL_5; wire [32 : 0] MUX_adminResp2F_enq_1__VAL_1, MUX_adminResp2F_enq_1__VAL_2, - MUX_adminResp2F_enq_1__VAL_3, - MUX_adminResp2F_enq_1__VAL_4; + MUX_adminResp2F_enq_1__VAL_3; wire [31 : 0] MUX_readCntReg_write_1__VAL_2, MUX_wci_0_respTimr_write_1__VAL_2, MUX_wci_10_respTimr_write_1__VAL_2, @@ -4150,14 +4093,13 @@ module mkOCCP(pciDevice, MUX_wci_7_respTimr_write_1__VAL_2, MUX_wci_8_respTimr_write_1__VAL_2, MUX_wci_9_respTimr_write_1__VAL_2; - wire MUX_adminResp2F_enq_1__SEL_1, - MUX_wci_0_busy_write_1__SEL_1, + wire MUX_wci_0_busy_write_1__SEL_1, MUX_wci_0_busy_write_1__SEL_2, MUX_wci_0_reqERR_write_1__SEL_1, MUX_wci_0_reqFAIL_write_1__SEL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_2, - MUX_wci_0_reqF_q_0_write_1__SEL_2, + MUX_wci_0_reqF_q_0_write_1__SEL_1, MUX_wci_0_reqPend_write_1__SEL_1, MUX_wci_0_reqTO_write_1__SEL_1, MUX_wci_0_respF_enq_1__SEL_6, @@ -4223,7 +4165,7 @@ module mkOCCP(pciDevice, MUX_wci_1_reqFAIL_write_1__SEL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_2, - MUX_wci_1_reqF_q_0_write_1__SEL_2, + MUX_wci_1_reqF_q_0_write_1__SEL_1, MUX_wci_1_reqPend_write_1__SEL_1, MUX_wci_1_reqTO_write_1__SEL_1, MUX_wci_1_respF_enq_1__SEL_6, @@ -4234,7 +4176,7 @@ module mkOCCP(pciDevice, MUX_wci_2_reqFAIL_write_1__SEL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_2, - MUX_wci_2_reqF_q_0_write_1__SEL_2, + MUX_wci_2_reqF_q_0_write_1__SEL_1, MUX_wci_2_reqPend_write_1__SEL_1, MUX_wci_2_reqTO_write_1__SEL_1, MUX_wci_2_respF_enq_1__SEL_6, @@ -4245,7 +4187,7 @@ module mkOCCP(pciDevice, MUX_wci_3_reqFAIL_write_1__SEL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_2, - MUX_wci_3_reqF_q_0_write_1__SEL_2, + MUX_wci_3_reqF_q_0_write_1__SEL_1, MUX_wci_3_reqPend_write_1__SEL_1, MUX_wci_3_reqTO_write_1__SEL_1, MUX_wci_3_respF_enq_1__SEL_6, @@ -4256,7 +4198,7 @@ module mkOCCP(pciDevice, MUX_wci_4_reqFAIL_write_1__SEL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_2, - MUX_wci_4_reqF_q_0_write_1__SEL_2, + MUX_wci_4_reqF_q_0_write_1__SEL_1, MUX_wci_4_reqPend_write_1__SEL_1, MUX_wci_4_reqTO_write_1__SEL_1, MUX_wci_4_respF_enq_1__SEL_6, @@ -4267,7 +4209,7 @@ module mkOCCP(pciDevice, MUX_wci_5_reqFAIL_write_1__SEL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_2, - MUX_wci_5_reqF_q_0_write_1__SEL_2, + MUX_wci_5_reqF_q_0_write_1__SEL_1, MUX_wci_5_reqPend_write_1__SEL_1, MUX_wci_5_reqTO_write_1__SEL_1, MUX_wci_5_respF_enq_1__SEL_6, @@ -4278,7 +4220,7 @@ module mkOCCP(pciDevice, MUX_wci_6_reqFAIL_write_1__SEL_1, MUX_wci_6_reqF_cntr_r_write_1__VAL_1, MUX_wci_6_reqF_cntr_r_write_1__VAL_2, - MUX_wci_6_reqF_q_0_write_1__SEL_2, + MUX_wci_6_reqF_q_0_write_1__SEL_1, MUX_wci_6_reqPend_write_1__SEL_1, MUX_wci_6_reqTO_write_1__SEL_1, MUX_wci_6_respF_enq_1__SEL_6, @@ -4289,7 +4231,7 @@ module mkOCCP(pciDevice, MUX_wci_7_reqFAIL_write_1__SEL_1, MUX_wci_7_reqF_cntr_r_write_1__VAL_1, MUX_wci_7_reqF_cntr_r_write_1__VAL_2, - MUX_wci_7_reqF_q_0_write_1__SEL_2, + MUX_wci_7_reqF_q_0_write_1__SEL_1, MUX_wci_7_reqPend_write_1__SEL_1, MUX_wci_7_reqTO_write_1__SEL_1, MUX_wci_7_respF_enq_1__SEL_6, @@ -4300,7 +4242,7 @@ module mkOCCP(pciDevice, MUX_wci_8_reqFAIL_write_1__SEL_1, MUX_wci_8_reqF_cntr_r_write_1__VAL_1, MUX_wci_8_reqF_cntr_r_write_1__VAL_2, - MUX_wci_8_reqF_q_0_write_1__SEL_2, + MUX_wci_8_reqF_q_0_write_1__SEL_1, MUX_wci_8_reqPend_write_1__SEL_1, MUX_wci_8_reqTO_write_1__SEL_1, MUX_wci_8_respF_enq_1__SEL_6, @@ -4311,7 +4253,7 @@ module mkOCCP(pciDevice, MUX_wci_9_reqFAIL_write_1__SEL_1, MUX_wci_9_reqF_cntr_r_write_1__VAL_1, MUX_wci_9_reqF_cntr_r_write_1__VAL_2, - MUX_wci_9_reqF_q_0_write_1__SEL_2, + MUX_wci_9_reqF_q_0_write_1__SEL_1, MUX_wci_9_reqPend_write_1__SEL_1, MUX_wci_9_reqTO_write_1__SEL_1, MUX_wci_9_respF_enq_1__SEL_6, @@ -4321,591 +4263,586 @@ module mkOCCP(pciDevice, MUX_wrkAct_write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h106736, - v__h106789, - v__h14436, - v__h14526, - v__h14615, - v__h14839, - v__h14929, - v__h15018, - v__h15247, - v__h15337, - v__h15426, - v__h18805, - v__h18895, - v__h18984, - v__h19208, - v__h19298, - v__h19387, - v__h19616, - v__h19706, - v__h19795, - v__h23174, - v__h23264, - v__h23353, - v__h23577, - v__h23667, - v__h23756, - v__h23985, - v__h24075, - v__h24164, - v__h27543, - v__h27633, - v__h27722, - v__h27946, - v__h28036, - v__h28125, - v__h28354, - v__h28444, - v__h28533, - v__h31912, - v__h32002, - v__h32091, - v__h32315, - v__h32405, - v__h32494, - v__h32723, - v__h32813, - v__h32902, - v__h36281, - v__h36371, - v__h36460, - v__h36684, - v__h36774, - v__h36863, - v__h37092, - v__h37182, - v__h37271, - v__h40650, - v__h40740, - v__h40829, - v__h41053, - v__h41143, - v__h41232, - v__h41461, - v__h41551, - v__h41640, - v__h45019, - v__h45109, - v__h45198, - v__h45422, - v__h45512, - v__h45601, - v__h45830, - v__h45920, - v__h46009, - v__h49388, - v__h49478, - v__h49567, - v__h49791, - v__h49881, - v__h49970, - v__h50199, - v__h50289, - v__h50378, - v__h53757, - v__h53847, - v__h53936, - v__h54160, - v__h54250, - v__h54339, - v__h54568, - v__h54658, - v__h54747, - v__h58126, - v__h58216, - v__h58305, - v__h58529, - v__h58619, - v__h58708, - v__h58937, - v__h59027, - v__h59116, - v__h62495, - v__h62585, - v__h62674, - v__h62898, - v__h62988, - v__h63077, - v__h63306, - v__h63396, - v__h63485, - v__h66864, - v__h66954, - v__h67043, - v__h67267, - v__h67357, - v__h67446, - v__h67675, - v__h67765, - v__h67854, - v__h71233, - v__h71323, - v__h71412, - v__h71636, - v__h71726, - v__h71815, - v__h72044, - v__h72134, - v__h72223, - v__h75602, - v__h75692, - v__h75781, - v__h76005, - v__h76095, - v__h76184, - v__h76413, - v__h76503, - v__h76592, - v__h80654, - v__h81242, - v__h81350, - v__h81929, - v__h82037, - v__h82616, - v__h82724, - v__h83303, - v__h83411, - v__h83990, - v__h84098, - v__h84677, - v__h84785, - v__h85364, - v__h85472, - v__h86051, - v__h86159, - v__h86738, - v__h86846, - v__h87425, - v__h87533, - v__h88112, - v__h88220, - v__h88799, - v__h88907, - v__h89486, - v__h89594, - v__h90173, - v__h90281, - v__h90860, - v__h97758, - v__h97829, - v__h97900, - v__h97971, - v__h98042, - v__h98113, - v__h98184, - v__h98255, - v__h98326, - v__h98397, - v__h98468, - v__h98539, - v__h98610, - v__h98681, - v__h98752; + reg [63 : 0] v__h104109, + v__h104162, + v__h11985, + v__h12075, + v__h12164, + v__h12388, + v__h12478, + v__h12567, + v__h12796, + v__h12886, + v__h12975, + v__h16354, + v__h16444, + v__h16533, + v__h16757, + v__h16847, + v__h16936, + v__h17165, + v__h17255, + v__h17344, + v__h20723, + v__h20813, + v__h20902, + v__h21126, + v__h21216, + v__h21305, + v__h21534, + v__h21624, + v__h21713, + v__h25092, + v__h25182, + v__h25271, + v__h25495, + v__h25585, + v__h25674, + v__h25903, + v__h25993, + v__h26082, + v__h29461, + v__h29551, + v__h29640, + v__h29864, + v__h29954, + v__h30043, + v__h30272, + v__h30362, + v__h30451, + v__h33830, + v__h33920, + v__h34009, + v__h34233, + v__h34323, + v__h34412, + v__h34641, + v__h34731, + v__h34820, + v__h38199, + v__h38289, + v__h38378, + v__h38602, + v__h38692, + v__h38781, + v__h39010, + v__h39100, + v__h39189, + v__h42568, + v__h42658, + v__h42747, + v__h42971, + v__h43061, + v__h43150, + v__h43379, + v__h43469, + v__h43558, + v__h46937, + v__h47027, + v__h47116, + v__h47340, + v__h47430, + v__h47519, + v__h47748, + v__h47838, + v__h47927, + v__h51306, + v__h51396, + v__h51485, + v__h51709, + v__h51799, + v__h51888, + v__h52117, + v__h52207, + v__h52296, + v__h55675, + v__h55765, + v__h55854, + v__h56078, + v__h56168, + v__h56257, + v__h56486, + v__h56576, + v__h56665, + v__h60044, + v__h60134, + v__h60223, + v__h60447, + v__h60537, + v__h60626, + v__h60855, + v__h60945, + v__h61034, + v__h64413, + v__h64503, + v__h64592, + v__h64816, + v__h64906, + v__h64995, + v__h65224, + v__h65314, + v__h65403, + v__h68782, + v__h68872, + v__h68961, + v__h69185, + v__h69275, + v__h69364, + v__h69593, + v__h69683, + v__h69772, + v__h73151, + v__h73241, + v__h73330, + v__h73554, + v__h73644, + v__h73733, + v__h73962, + v__h74052, + v__h74141, + v__h78104, + v__h78692, + v__h78800, + v__h79379, + v__h79487, + v__h80066, + v__h80174, + v__h80753, + v__h80861, + v__h81440, + v__h81548, + v__h82127, + v__h82235, + v__h82814, + v__h82922, + v__h83501, + v__h83609, + v__h84188, + v__h84296, + v__h84875, + v__h84983, + v__h85562, + v__h85670, + v__h86249, + v__h86357, + v__h86936, + v__h87044, + v__h87623, + v__h87731, + v__h88310, + v__h95208, + v__h95279, + v__h95350, + v__h95421, + v__h95492, + v__h95563, + v__h95634, + v__h95705, + v__h95776, + v__h95847, + v__h95918, + v__h95989, + v__h96060, + v__h96131, + v__h96202; reg [31 : 0] CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744, - rtnData__h113157; - reg [7 : 0] put__h9199; - reg CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952, - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619, - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730, - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135; - wire [63 : 0] x_wget__h5217; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590, + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691, + rtnData__h110501; + reg CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639, + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044; + wire [63 : 0] x_wget__h5213; wire [49 : 0] _281474976710656_MINUS_timeServ_delSecond__q1, - x__h3692, - x__h4412, - x__h4640; - wire [47 : 0] x_f__h4839; - wire [32 : 0] IF_adminResp2F_notEmpty__321_THEN_adminResp2F__ETC___d2359; - wire [31 : 0] cpStatus__h77314, - crr_data__h77984, - toCount__h14143, - toCount__h18518, - toCount__h22887, - toCount__h27256, - toCount__h31625, - toCount__h35994, - toCount__h40363, - toCount__h44732, - toCount__h49101, - toCount__h53470, - toCount__h57839, - toCount__h62208, - toCount__h66577, - toCount__h70946, - toCount__h75315, - wciAddr__h79587, - wciAddr__h79655, - wciAddr__h79723, - wciAddr__h79791, - wciAddr__h79859, - wciAddr__h79927, - wciAddr__h79995, - wciAddr__h80063, - wciAddr__h80131, - wciAddr__h80199, - wciAddr__h80267, - wciAddr__h80335, - wciAddr__h80403, - wciAddr__h80471, - wciAddr__h80539, - x__h14303, - x__h18675, - x__h23044, - x__h27413, - x__h31782, - x__h36151, - x__h40520, - x__h44889, - x__h4706, - x__h49258, - x__h53627, - x__h57996, - x__h62365, - x__h66734, - x__h71103, - x__h75472, - x_addr__h99156, - x_data__h105345, - x_data__h105351, - x_data__h105396, - x_data__h105402, - x_data__h105447, - x_data__h105453, - x_data__h105498, - x_data__h105504, - x_data__h105549, - x_data__h105555, - x_data__h105600, - x_data__h105606, - x_data__h105651, - x_data__h105657, - x_data__h105702, - x_data__h105708, - x_data__h105753, - x_data__h105759, - x_data__h105804, - x_data__h105810, - x_data__h105855, - x_data__h105861, - x_data__h105906, - x_data__h105912, - x_data__h105957, - x_data__h105963, - x_data__h106008, - x_data__h106014, - x_data__h106059, - x_data__h106065; - wire [26 : 0] IF_wci_0_lastControlOp_30_BIT_3_31_THEN_wci_0__ETC___d345, - IF_wci_10_lastControlOp_730_BIT_3_731_THEN_wci_ETC___d1745, - IF_wci_11_lastControlOp_870_BIT_3_871_THEN_wci_ETC___d1885, - IF_wci_12_lastControlOp_010_BIT_3_011_THEN_wci_ETC___d2025, - IF_wci_13_lastControlOp_150_BIT_3_151_THEN_wci_ETC___d2165, - IF_wci_14_lastControlOp_290_BIT_3_291_THEN_wci_ETC___d2305, - IF_wci_1_lastControlOp_70_BIT_3_71_THEN_wci_1__ETC___d485, - IF_wci_2_lastControlOp_10_BIT_3_11_THEN_wci_2__ETC___d625, - IF_wci_3_lastControlOp_50_BIT_3_51_THEN_wci_3__ETC___d765, - IF_wci_4_lastControlOp_90_BIT_3_91_THEN_wci_4__ETC___d905, - IF_wci_5_lastControlOp_030_BIT_3_031_THEN_wci__ETC___d1045, - IF_wci_6_lastControlOp_170_BIT_3_171_THEN_wci__ETC___d1185, - IF_wci_7_lastControlOp_310_BIT_3_311_THEN_wci__ETC___d1325, - IF_wci_8_lastControlOp_450_BIT_3_451_THEN_wci__ETC___d1465, - IF_wci_9_lastControlOp_590_BIT_3_591_THEN_wci__ETC___d1605; - wire [23 : 0] bAddr__h113646, bAddr__h114105; + x__h3688, + x__h4408, + x__h4636; + wire [47 : 0] x_f__h4835; + wire [32 : 0] IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342; + wire [31 : 0] cpStatus__h74863, + crr_data__h75533, + toCount__h11692, + toCount__h16067, + toCount__h20436, + toCount__h24805, + toCount__h29174, + toCount__h33543, + toCount__h37912, + toCount__h42281, + toCount__h46650, + toCount__h51019, + toCount__h55388, + toCount__h59757, + toCount__h64126, + toCount__h68495, + toCount__h72864, + wciAddr__h77037, + wciAddr__h77105, + wciAddr__h77173, + wciAddr__h77241, + wciAddr__h77309, + wciAddr__h77377, + wciAddr__h77445, + wciAddr__h77513, + wciAddr__h77581, + wciAddr__h77649, + wciAddr__h77717, + wciAddr__h77785, + wciAddr__h77853, + wciAddr__h77921, + wciAddr__h77989, + x__h11852, + x__h16224, + x__h20593, + x__h24962, + x__h29331, + x__h33700, + x__h38069, + x__h42438, + x__h46807, + x__h4702, + x__h51176, + x__h55545, + x__h59914, + x__h64283, + x__h68652, + x__h73021, + x_addr__h96606, + x_data__h102795, + x_data__h102801, + x_data__h102846, + x_data__h102852, + x_data__h102897, + x_data__h102903, + x_data__h102948, + x_data__h102954, + x_data__h102999, + x_data__h103005, + x_data__h103050, + x_data__h103056, + x_data__h103101, + x_data__h103107, + x_data__h103152, + x_data__h103158, + x_data__h103203, + x_data__h103209, + x_data__h103254, + x_data__h103260, + x_data__h103305, + x_data__h103311, + x_data__h103356, + x_data__h103362, + x_data__h103407, + x_data__h103413, + x_data__h103458, + x_data__h103464, + x_data__h103509, + x_data__h103515; + wire [26 : 0] IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328, + IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728, + IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868, + IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008, + IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148, + IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288, + IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468, + IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608, + IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748, + IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888, + IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028, + IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168, + IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308, + IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448, + IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588; + wire [23 : 0] bAddr__h110990, bAddr__h111449; wire [21 : 0] _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2; - wire [14 : 0] x__h106938, x__h107487; - wire [5 : 0] x__h9243; - wire [4 : 0] x__h99158; - wire [3 : 0] _theResult_____1__h78175, - _theResult_____1__h78190, - wn___1__h79049, - wn__h78174; + wire [14 : 0] x__h104311, x__h104860; + wire [4 : 0] x__h96608; + wire [3 : 0] _theResult_____1__h75724, + _theResult_____1__h75739, + wn___1__h76499, + wn__h75723; wire [2 : 0] rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135; - wire IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5025, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5031, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5037, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5043, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5049, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5055, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5061, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5067, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5073, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5079, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5085, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5091, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5097, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5103, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5109, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5023, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5029, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5035, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5041, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5047, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5053, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5059, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5065, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5071, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5077, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5083, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5089, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5095, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5101, - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5107, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3671, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3675, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3679, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3683, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3687, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3691, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3695, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3699, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3703, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3707, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3711, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3715, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3719, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3723, - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3727, + wire IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636, IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39, - NOT_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_TH_ETC___d5114, - NOT_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_TH_ETC___d3732, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5024, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5030, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5036, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5042, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5048, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5054, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5060, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5066, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5072, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5078, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5084, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5090, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5096, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5102, - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5108, - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120, - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3779, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3792, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3833, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3848, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3949, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3961, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3974, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3984, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4026, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4038, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4049, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4059, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4101, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4113, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4124, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4134, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4176, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4188, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4199, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4209, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4251, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4263, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4274, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4284, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4326, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4338, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4349, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4359, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4401, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4413, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4424, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4434, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4476, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4488, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4499, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4509, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4551, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4563, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4574, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4584, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4626, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4638, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4649, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4659, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4701, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4713, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4724, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4734, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4776, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4788, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4799, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4809, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4851, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4863, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4874, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4884, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4926, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4938, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4949, - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4959, - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930, - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137, - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009, - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015, - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021, - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027, - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033, - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955, - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961, - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967, - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973, - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979, - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985, - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991, - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997, - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003, - cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_OR_cpRe_ETC___d2673, - cpReq_380_BITS_11_TO_4_383_EQ_0x50_637_OR_cpRe_ETC___d2768, - cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468, - cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2771, - cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2799, - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623, - cpReq_380_BITS_27_TO_4_466_ULT_0x1000___d2927, - cpReq_380_BITS_27_TO_4_466_ULT_0x100_467_AND_N_ETC___d2790, - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467, - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107, - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113, - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092, - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100, + NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023, + NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641, + NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017, + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029, + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868, + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839, + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046, + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918, + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924, + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930, + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936, + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942, + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864, + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870, + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876, + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882, + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888, + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894, + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900, + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906, + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912, + cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632, + cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438, + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594, + cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836, + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70, timeServ_refFromRise_3_ULE_199800000___d48, timeServ_refFromRise_3_ULT_200200000___d50, - wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248, - wci_0_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d269, - wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648, - wci_10_wciResponse_wget__640_BITS_33_TO_32_641_ETC___d1669, - wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788, - wci_11_wciResponse_wget__780_BITS_33_TO_32_781_ETC___d1809, - wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928, - wci_12_wciResponse_wget__920_BITS_33_TO_32_921_ETC___d1949, - wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068, - wci_13_wciResponse_wget__060_BITS_33_TO_32_061_ETC___d2089, - wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208, - wci_14_wciResponse_wget__200_BITS_33_TO_32_201_ETC___d2229, - wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388, - wci_1_wciResponse_wget__80_BITS_33_TO_32_81_EQ_ETC___d409, - wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528, - wci_2_wciResponse_wget__20_BITS_33_TO_32_21_EQ_ETC___d549, - wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668, - wci_3_wciResponse_wget__60_BITS_33_TO_32_61_EQ_ETC___d689, - wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808, - wci_4_wciResponse_wget__00_BITS_33_TO_32_01_EQ_ETC___d829, - wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948, - wci_5_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d969, - wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088, - wci_6_wciResponse_wget__080_BITS_33_TO_32_081__ETC___d1109, - wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228, - wci_7_wciResponse_wget__220_BITS_33_TO_32_221__ETC___d1249, - wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368, - wci_8_wciResponse_wget__360_BITS_33_TO_32_361__ETC___d1389, - wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508, - wci_9_wciResponse_wget__500_BITS_33_TO_32_501__ETC___d1529; + wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231, + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252, + wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631, + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652, + wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771, + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792, + wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911, + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932, + wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051, + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072, + wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191, + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212, + wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371, + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392, + wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511, + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532, + wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651, + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672, + wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791, + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812, + wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931, + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952, + wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071, + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092, + wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211, + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232, + wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351, + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372, + wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491, + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512; // output resets assign RST_N_wci_Vm_0 = wci_0_mReset_OUT_RST ; @@ -5255,12 +5192,6 @@ module mkOCCP(pciDevice, // value method led assign led = scratch24[1:0] ; - // value method upads_rts - assign upads_rts = bluart_pads_rts ; - - // value method upads_tx - assign upads_tx = bluart_pads_tx ; - // submodule adminResp1F FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp1F(.RST(RST_N), .CLK(CLK), @@ -5316,27 +5247,6 @@ module mkOCCP(pciDevice, .FULL_N(adminRespF_FULL_N), .EMPTY_N(adminRespF_EMPTY_N)); - // submodule bluart - mkBLUART bluart(.CLK(CLK), - .RST_N(RST_N), - .pads_cts_arg(bluart_pads_cts_arg), - .pads_rx_arg(bluart_pads_rx_arg), - .setClkDiv_put(bluart_setClkDiv_put), - .txChar_put(bluart_txChar_put), - .EN_setClkDiv_put(bluart_EN_setClkDiv_put), - .EN_txChar_put(bluart_EN_txChar_put), - .EN_rxChar_get(bluart_EN_rxChar_get), - .RDY_setClkDiv_put(), - .txLevel(bluart_txLevel), - .RDY_txLevel(), - .rxLevel(bluart_rxLevel), - .RDY_rxLevel(), - .RDY_txChar_put(bluart_RDY_txChar_put), - .rxChar_get(bluart_rxChar_get), - .RDY_rxChar_get(bluart_RDY_rxChar_get), - .pads_rts(bluart_pads_rts), - .pads_tx(bluart_pads_tx)); - // submodule cpReqF FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N), .CLK(CLK), @@ -5817,8 +5727,8 @@ module mkOCCP(pciDevice, assign WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T = cpReq[64:62] == 3'd1 && cpReq[11:4] == 8'h4C && !dispatched ; - // rule RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F = + // rule RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F = cpReq[64:62] == 3'd1 && cpReq[11:4] != 8'h20 && cpReq[11:4] != 8'h24 && cpReq[11:4] != 8'h28 && @@ -5829,15 +5739,13 @@ module mkOCCP(pciDevice, cpReq[11:4] != 8'h40 && cpReq[11:4] != 8'h44 && cpReq[11:4] != 8'h4C && - cpReq[11:4] != 8'h6C && - cpReq[11:4] != 8'h70 && !dispatched ; // rule RL_cpDispatch_F_T_T_T assign CAN_FIRE_RL_cpDispatch_F_T_T_T = cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && adminResp1F_FULL_N && !dispatched ; assign WILL_FIRE_RL_cpDispatch_F_T_T_T = @@ -5846,10 +5754,10 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_T_T assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T = cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && - cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_OR_cpRe_ETC___d2673 ; + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && + cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632 ; assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T = CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T && !WILL_FIRE_RL_responseAdminRd ; @@ -5857,9 +5765,9 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_T_F_T assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_T = cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && cpReq[11:4] == 8'h4C && adminResp2F_FULL_N && !dispatched ; @@ -5867,48 +5775,23 @@ module mkOCCP(pciDevice, CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_T && !WILL_FIRE_RL_responseAdminRd ; - // rule RL_cpDispatch_F_T_T_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T = - cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2771 && - !WILL_FIRE_RL_responseAdminRd ; - - // rule RL_cpDispatch_F_T_T_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T = - cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100_467_AND_N_ETC___d2790 && - !WILL_FIRE_RL_responseAdminRd ; - - // rule RL_cpDispatch_F_T_T_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F = + // rule RL_cpDispatch_F_T_T_F_T_F_F + assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_F = cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2799 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && + NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712 ; + assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F = + CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_F && !WILL_FIRE_RL_responseAdminRd ; - // rule RL_init_uart_text - assign WILL_FIRE_RL_init_uart_text = bluart_RDY_txChar_put && !uartInited ; - - // rule RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T = - cpReq[64:62] == 3'd1 && cpReq[11:4] == 8'h6C && !dispatched ; - - // rule RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T = - cpReq[64:62] == 3'd1 && cpReq[11:4] == 8'h70 && - bluart_RDY_txChar_put && - !dispatched && - !WILL_FIRE_RL_init_uart_text ; - // rule RL_cpDispatch_F_T_T_F_F assign CAN_FIRE_RL_cpDispatch_F_T_T_F_F = cpReq[64:62] == 3'd2 && - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - !cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + !cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && adminResp3F_FULL_N && !dispatched ; assign WILL_FIRE_RL_cpDispatch_F_T_T_F_F = @@ -5918,443 +5801,443 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_T_F_T = cpReq[64:62] == 3'd2 && - !cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - cpReq_380_BITS_27_TO_4_466_ULT_0x1000___d2927 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 && !dispatched && !WILL_FIRE_RL_responseAdminRd ; // rule RL_cpDispatch_F_T_F_F assign CAN_FIRE_RL_cpDispatch_F_T_F_F = cpReq[64:62] == 3'd2 && - !cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_27_TO_4_466_ULT_0x1000___d2927 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 && (rom_serverAdapter_cnt ^ 3'h4) < 3'd7 && !dispatched ; // rule RL_cpDispatch_F_F_T_E0_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd2 && !wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 && !dispatched ; // rule RL_cpDispatch_F_F_T_E0_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E0_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E0_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E1_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd2 && !wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 && !dispatched ; // rule RL_cpDispatch_F_F_T_E1_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E1_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E1_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E2_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd2 && !wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 && !dispatched ; // rule RL_cpDispatch_F_F_T_E2_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E2_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E2_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E3_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd2 && !wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 && !dispatched ; // rule RL_cpDispatch_F_F_T_E3_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E3_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E3_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E4_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd2 && !wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 && !dispatched ; // rule RL_cpDispatch_F_F_T_E4_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E4_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E4_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E5_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd2 && !wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 && !dispatched ; // rule RL_cpDispatch_F_F_T_E5_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E5_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E5_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E6_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd2 && !wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 && !dispatched ; // rule RL_cpDispatch_F_F_T_E6_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E6_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E6_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E7_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd2 && !wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 && !dispatched ; // rule RL_cpDispatch_F_F_T_E7_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E7_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E7_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E8_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd2 && !wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 && !dispatched ; // rule RL_cpDispatch_F_F_T_E8_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E8_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E8_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E9_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd2 && !wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 && !dispatched ; // rule RL_cpDispatch_F_F_T_E9_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E9_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E9_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E10_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd2 && !wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 && !dispatched ; // rule RL_cpDispatch_F_F_T_E10_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E10_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E10_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E11_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd2 && !wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 && !dispatched ; // rule RL_cpDispatch_F_F_T_E11_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E11_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E11_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E12_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd2 && !wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 && !dispatched ; // rule RL_cpDispatch_F_F_T_E12_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E12_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E12_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E13_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd2 && !wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 && !dispatched ; // rule RL_cpDispatch_F_F_T_E13_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E13_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E13_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_E14_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd2 && !wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 && !dispatched ; // rule RL_cpDispatch_F_F_T_E14_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; // rule RL_cpDispatch_F_F_T_E14_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_E14_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; // rule RL_cpDispatch_F_F_T_OOB assign WILL_FIRE_RL_cpDispatch_F_F_T_OOB = cpReq[64:62] == 3'd3 && - NOT_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_TH_ETC___d3732 ; + NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641 ; // rule RL_cpDispatch_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_T = @@ -6363,868 +6246,868 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_F_F_E0_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3792 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701 ; // rule RL_cpDispatch_F_F_F_F_E0_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3848 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757 ; // rule RL_cpDispatch_F_F_F_F_E0_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E1_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3961 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870 ; // rule RL_cpDispatch_F_F_F_F_E1_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3984 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893 ; // rule RL_cpDispatch_F_F_F_F_E1_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E2_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4038 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947 ; // rule RL_cpDispatch_F_F_F_F_E2_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4059 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968 ; // rule RL_cpDispatch_F_F_F_F_E2_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E3_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4113 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022 ; // rule RL_cpDispatch_F_F_F_F_E3_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4134 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043 ; // rule RL_cpDispatch_F_F_F_F_E3_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E4_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4188 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097 ; // rule RL_cpDispatch_F_F_F_F_E4_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4209 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118 ; // rule RL_cpDispatch_F_F_F_F_E4_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E5_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4263 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172 ; // rule RL_cpDispatch_F_F_F_F_E5_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4284 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193 ; // rule RL_cpDispatch_F_F_F_F_E5_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E6_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4338 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247 ; // rule RL_cpDispatch_F_F_F_F_E6_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4359 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268 ; // rule RL_cpDispatch_F_F_F_F_E6_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E7_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4413 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322 ; // rule RL_cpDispatch_F_F_F_F_E7_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4434 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343 ; // rule RL_cpDispatch_F_F_F_F_E7_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E8_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4488 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397 ; // rule RL_cpDispatch_F_F_F_F_E8_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4509 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418 ; // rule RL_cpDispatch_F_F_F_F_E8_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E9_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4563 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472 ; // rule RL_cpDispatch_F_F_F_F_E9_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4584 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493 ; // rule RL_cpDispatch_F_F_F_F_E9_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E10_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4638 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547 ; // rule RL_cpDispatch_F_F_F_F_E10_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4659 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568 ; // rule RL_cpDispatch_F_F_F_F_E10_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E11_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4713 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622 ; // rule RL_cpDispatch_F_F_F_F_E11_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4734 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643 ; // rule RL_cpDispatch_F_F_F_F_E11_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E12_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4788 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697 ; // rule RL_cpDispatch_F_F_F_F_E12_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4809 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718 ; // rule RL_cpDispatch_F_F_F_F_E12_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E13_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4863 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772 ; // rule RL_cpDispatch_F_F_F_F_E13_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4884 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793 ; // rule RL_cpDispatch_F_F_F_F_E13_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_E14_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4938 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847 ; // rule RL_cpDispatch_F_F_F_F_E14_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4959 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868 ; // rule RL_cpDispatch_F_F_F_F_E14_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 ; + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && - NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 ; + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; // rule RL_cpDispatch_F_F_F_F_OOB assign WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - NOT_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_TH_ETC___d5114 ; + NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023 ; // rule RL_completeWorkerWrite assign WILL_FIRE_RL_completeWorkerWrite = - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 && + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 && cpReq[64:62] == 3'd3 && !WILL_FIRE_RL_cpDispatch_F_F_T_OOB && !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F && @@ -7233,12 +7116,12 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T && @@ -7248,37 +7131,37 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F && @@ -7286,8 +7169,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F && @@ -7309,11 +7192,11 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T && @@ -7323,8 +7206,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T && @@ -7340,8 +7223,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F && @@ -7351,13 +7234,13 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F && @@ -7366,7 +7249,7 @@ module mkOCCP(pciDevice, // rule RL_completeWorkerRead assign WILL_FIRE_RL_completeWorkerRead = cpRespF_FULL_N && - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 && + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 && cpReq[64:62] != 3'd0 && cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -7379,57 +7262,57 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T && @@ -7440,12 +7323,13 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F && @@ -7454,8 +7338,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T && @@ -7464,15 +7348,14 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T && @@ -7481,9 +7364,9 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T && @@ -7503,8 +7386,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T && !WILL_FIRE_RL_responseAdminRd ; @@ -7535,693 +7418,693 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_E0_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E0_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E0_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd2 && wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 && !dispatched ; // rule RL_cpDispatch_F_F_T_E0_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E0_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E0_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3779 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688 ; // rule RL_cpDispatch_F_F_F_F_E0_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3833 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742 ; // rule RL_cpDispatch_F_F_T_E1_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E1_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E1_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd2 && wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 && !dispatched ; // rule RL_cpDispatch_F_F_T_E1_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E1_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E1_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3949 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858 ; // rule RL_cpDispatch_F_F_F_F_E1_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3974 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883 ; // rule RL_cpDispatch_F_F_T_E2_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E2_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E2_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd2 && wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 && !dispatched ; // rule RL_cpDispatch_F_F_T_E2_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E2_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E2_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4026 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935 ; // rule RL_cpDispatch_F_F_F_F_E2_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4049 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958 ; // rule RL_cpDispatch_F_F_T_E3_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E3_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E3_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd2 && wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 && !dispatched ; // rule RL_cpDispatch_F_F_T_E3_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E3_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E3_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4101 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010 ; // rule RL_cpDispatch_F_F_F_F_E3_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4124 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033 ; // rule RL_cpDispatch_F_F_T_E4_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E4_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E4_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd2 && wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 && !dispatched ; // rule RL_cpDispatch_F_F_T_E4_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E4_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E4_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4176 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085 ; // rule RL_cpDispatch_F_F_F_F_E4_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4199 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108 ; // rule RL_cpDispatch_F_F_T_E5_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E5_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E5_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd2 && wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 && !dispatched ; // rule RL_cpDispatch_F_F_T_E5_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E5_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E5_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4251 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160 ; // rule RL_cpDispatch_F_F_F_F_E5_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4274 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183 ; // rule RL_cpDispatch_F_F_T_E6_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E6_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E6_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd2 && wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 && !dispatched ; // rule RL_cpDispatch_F_F_T_E6_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E6_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E6_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4326 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235 ; // rule RL_cpDispatch_F_F_F_F_E6_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4349 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258 ; // rule RL_cpDispatch_F_F_T_E7_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E7_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E7_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd2 && wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 && !dispatched ; // rule RL_cpDispatch_F_F_T_E7_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E7_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E7_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4401 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310 ; // rule RL_cpDispatch_F_F_F_F_E7_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4424 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333 ; // rule RL_cpDispatch_F_F_T_E8_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E8_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E8_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd2 && wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 && !dispatched ; // rule RL_cpDispatch_F_F_T_E8_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E8_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E8_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4476 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385 ; // rule RL_cpDispatch_F_F_F_F_E8_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4499 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408 ; // rule RL_cpDispatch_F_F_T_E9_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E9_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E9_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd2 && wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 && !dispatched ; // rule RL_cpDispatch_F_F_T_E9_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E9_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E9_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4551 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460 ; // rule RL_cpDispatch_F_F_F_F_E9_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4574 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483 ; // rule RL_cpDispatch_F_F_T_E10_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E10_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E10_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd2 && wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 && !dispatched ; // rule RL_cpDispatch_F_F_T_E10_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E10_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E10_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4626 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535 ; // rule RL_cpDispatch_F_F_F_F_E10_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4649 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558 ; // rule RL_cpDispatch_F_F_T_E11_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E11_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E11_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd2 && wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 && !dispatched ; // rule RL_cpDispatch_F_F_T_E11_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E11_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E11_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4701 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610 ; // rule RL_cpDispatch_F_F_F_F_E11_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4724 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633 ; // rule RL_cpDispatch_F_F_T_E12_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E12_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E12_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd2 && wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 && !dispatched ; // rule RL_cpDispatch_F_F_T_E12_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E12_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E12_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4776 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685 ; // rule RL_cpDispatch_F_F_F_F_E12_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4799 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708 ; // rule RL_cpDispatch_F_F_T_E13_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E13_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E13_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd2 && wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 && !dispatched ; // rule RL_cpDispatch_F_F_T_E13_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E13_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E13_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4851 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760 ; // rule RL_cpDispatch_F_F_F_F_E13_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4874 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783 ; // rule RL_cpDispatch_F_F_T_E14_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; // rule RL_cpDispatch_F_F_T_E14_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; // rule RL_cpDispatch_F_F_T_E14_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd2 && wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 && !dispatched ; // rule RL_cpDispatch_F_F_T_E14_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; // rule RL_cpDispatch_F_F_T_E14_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h78175 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 ; + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; // rule RL_cpDispatch_F_F_F_F_E14_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4926 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835 ; // rule RL_cpDispatch_F_F_F_F_E14_F_T_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T = cpReq[64:62] != 3'd1 && - NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4949 ; + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858 ; // rule RL_responseAdminRd assign WILL_FIRE_RL_responseAdminRd = adminRespF_EMPTY_N && cpRespF_FULL_N ; @@ -8229,7 +8112,7 @@ module mkOCCP(pciDevice, // rule RL_wci_0_wrkBusy assign WILL_FIRE_RL_wci_0_wrkBusy = ((wci_0_wciResponse_wget[33:32] == 2'd0) ? - wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 || + wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || wci_0_respF_FULL_N : wci_0_respF_FULL_N) && wci_0_busy ; @@ -8253,7 +8136,7 @@ module mkOCCP(pciDevice, // rule RL_wci_1_wrkBusy assign WILL_FIRE_RL_wci_1_wrkBusy = ((wci_1_wciResponse_wget[33:32] == 2'd0) ? - wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 || + wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || wci_1_respF_FULL_N : wci_1_respF_FULL_N) && wci_1_busy ; @@ -8277,7 +8160,7 @@ module mkOCCP(pciDevice, // rule RL_wci_2_wrkBusy assign WILL_FIRE_RL_wci_2_wrkBusy = ((wci_2_wciResponse_wget[33:32] == 2'd0) ? - wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 || + wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || wci_2_respF_FULL_N : wci_2_respF_FULL_N) && wci_2_busy ; @@ -8301,7 +8184,7 @@ module mkOCCP(pciDevice, // rule RL_wci_3_wrkBusy assign WILL_FIRE_RL_wci_3_wrkBusy = ((wci_3_wciResponse_wget[33:32] == 2'd0) ? - wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 || + wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || wci_3_respF_FULL_N : wci_3_respF_FULL_N) && wci_3_busy ; @@ -8325,7 +8208,7 @@ module mkOCCP(pciDevice, // rule RL_wci_4_wrkBusy assign WILL_FIRE_RL_wci_4_wrkBusy = ((wci_4_wciResponse_wget[33:32] == 2'd0) ? - wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 || + wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || wci_4_respF_FULL_N : wci_4_respF_FULL_N) && wci_4_busy ; @@ -8349,7 +8232,7 @@ module mkOCCP(pciDevice, // rule RL_wci_5_wrkBusy assign WILL_FIRE_RL_wci_5_wrkBusy = ((wci_5_wciResponse_wget[33:32] == 2'd0) ? - wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 || + wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || wci_5_respF_FULL_N : wci_5_respF_FULL_N) && wci_5_busy ; @@ -8373,7 +8256,7 @@ module mkOCCP(pciDevice, // rule RL_wci_6_wrkBusy assign WILL_FIRE_RL_wci_6_wrkBusy = ((wci_6_wciResponse_wget[33:32] == 2'd0) ? - wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 || + wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || wci_6_respF_FULL_N : wci_6_respF_FULL_N) && wci_6_busy ; @@ -8397,7 +8280,7 @@ module mkOCCP(pciDevice, // rule RL_wci_7_wrkBusy assign WILL_FIRE_RL_wci_7_wrkBusy = ((wci_7_wciResponse_wget[33:32] == 2'd0) ? - wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 || + wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || wci_7_respF_FULL_N : wci_7_respF_FULL_N) && wci_7_busy ; @@ -8421,7 +8304,7 @@ module mkOCCP(pciDevice, // rule RL_wci_8_wrkBusy assign WILL_FIRE_RL_wci_8_wrkBusy = ((wci_8_wciResponse_wget[33:32] == 2'd0) ? - wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 || + wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || wci_8_respF_FULL_N : wci_8_respF_FULL_N) && wci_8_busy ; @@ -8445,7 +8328,7 @@ module mkOCCP(pciDevice, // rule RL_wci_9_wrkBusy assign WILL_FIRE_RL_wci_9_wrkBusy = ((wci_9_wciResponse_wget[33:32] == 2'd0) ? - wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 || + wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || wci_9_respF_FULL_N : wci_9_respF_FULL_N) && wci_9_busy ; @@ -8469,7 +8352,7 @@ module mkOCCP(pciDevice, // rule RL_wci_10_wrkBusy assign WILL_FIRE_RL_wci_10_wrkBusy = ((wci_10_wciResponse_wget[33:32] == 2'd0) ? - wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 || + wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || wci_10_respF_FULL_N : wci_10_respF_FULL_N) && wci_10_busy ; @@ -8493,7 +8376,7 @@ module mkOCCP(pciDevice, // rule RL_wci_11_wrkBusy assign WILL_FIRE_RL_wci_11_wrkBusy = ((wci_11_wciResponse_wget[33:32] == 2'd0) ? - wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 || + wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || wci_11_respF_FULL_N : wci_11_respF_FULL_N) && wci_11_busy ; @@ -8517,7 +8400,7 @@ module mkOCCP(pciDevice, // rule RL_wci_12_wrkBusy assign WILL_FIRE_RL_wci_12_wrkBusy = ((wci_12_wciResponse_wget[33:32] == 2'd0) ? - wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 || + wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || wci_12_respF_FULL_N : wci_12_respF_FULL_N) && wci_12_busy ; @@ -8541,7 +8424,7 @@ module mkOCCP(pciDevice, // rule RL_wci_13_wrkBusy assign WILL_FIRE_RL_wci_13_wrkBusy = ((wci_13_wciResponse_wget[33:32] == 2'd0) ? - wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 || + wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || wci_13_respF_FULL_N : wci_13_respF_FULL_N) && wci_13_busy ; @@ -8565,7 +8448,7 @@ module mkOCCP(pciDevice, // rule RL_wci_14_wrkBusy assign WILL_FIRE_RL_wci_14_wrkBusy = ((wci_14_wciResponse_wget[33:32] == 2'd0) ? - wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 || + wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || wci_14_respF_FULL_N : wci_14_respF_FULL_N) && wci_14_busy ; @@ -8587,12 +8470,9 @@ module mkOCCP(pciDevice, MUX_wci_14_busy_write_1__SEL_2 ; // inputs to muxes for submodule ports - assign MUX_adminResp2F_enq_1__SEL_1 = - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T ; assign MUX_wci_0_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_0_wrkBusy && - (!wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 || + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || wci_0_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_0_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || @@ -8608,14 +8488,14 @@ module mkOCCP(pciDevice, wci_0_wciResponse_wget[33:32] == 2'd2 && (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || wci_0_reqPend == 2'd3) ; - assign MUX_wci_0_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_0_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r ; assign MUX_wci_0_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_0_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_0_wrkBusy && - wci_0_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d269 ; + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 ; assign MUX_wci_0_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || @@ -8630,7 +8510,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F ; assign MUX_wci_10_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_10_wrkBusy && - (!wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 || + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || wci_10_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_10_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || @@ -8653,7 +8533,7 @@ module mkOCCP(pciDevice, wci_10_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_10_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_10_wrkBusy && - wci_10_wciResponse_wget__640_BITS_33_TO_32_641_ETC___d1669 ; + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 ; assign MUX_wci_10_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || @@ -8668,7 +8548,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F ; assign MUX_wci_11_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_11_wrkBusy && - (!wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 || + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || wci_11_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_11_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || @@ -8691,7 +8571,7 @@ module mkOCCP(pciDevice, wci_11_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_11_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_11_wrkBusy && - wci_11_wciResponse_wget__780_BITS_33_TO_32_781_ETC___d1809 ; + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 ; assign MUX_wci_11_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || @@ -8706,7 +8586,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F ; assign MUX_wci_12_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_12_wrkBusy && - (!wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 || + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || wci_12_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_12_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || @@ -8729,7 +8609,7 @@ module mkOCCP(pciDevice, wci_12_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_12_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_12_wrkBusy && - wci_12_wciResponse_wget__920_BITS_33_TO_32_921_ETC___d1949 ; + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 ; assign MUX_wci_12_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || @@ -8744,7 +8624,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F ; assign MUX_wci_13_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_13_wrkBusy && - (!wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 || + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || wci_13_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_13_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || @@ -8767,7 +8647,7 @@ module mkOCCP(pciDevice, wci_13_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_13_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_13_wrkBusy && - wci_13_wciResponse_wget__060_BITS_33_TO_32_061_ETC___d2089 ; + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 ; assign MUX_wci_13_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || @@ -8782,7 +8662,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F ; assign MUX_wci_14_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_14_wrkBusy && - (!wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 || + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || wci_14_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_14_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || @@ -8805,7 +8685,7 @@ module mkOCCP(pciDevice, wci_14_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_14_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_14_wrkBusy && - wci_14_wciResponse_wget__200_BITS_33_TO_32_201_ETC___d2229 ; + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 ; assign MUX_wci_14_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || @@ -8820,7 +8700,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F ; assign MUX_wci_1_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_1_wrkBusy && - (!wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 || + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || wci_1_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_1_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || @@ -8836,14 +8716,14 @@ module mkOCCP(pciDevice, wci_1_wciResponse_wget[33:32] == 2'd2 && (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || wci_1_reqPend == 2'd3) ; - assign MUX_wci_1_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_1_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r ; assign MUX_wci_1_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_1_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_1_wrkBusy && - wci_1_wciResponse_wget__80_BITS_33_TO_32_81_EQ_ETC___d409 ; + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 ; assign MUX_wci_1_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || @@ -8858,7 +8738,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F ; assign MUX_wci_2_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_2_wrkBusy && - (!wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 || + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || wci_2_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_2_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || @@ -8874,14 +8754,14 @@ module mkOCCP(pciDevice, wci_2_wciResponse_wget[33:32] == 2'd2 && (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || wci_2_reqPend == 2'd3) ; - assign MUX_wci_2_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_2_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r ; assign MUX_wci_2_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_2_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_2_wrkBusy && - wci_2_wciResponse_wget__20_BITS_33_TO_32_21_EQ_ETC___d549 ; + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 ; assign MUX_wci_2_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || @@ -8896,7 +8776,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F ; assign MUX_wci_3_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_3_wrkBusy && - (!wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 || + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || wci_3_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_3_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || @@ -8912,14 +8792,14 @@ module mkOCCP(pciDevice, wci_3_wciResponse_wget[33:32] == 2'd2 && (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || wci_3_reqPend == 2'd3) ; - assign MUX_wci_3_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_3_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r ; assign MUX_wci_3_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_3_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_3_wrkBusy && - wci_3_wciResponse_wget__60_BITS_33_TO_32_61_EQ_ETC___d689 ; + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 ; assign MUX_wci_3_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || @@ -8934,7 +8814,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F ; assign MUX_wci_4_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_4_wrkBusy && - (!wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 || + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || wci_4_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_4_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || @@ -8950,14 +8830,14 @@ module mkOCCP(pciDevice, wci_4_wciResponse_wget[33:32] == 2'd2 && (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || wci_4_reqPend == 2'd3) ; - assign MUX_wci_4_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_4_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r ; assign MUX_wci_4_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_4_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_4_wrkBusy && - wci_4_wciResponse_wget__00_BITS_33_TO_32_01_EQ_ETC___d829 ; + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 ; assign MUX_wci_4_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || @@ -8972,7 +8852,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F ; assign MUX_wci_5_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_5_wrkBusy && - (!wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 || + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || wci_5_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_5_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || @@ -8988,14 +8868,14 @@ module mkOCCP(pciDevice, wci_5_wciResponse_wget[33:32] == 2'd2 && (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || wci_5_reqPend == 2'd3) ; - assign MUX_wci_5_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_5_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r ; assign MUX_wci_5_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_5_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_5_wrkBusy && - wci_5_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d969 ; + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 ; assign MUX_wci_5_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || @@ -9010,7 +8890,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F ; assign MUX_wci_6_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_6_wrkBusy && - (!wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 || + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || wci_6_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_6_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || @@ -9026,14 +8906,14 @@ module mkOCCP(pciDevice, wci_6_wciResponse_wget[33:32] == 2'd2 && (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || wci_6_reqPend == 2'd3) ; - assign MUX_wci_6_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_6_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r ; assign MUX_wci_6_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_6_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_6_wrkBusy && - wci_6_wciResponse_wget__080_BITS_33_TO_32_081__ETC___d1109 ; + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 ; assign MUX_wci_6_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || @@ -9048,7 +8928,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F ; assign MUX_wci_7_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_7_wrkBusy && - (!wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 || + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || wci_7_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_7_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || @@ -9064,14 +8944,14 @@ module mkOCCP(pciDevice, wci_7_wciResponse_wget[33:32] == 2'd2 && (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || wci_7_reqPend == 2'd3) ; - assign MUX_wci_7_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_7_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r ; assign MUX_wci_7_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_7_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_7_wrkBusy && - wci_7_wciResponse_wget__220_BITS_33_TO_32_221__ETC___d1249 ; + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 ; assign MUX_wci_7_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || @@ -9086,7 +8966,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F ; assign MUX_wci_8_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_8_wrkBusy && - (!wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 || + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || wci_8_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_8_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || @@ -9102,14 +8982,14 @@ module mkOCCP(pciDevice, wci_8_wciResponse_wget[33:32] == 2'd2 && (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || wci_8_reqPend == 2'd3) ; - assign MUX_wci_8_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_8_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r ; assign MUX_wci_8_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_8_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_8_wrkBusy && - wci_8_wciResponse_wget__360_BITS_33_TO_32_361__ETC___d1389 ; + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 ; assign MUX_wci_8_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || @@ -9124,7 +9004,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F ; assign MUX_wci_9_busy_write_1__SEL_1 = WILL_FIRE_RL_wci_9_wrkBusy && - (!wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 || + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || wci_9_wciResponse_wget[33:32] != 2'd0) ; assign MUX_wci_9_busy_write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || @@ -9140,14 +9020,14 @@ module mkOCCP(pciDevice, wci_9_wciResponse_wget[33:32] == 2'd2 && (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || wci_9_reqPend == 2'd3) ; - assign MUX_wci_9_reqF_q_0_write_1__SEL_2 = + assign MUX_wci_9_reqF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r ; assign MUX_wci_9_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] != 2'd0 ; assign MUX_wci_9_reqTO_write_1__SEL_1 = WILL_FIRE_RL_wci_9_wrkBusy && - wci_9_wciResponse_wget__500_BITS_33_TO_32_501__ETC___d1529 ; + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 ; assign MUX_wci_9_respF_enq_1__SEL_6 = WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || @@ -9438,9 +9318,6 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_completeWorkerRead || WILL_FIRE_RL_completeWorkerWrite ; assign MUX_adminResp2F_enq_1__VAL_1 = - { 1'd1, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 } ; - assign MUX_adminResp2F_enq_1__VAL_2 = { cpReq[11:4] == 8'h30 || cpReq[11:4] == 8'h34 || cpReq[11:4] == 8'h38 || cpReq[11:4] == 8'h3C || @@ -9450,34 +9327,19 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'h4C || cpReq[11:4] == 8'h50 || cpReq[11:4] == 8'h54 || - cpReq[11:4] == 8'h60 || - cpReq[11:4] == 8'h64 || - cpReq[11:4] == 8'h68 || cpReq[11:4] == 8'h7C || cpReq[11:4] == 8'h80 || cpReq[11:4] == 8'h84, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; + assign MUX_adminResp2F_enq_1__VAL_2 = + { 1'd1, + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; assign MUX_adminResp2F_enq_1__VAL_3 = { cpReq[11:4] == 8'h50 || cpReq[11:4] == 8'h54 || - cpReq[11:4] == 8'h60 || - cpReq[11:4] == 8'h64 || - cpReq[11:4] == 8'h68 || cpReq[11:4] == 8'h7C || cpReq[11:4] == 8'h80 || cpReq[11:4] == 8'h84, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 } ; - assign MUX_adminResp2F_enq_1__VAL_4 = - { cpReq[11:4] == 8'h7C || cpReq[11:4] == 8'h80 || - cpReq[11:4] == 8'h84, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 } ; - always@(uartTxtP or put__h9199) - begin - case (uartTxtP) - 6'd0, 6'd42: MUX_bluart_txChar_put_1__VAL_2 = 8'h0D; - 6'd1, 6'd43: MUX_bluart_txChar_put_1__VAL_2 = 8'h0A; - default: MUX_bluart_txChar_put_1__VAL_2 = put__h9199; - endcase - end + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; assign MUX_cpReq_write_1__VAL_4 = cpReqF_D_OUT[58] ? { (cpReqF_D_OUT[25:18] == 8'd0) ? 3'd2 : 3'd4, @@ -9486,16 +9348,16 @@ module mkOCCP(pciDevice, 2'd0 : ((cpReqF_D_OUT[25:22] == 4'd0) ? 2'd1 : 2'd2), cpReqF_D_OUT[33:26], - bAddr__h114105, + bAddr__h111449, cpReqF_D_OUT[3:0] } : { (cpReqF_D_OUT[57:50] == 8'd0) ? 5'd4 : ((cpReqF_D_OUT[57:54] == 4'd0) ? 5'd13 : 5'd14), cpReqF_D_OUT[31:0], - bAddr__h113646, + bAddr__h110990, cpReqF_D_OUT[35:32] } ; - assign MUX_cpRespF_enq_1__VAL_1 = { seqTag, crr_data__h77984 } ; - assign MUX_cpRespF_enq_1__VAL_2 = { cpReq[35:28], rtnData__h113157 } ; + assign MUX_cpRespF_enq_1__VAL_1 = { seqTag, crr_data__h75533 } ; + assign MUX_cpRespF_enq_1__VAL_2 = { cpReq[35:28], rtnData__h110501 } ; assign MUX_readCntReg_write_1__VAL_2 = readCntReg + 32'd1 ; always@(wci_0_reqPend or wci_0_reqERR) begin @@ -9520,10 +9382,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_0_reqF_cntr_r_write_1__VAL_1 = wci_0_reqF_cntr_r + 1'd1 ; assign MUX_wci_0_reqF_cntr_r_write_1__VAL_2 = wci_0_reqF_cntr_r - 1'd1 ; - assign MUX_wci_0_reqF_q_0_write_1__VAL_1 = - wci_0_reqF_cntr_r ? - MUX_wci_0_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or @@ -9533,24 +9391,28 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_2 = + MUX_wci_0_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_2 = + MUX_wci_0_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_2 = + MUX_wci_0_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_0_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_0_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_0_reqF_q_0_write_1__VAL_2 = + wci_0_reqF_cntr_r ? + MUX_wci_0_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_1 = - { 8'd79, x_addr__h99156, 32'hAAAAAAAA } ; + { 8'd79, x_addr__h96606, 32'hAAAAAAAA } ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79587, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77037, cpReq[59:28] } ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79587, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77037, 32'hAAAAAAAA } ; always@(wci_0_reqPend or wci_0_reqTO) begin case (wci_0_reqPend) @@ -9566,13 +9428,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_0_wciResponse_wget ; assign MUX_wci_0_respF_enq_1__VAL_2 = { 2'd1, wci_0_wStatus } ; - assign MUX_wci_0_respF_enq_1__VAL_3 = { 2'd1, x_data__h105345 } ; - assign MUX_wci_0_respF_enq_1__VAL_4 = { 2'd1, x_data__h105351 } ; + assign MUX_wci_0_respF_enq_1__VAL_3 = { 2'd1, x_data__h102795 } ; + assign MUX_wci_0_respF_enq_1__VAL_4 = { 2'd1, x_data__h102801 } ; assign MUX_wci_0_respF_enq_1__VAL_5 = { 22'd1048576, wci_0_pageWindow } ; assign MUX_wci_0_respTimr_write_1__VAL_2 = (wci_0_wciResponse_wget[33:32] == 2'd0) ? - (wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 ? - x__h14303 : + (wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 ? + x__h11852 : 32'd0) : 32'd0 ; always@(wci_10_reqPend or wci_10_reqERR) @@ -9625,9 +9487,9 @@ module mkOCCP(pciDevice, MUX_wci_10_reqF_q_0_write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_10_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80267, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77717, cpReq[59:28] } ; assign MUX_wci_10_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80267, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77717, 32'hAAAAAAAA } ; always@(wci_10_reqPend or wci_10_reqTO) begin case (wci_10_reqPend) @@ -9643,13 +9505,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_10_wciResponse_wget ; assign MUX_wci_10_respF_enq_1__VAL_2 = { 2'd1, wci_10_wStatus } ; - assign MUX_wci_10_respF_enq_1__VAL_3 = { 2'd1, x_data__h105855 } ; - assign MUX_wci_10_respF_enq_1__VAL_4 = { 2'd1, x_data__h105861 } ; + assign MUX_wci_10_respF_enq_1__VAL_3 = { 2'd1, x_data__h103305 } ; + assign MUX_wci_10_respF_enq_1__VAL_4 = { 2'd1, x_data__h103311 } ; assign MUX_wci_10_respF_enq_1__VAL_5 = { 22'd1048576, wci_10_pageWindow } ; assign MUX_wci_10_respTimr_write_1__VAL_2 = (wci_10_wciResponse_wget[33:32] == 2'd0) ? - (wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 ? - x__h57996 : + (wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 ? + x__h55545 : 32'd0) : 32'd0 ; always@(wci_11_reqPend or wci_11_reqERR) @@ -9702,9 +9564,9 @@ module mkOCCP(pciDevice, MUX_wci_11_reqF_q_0_write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_11_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80335, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77785, cpReq[59:28] } ; assign MUX_wci_11_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80335, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77785, 32'hAAAAAAAA } ; always@(wci_11_reqPend or wci_11_reqTO) begin case (wci_11_reqPend) @@ -9720,13 +9582,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_11_wciResponse_wget ; assign MUX_wci_11_respF_enq_1__VAL_2 = { 2'd1, wci_11_wStatus } ; - assign MUX_wci_11_respF_enq_1__VAL_3 = { 2'd1, x_data__h105906 } ; - assign MUX_wci_11_respF_enq_1__VAL_4 = { 2'd1, x_data__h105912 } ; + assign MUX_wci_11_respF_enq_1__VAL_3 = { 2'd1, x_data__h103356 } ; + assign MUX_wci_11_respF_enq_1__VAL_4 = { 2'd1, x_data__h103362 } ; assign MUX_wci_11_respF_enq_1__VAL_5 = { 22'd1048576, wci_11_pageWindow } ; assign MUX_wci_11_respTimr_write_1__VAL_2 = (wci_11_wciResponse_wget[33:32] == 2'd0) ? - (wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 ? - x__h62365 : + (wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 ? + x__h59914 : 32'd0) : 32'd0 ; always@(wci_12_reqPend or wci_12_reqERR) @@ -9779,9 +9641,9 @@ module mkOCCP(pciDevice, MUX_wci_12_reqF_q_0_write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_12_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80403, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77853, cpReq[59:28] } ; assign MUX_wci_12_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80403, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77853, 32'hAAAAAAAA } ; always@(wci_12_reqPend or wci_12_reqTO) begin case (wci_12_reqPend) @@ -9797,13 +9659,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_12_wciResponse_wget ; assign MUX_wci_12_respF_enq_1__VAL_2 = { 2'd1, wci_12_wStatus } ; - assign MUX_wci_12_respF_enq_1__VAL_3 = { 2'd1, x_data__h105957 } ; - assign MUX_wci_12_respF_enq_1__VAL_4 = { 2'd1, x_data__h105963 } ; + assign MUX_wci_12_respF_enq_1__VAL_3 = { 2'd1, x_data__h103407 } ; + assign MUX_wci_12_respF_enq_1__VAL_4 = { 2'd1, x_data__h103413 } ; assign MUX_wci_12_respF_enq_1__VAL_5 = { 22'd1048576, wci_12_pageWindow } ; assign MUX_wci_12_respTimr_write_1__VAL_2 = (wci_12_wciResponse_wget[33:32] == 2'd0) ? - (wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 ? - x__h66734 : + (wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 ? + x__h64283 : 32'd0) : 32'd0 ; always@(wci_13_reqPend or wci_13_reqERR) @@ -9856,9 +9718,9 @@ module mkOCCP(pciDevice, MUX_wci_13_reqF_q_0_write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_13_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80471, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77921, cpReq[59:28] } ; assign MUX_wci_13_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80471, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77921, 32'hAAAAAAAA } ; always@(wci_13_reqPend or wci_13_reqTO) begin case (wci_13_reqPend) @@ -9874,13 +9736,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_13_wciResponse_wget ; assign MUX_wci_13_respF_enq_1__VAL_2 = { 2'd1, wci_13_wStatus } ; - assign MUX_wci_13_respF_enq_1__VAL_3 = { 2'd1, x_data__h106008 } ; - assign MUX_wci_13_respF_enq_1__VAL_4 = { 2'd1, x_data__h106014 } ; + assign MUX_wci_13_respF_enq_1__VAL_3 = { 2'd1, x_data__h103458 } ; + assign MUX_wci_13_respF_enq_1__VAL_4 = { 2'd1, x_data__h103464 } ; assign MUX_wci_13_respF_enq_1__VAL_5 = { 22'd1048576, wci_13_pageWindow } ; assign MUX_wci_13_respTimr_write_1__VAL_2 = (wci_13_wciResponse_wget[33:32] == 2'd0) ? - (wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 ? - x__h71103 : + (wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 ? + x__h68652 : 32'd0) : 32'd0 ; always@(wci_14_reqPend or wci_14_reqERR) @@ -9933,9 +9795,9 @@ module mkOCCP(pciDevice, MUX_wci_14_reqF_q_0_write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_14_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80539, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77989, cpReq[59:28] } ; assign MUX_wci_14_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80539, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77989, 32'hAAAAAAAA } ; always@(wci_14_reqPend or wci_14_reqTO) begin case (wci_14_reqPend) @@ -9951,13 +9813,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_14_wciResponse_wget ; assign MUX_wci_14_respF_enq_1__VAL_2 = { 2'd1, wci_14_wStatus } ; - assign MUX_wci_14_respF_enq_1__VAL_3 = { 2'd1, x_data__h106059 } ; - assign MUX_wci_14_respF_enq_1__VAL_4 = { 2'd1, x_data__h106065 } ; + assign MUX_wci_14_respF_enq_1__VAL_3 = { 2'd1, x_data__h103509 } ; + assign MUX_wci_14_respF_enq_1__VAL_4 = { 2'd1, x_data__h103515 } ; assign MUX_wci_14_respF_enq_1__VAL_5 = { 22'd1048576, wci_14_pageWindow } ; assign MUX_wci_14_respTimr_write_1__VAL_2 = (wci_14_wciResponse_wget[33:32] == 2'd0) ? - (wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 ? - x__h75472 : + (wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 ? + x__h73021 : 32'd0) : 32'd0 ; always@(wci_1_reqPend or wci_1_reqERR) @@ -9983,10 +9845,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_1_reqF_cntr_r_write_1__VAL_1 = wci_1_reqF_cntr_r + 1'd1 ; assign MUX_wci_1_reqF_cntr_r_write_1__VAL_2 = wci_1_reqF_cntr_r - 1'd1 ; - assign MUX_wci_1_reqF_q_0_write_1__VAL_1 = - wci_1_reqF_cntr_r ? - MUX_wci_1_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or @@ -9996,22 +9854,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_2 = + MUX_wci_1_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_2 = + MUX_wci_1_reqF_q_0_write_1__VAL_1 = MUX_wci_1_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_2 = + MUX_wci_1_reqF_q_0_write_1__VAL_1 = MUX_wci_1_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_1_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_1_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_1_reqF_q_0_write_1__VAL_2 = + wci_1_reqF_cntr_r ? + MUX_wci_1_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79655, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77105, cpReq[59:28] } ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79655, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77105, 32'hAAAAAAAA } ; always@(wci_1_reqPend or wci_1_reqTO) begin case (wci_1_reqPend) @@ -10027,13 +9889,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_1_wciResponse_wget ; assign MUX_wci_1_respF_enq_1__VAL_2 = { 2'd1, wci_1_wStatus } ; - assign MUX_wci_1_respF_enq_1__VAL_3 = { 2'd1, x_data__h105396 } ; - assign MUX_wci_1_respF_enq_1__VAL_4 = { 2'd1, x_data__h105402 } ; + assign MUX_wci_1_respF_enq_1__VAL_3 = { 2'd1, x_data__h102846 } ; + assign MUX_wci_1_respF_enq_1__VAL_4 = { 2'd1, x_data__h102852 } ; assign MUX_wci_1_respF_enq_1__VAL_5 = { 22'd1048576, wci_1_pageWindow } ; assign MUX_wci_1_respTimr_write_1__VAL_2 = (wci_1_wciResponse_wget[33:32] == 2'd0) ? - (wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 ? - x__h18675 : + (wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 ? + x__h16224 : 32'd0) : 32'd0 ; always@(wci_2_reqPend or wci_2_reqERR) @@ -10059,10 +9921,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_2_reqF_cntr_r_write_1__VAL_1 = wci_2_reqF_cntr_r + 1'd1 ; assign MUX_wci_2_reqF_cntr_r_write_1__VAL_2 = wci_2_reqF_cntr_r - 1'd1 ; - assign MUX_wci_2_reqF_q_0_write_1__VAL_1 = - wci_2_reqF_cntr_r ? - MUX_wci_2_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or @@ -10072,22 +9930,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_2 = + MUX_wci_2_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_2 = + MUX_wci_2_reqF_q_0_write_1__VAL_1 = MUX_wci_2_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_2 = + MUX_wci_2_reqF_q_0_write_1__VAL_1 = MUX_wci_2_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_2_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_2_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_2_reqF_q_0_write_1__VAL_2 = + wci_2_reqF_cntr_r ? + MUX_wci_2_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79723, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77173, cpReq[59:28] } ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79723, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77173, 32'hAAAAAAAA } ; always@(wci_2_reqPend or wci_2_reqTO) begin case (wci_2_reqPend) @@ -10103,13 +9965,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_2_wciResponse_wget ; assign MUX_wci_2_respF_enq_1__VAL_2 = { 2'd1, wci_2_wStatus } ; - assign MUX_wci_2_respF_enq_1__VAL_3 = { 2'd1, x_data__h105447 } ; - assign MUX_wci_2_respF_enq_1__VAL_4 = { 2'd1, x_data__h105453 } ; + assign MUX_wci_2_respF_enq_1__VAL_3 = { 2'd1, x_data__h102897 } ; + assign MUX_wci_2_respF_enq_1__VAL_4 = { 2'd1, x_data__h102903 } ; assign MUX_wci_2_respF_enq_1__VAL_5 = { 22'd1048576, wci_2_pageWindow } ; assign MUX_wci_2_respTimr_write_1__VAL_2 = (wci_2_wciResponse_wget[33:32] == 2'd0) ? - (wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 ? - x__h23044 : + (wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 ? + x__h20593 : 32'd0) : 32'd0 ; always@(wci_3_reqPend or wci_3_reqERR) @@ -10135,10 +9997,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_3_reqF_cntr_r_write_1__VAL_1 = wci_3_reqF_cntr_r + 1'd1 ; assign MUX_wci_3_reqF_cntr_r_write_1__VAL_2 = wci_3_reqF_cntr_r - 1'd1 ; - assign MUX_wci_3_reqF_q_0_write_1__VAL_1 = - wci_3_reqF_cntr_r ? - MUX_wci_3_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or @@ -10148,22 +10006,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_2 = + MUX_wci_3_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_2 = + MUX_wci_3_reqF_q_0_write_1__VAL_1 = MUX_wci_3_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_2 = + MUX_wci_3_reqF_q_0_write_1__VAL_1 = MUX_wci_3_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_3_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_3_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_3_reqF_q_0_write_1__VAL_2 = + wci_3_reqF_cntr_r ? + MUX_wci_3_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79791, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77241, cpReq[59:28] } ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79791, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77241, 32'hAAAAAAAA } ; always@(wci_3_reqPend or wci_3_reqTO) begin case (wci_3_reqPend) @@ -10179,13 +10041,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_3_wciResponse_wget ; assign MUX_wci_3_respF_enq_1__VAL_2 = { 2'd1, wci_3_wStatus } ; - assign MUX_wci_3_respF_enq_1__VAL_3 = { 2'd1, x_data__h105498 } ; - assign MUX_wci_3_respF_enq_1__VAL_4 = { 2'd1, x_data__h105504 } ; + assign MUX_wci_3_respF_enq_1__VAL_3 = { 2'd1, x_data__h102948 } ; + assign MUX_wci_3_respF_enq_1__VAL_4 = { 2'd1, x_data__h102954 } ; assign MUX_wci_3_respF_enq_1__VAL_5 = { 22'd1048576, wci_3_pageWindow } ; assign MUX_wci_3_respTimr_write_1__VAL_2 = (wci_3_wciResponse_wget[33:32] == 2'd0) ? - (wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 ? - x__h27413 : + (wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 ? + x__h24962 : 32'd0) : 32'd0 ; always@(wci_4_reqPend or wci_4_reqERR) @@ -10211,10 +10073,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_4_reqF_cntr_r_write_1__VAL_1 = wci_4_reqF_cntr_r + 1'd1 ; assign MUX_wci_4_reqF_cntr_r_write_1__VAL_2 = wci_4_reqF_cntr_r - 1'd1 ; - assign MUX_wci_4_reqF_q_0_write_1__VAL_1 = - wci_4_reqF_cntr_r ? - MUX_wci_4_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or @@ -10224,22 +10082,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_2 = + MUX_wci_4_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_2 = + MUX_wci_4_reqF_q_0_write_1__VAL_1 = MUX_wci_4_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_2 = + MUX_wci_4_reqF_q_0_write_1__VAL_1 = MUX_wci_4_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_4_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_4_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_4_reqF_q_0_write_1__VAL_2 = + wci_4_reqF_cntr_r ? + MUX_wci_4_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79859, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77309, cpReq[59:28] } ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79859, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77309, 32'hAAAAAAAA } ; always@(wci_4_reqPend or wci_4_reqTO) begin case (wci_4_reqPend) @@ -10255,13 +10117,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_4_wciResponse_wget ; assign MUX_wci_4_respF_enq_1__VAL_2 = { 2'd1, wci_4_wStatus } ; - assign MUX_wci_4_respF_enq_1__VAL_3 = { 2'd1, x_data__h105549 } ; - assign MUX_wci_4_respF_enq_1__VAL_4 = { 2'd1, x_data__h105555 } ; + assign MUX_wci_4_respF_enq_1__VAL_3 = { 2'd1, x_data__h102999 } ; + assign MUX_wci_4_respF_enq_1__VAL_4 = { 2'd1, x_data__h103005 } ; assign MUX_wci_4_respF_enq_1__VAL_5 = { 22'd1048576, wci_4_pageWindow } ; assign MUX_wci_4_respTimr_write_1__VAL_2 = (wci_4_wciResponse_wget[33:32] == 2'd0) ? - (wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 ? - x__h31782 : + (wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 ? + x__h29331 : 32'd0) : 32'd0 ; always@(wci_5_reqPend or wci_5_reqERR) @@ -10287,10 +10149,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_5_reqF_cntr_r_write_1__VAL_1 = wci_5_reqF_cntr_r + 1'd1 ; assign MUX_wci_5_reqF_cntr_r_write_1__VAL_2 = wci_5_reqF_cntr_r - 1'd1 ; - assign MUX_wci_5_reqF_q_0_write_1__VAL_1 = - wci_5_reqF_cntr_r ? - MUX_wci_5_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or @@ -10300,22 +10158,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_2 = + MUX_wci_5_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_2 = + MUX_wci_5_reqF_q_0_write_1__VAL_1 = MUX_wci_5_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_2 = + MUX_wci_5_reqF_q_0_write_1__VAL_1 = MUX_wci_5_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_5_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_5_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_5_reqF_q_0_write_1__VAL_2 = + wci_5_reqF_cntr_r ? + MUX_wci_5_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79927, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77377, cpReq[59:28] } ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79927, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77377, 32'hAAAAAAAA } ; always@(wci_5_reqPend or wci_5_reqTO) begin case (wci_5_reqPend) @@ -10331,13 +10193,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_5_wciResponse_wget ; assign MUX_wci_5_respF_enq_1__VAL_2 = { 2'd1, wci_5_wStatus } ; - assign MUX_wci_5_respF_enq_1__VAL_3 = { 2'd1, x_data__h105600 } ; - assign MUX_wci_5_respF_enq_1__VAL_4 = { 2'd1, x_data__h105606 } ; + assign MUX_wci_5_respF_enq_1__VAL_3 = { 2'd1, x_data__h103050 } ; + assign MUX_wci_5_respF_enq_1__VAL_4 = { 2'd1, x_data__h103056 } ; assign MUX_wci_5_respF_enq_1__VAL_5 = { 22'd1048576, wci_5_pageWindow } ; assign MUX_wci_5_respTimr_write_1__VAL_2 = (wci_5_wciResponse_wget[33:32] == 2'd0) ? - (wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 ? - x__h36151 : + (wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 ? + x__h33700 : 32'd0) : 32'd0 ; always@(wci_6_reqPend or wci_6_reqERR) @@ -10363,10 +10225,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_6_reqF_cntr_r_write_1__VAL_1 = wci_6_reqF_cntr_r + 1'd1 ; assign MUX_wci_6_reqF_cntr_r_write_1__VAL_2 = wci_6_reqF_cntr_r - 1'd1 ; - assign MUX_wci_6_reqF_q_0_write_1__VAL_1 = - wci_6_reqF_cntr_r ? - MUX_wci_6_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T or @@ -10376,22 +10234,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_2 = + MUX_wci_6_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_2 = + MUX_wci_6_reqF_q_0_write_1__VAL_1 = MUX_wci_6_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T: - MUX_wci_6_reqF_q_0_write_1__VAL_2 = + MUX_wci_6_reqF_q_0_write_1__VAL_1 = MUX_wci_6_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_6_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_6_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_6_reqF_q_0_write_1__VAL_2 = + wci_6_reqF_cntr_r ? + MUX_wci_6_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_6_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h79995, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77445, cpReq[59:28] } ; assign MUX_wci_6_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h79995, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77445, 32'hAAAAAAAA } ; always@(wci_6_reqPend or wci_6_reqTO) begin case (wci_6_reqPend) @@ -10407,13 +10269,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_6_wciResponse_wget ; assign MUX_wci_6_respF_enq_1__VAL_2 = { 2'd1, wci_6_wStatus } ; - assign MUX_wci_6_respF_enq_1__VAL_3 = { 2'd1, x_data__h105651 } ; - assign MUX_wci_6_respF_enq_1__VAL_4 = { 2'd1, x_data__h105657 } ; + assign MUX_wci_6_respF_enq_1__VAL_3 = { 2'd1, x_data__h103101 } ; + assign MUX_wci_6_respF_enq_1__VAL_4 = { 2'd1, x_data__h103107 } ; assign MUX_wci_6_respF_enq_1__VAL_5 = { 22'd1048576, wci_6_pageWindow } ; assign MUX_wci_6_respTimr_write_1__VAL_2 = (wci_6_wciResponse_wget[33:32] == 2'd0) ? - (wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 ? - x__h40520 : + (wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 ? + x__h38069 : 32'd0) : 32'd0 ; always@(wci_7_reqPend or wci_7_reqERR) @@ -10439,10 +10301,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_7_reqF_cntr_r_write_1__VAL_1 = wci_7_reqF_cntr_r + 1'd1 ; assign MUX_wci_7_reqF_cntr_r_write_1__VAL_2 = wci_7_reqF_cntr_r - 1'd1 ; - assign MUX_wci_7_reqF_q_0_write_1__VAL_1 = - wci_7_reqF_cntr_r ? - MUX_wci_7_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T or @@ -10452,22 +10310,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_2 = + MUX_wci_7_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_2 = + MUX_wci_7_reqF_q_0_write_1__VAL_1 = MUX_wci_7_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T: - MUX_wci_7_reqF_q_0_write_1__VAL_2 = + MUX_wci_7_reqF_q_0_write_1__VAL_1 = MUX_wci_7_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_7_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_7_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_7_reqF_q_0_write_1__VAL_2 = + wci_7_reqF_cntr_r ? + MUX_wci_7_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_7_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80063, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77513, cpReq[59:28] } ; assign MUX_wci_7_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80063, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77513, 32'hAAAAAAAA } ; always@(wci_7_reqPend or wci_7_reqTO) begin case (wci_7_reqPend) @@ -10483,13 +10345,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_7_wciResponse_wget ; assign MUX_wci_7_respF_enq_1__VAL_2 = { 2'd1, wci_7_wStatus } ; - assign MUX_wci_7_respF_enq_1__VAL_3 = { 2'd1, x_data__h105702 } ; - assign MUX_wci_7_respF_enq_1__VAL_4 = { 2'd1, x_data__h105708 } ; + assign MUX_wci_7_respF_enq_1__VAL_3 = { 2'd1, x_data__h103152 } ; + assign MUX_wci_7_respF_enq_1__VAL_4 = { 2'd1, x_data__h103158 } ; assign MUX_wci_7_respF_enq_1__VAL_5 = { 22'd1048576, wci_7_pageWindow } ; assign MUX_wci_7_respTimr_write_1__VAL_2 = (wci_7_wciResponse_wget[33:32] == 2'd0) ? - (wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 ? - x__h44889 : + (wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 ? + x__h42438 : 32'd0) : 32'd0 ; always@(wci_8_reqPend or wci_8_reqERR) @@ -10515,10 +10377,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_8_reqF_cntr_r_write_1__VAL_1 = wci_8_reqF_cntr_r + 1'd1 ; assign MUX_wci_8_reqF_cntr_r_write_1__VAL_2 = wci_8_reqF_cntr_r - 1'd1 ; - assign MUX_wci_8_reqF_q_0_write_1__VAL_1 = - wci_8_reqF_cntr_r ? - MUX_wci_8_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T or @@ -10528,22 +10386,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_2 = + MUX_wci_8_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_2 = + MUX_wci_8_reqF_q_0_write_1__VAL_1 = MUX_wci_8_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T: - MUX_wci_8_reqF_q_0_write_1__VAL_2 = + MUX_wci_8_reqF_q_0_write_1__VAL_1 = MUX_wci_8_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_8_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_8_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_8_reqF_q_0_write_1__VAL_2 = + wci_8_reqF_cntr_r ? + MUX_wci_8_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_8_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80131, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77581, cpReq[59:28] } ; assign MUX_wci_8_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80131, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77581, 32'hAAAAAAAA } ; always@(wci_8_reqPend or wci_8_reqTO) begin case (wci_8_reqPend) @@ -10559,13 +10421,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_8_wciResponse_wget ; assign MUX_wci_8_respF_enq_1__VAL_2 = { 2'd1, wci_8_wStatus } ; - assign MUX_wci_8_respF_enq_1__VAL_3 = { 2'd1, x_data__h105753 } ; - assign MUX_wci_8_respF_enq_1__VAL_4 = { 2'd1, x_data__h105759 } ; + assign MUX_wci_8_respF_enq_1__VAL_3 = { 2'd1, x_data__h103203 } ; + assign MUX_wci_8_respF_enq_1__VAL_4 = { 2'd1, x_data__h103209 } ; assign MUX_wci_8_respF_enq_1__VAL_5 = { 22'd1048576, wci_8_pageWindow } ; assign MUX_wci_8_respTimr_write_1__VAL_2 = (wci_8_wciResponse_wget[33:32] == 2'd0) ? - (wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 ? - x__h49258 : + (wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 ? + x__h46807 : 32'd0) : 32'd0 ; always@(wci_9_reqPend or wci_9_reqERR) @@ -10591,10 +10453,6 @@ module mkOCCP(pciDevice, end assign MUX_wci_9_reqF_cntr_r_write_1__VAL_1 = wci_9_reqF_cntr_r + 1'd1 ; assign MUX_wci_9_reqF_cntr_r_write_1__VAL_2 = wci_9_reqF_cntr_r - 1'd1 ; - assign MUX_wci_9_reqF_q_0_write_1__VAL_1 = - wci_9_reqF_cntr_r ? - MUX_wci_9_reqF_q_0_write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T or @@ -10604,22 +10462,26 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_2 = + MUX_wci_9_reqF_q_0_write_1__VAL_1 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_2 = + MUX_wci_9_reqF_q_0_write_1__VAL_1 = MUX_wci_9_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T: - MUX_wci_9_reqF_q_0_write_1__VAL_2 = + MUX_wci_9_reqF_q_0_write_1__VAL_1 = MUX_wci_9_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_9_reqF_q_0_write_1__VAL_2 = + default: MUX_wci_9_reqF_q_0_write_1__VAL_1 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign MUX_wci_9_reqF_q_0_write_1__VAL_2 = + wci_9_reqF_cntr_r ? + MUX_wci_9_reqF_q_0_write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; assign MUX_wci_9_reqF_x_wire_wset_1__VAL_2 = - { 4'd3, cpReq[3:0], wciAddr__h80199, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h77649, cpReq[59:28] } ; assign MUX_wci_9_reqF_x_wire_wset_1__VAL_3 = - { 4'd5, cpReq[3:0], wciAddr__h80199, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h77649, 32'hAAAAAAAA } ; always@(wci_9_reqPend or wci_9_reqTO) begin case (wci_9_reqPend) @@ -10635,13 +10497,13 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_9_wciResponse_wget ; assign MUX_wci_9_respF_enq_1__VAL_2 = { 2'd1, wci_9_wStatus } ; - assign MUX_wci_9_respF_enq_1__VAL_3 = { 2'd1, x_data__h105804 } ; - assign MUX_wci_9_respF_enq_1__VAL_4 = { 2'd1, x_data__h105810 } ; + assign MUX_wci_9_respF_enq_1__VAL_3 = { 2'd1, x_data__h103254 } ; + assign MUX_wci_9_respF_enq_1__VAL_4 = { 2'd1, x_data__h103260 } ; assign MUX_wci_9_respF_enq_1__VAL_5 = { 22'd1048576, wci_9_pageWindow } ; assign MUX_wci_9_respTimr_write_1__VAL_2 = (wci_9_wciResponse_wget[33:32] == 2'd0) ? - (wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 ? - x__h53627 : + (wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 ? + x__h51176 : 32'd0) : 32'd0 ; @@ -10651,12 +10513,12 @@ module mkOCCP(pciDevice, assign timeServ_jamFrac_1_wget = 1'd1 ; assign timeServ_jamFrac_1_whas = timeServ_setRefF_dEMPTY_N && !timeServ_ppsOK ; - assign timeServ_jamFracVal_1_wget = x__h3692 ; + assign timeServ_jamFracVal_1_wget = x__h3688 ; assign timeServ_jamFracVal_1_whas = timeServ_jamFrac_1_whas ; - assign deviceDNA_wget = x_wget__h5217 ; + assign deviceDNA_wget = x_wget__h5213 ; assign deviceDNA_whas = dna_cnt == 7'd127 ; assign devDNAV_wget = - (dna_cnt == 7'd127) ? x_wget__h5217 : 64'h0BADC0DE0BADC0DE ; + (dna_cnt == 7'd127) ? x_wget__h5213 : 64'h0BADC0DE0BADC0DE ; assign devDNAV_whas = 1'd1 ; assign rom_serverAdapter_outData_enqData_wget = rom_memory_DO ; assign rom_serverAdapter_outData_enqData_whas = @@ -10692,7 +10554,7 @@ module mkOCCP(pciDevice, assign dna_shftReg_1_whas = dna_cnt >= 7'd3 && dna_cnt <= 7'd116 ; assign uuidV_wget = uuid_arg ; assign uuidV_whas = 1'd1 ; - assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_2 ; + assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_1 ; assign wci_0_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || @@ -10705,7 +10567,7 @@ module mkOCCP(pciDevice, assign wci_0_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; - assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_2 ; + assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_1 ; assign wci_1_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || @@ -10718,7 +10580,7 @@ module mkOCCP(pciDevice, assign wci_1_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; - assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_2 ; + assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_1 ; assign wci_2_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || @@ -10731,7 +10593,7 @@ module mkOCCP(pciDevice, assign wci_2_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; - assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_2 ; + assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_1 ; assign wci_3_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || @@ -10744,7 +10606,7 @@ module mkOCCP(pciDevice, assign wci_3_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; - assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_2 ; + assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_1 ; assign wci_4_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || @@ -10757,7 +10619,7 @@ module mkOCCP(pciDevice, assign wci_4_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; - assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_2 ; + assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_1 ; assign wci_5_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || @@ -10770,7 +10632,7 @@ module mkOCCP(pciDevice, assign wci_5_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; - assign wci_6_reqF_x_wire_wget = MUX_wci_6_reqF_q_0_write_1__VAL_2 ; + assign wci_6_reqF_x_wire_wget = MUX_wci_6_reqF_q_0_write_1__VAL_1 ; assign wci_6_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || @@ -10783,7 +10645,7 @@ module mkOCCP(pciDevice, assign wci_6_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; - assign wci_7_reqF_x_wire_wget = MUX_wci_7_reqF_q_0_write_1__VAL_2 ; + assign wci_7_reqF_x_wire_wget = MUX_wci_7_reqF_q_0_write_1__VAL_1 ; assign wci_7_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || @@ -10796,7 +10658,7 @@ module mkOCCP(pciDevice, assign wci_7_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; - assign wci_8_reqF_x_wire_wget = MUX_wci_8_reqF_q_0_write_1__VAL_2 ; + assign wci_8_reqF_x_wire_wget = MUX_wci_8_reqF_q_0_write_1__VAL_1 ; assign wci_8_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || @@ -10809,7 +10671,7 @@ module mkOCCP(pciDevice, assign wci_8_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; - assign wci_9_reqF_x_wire_wget = MUX_wci_9_reqF_q_0_write_1__VAL_2 ; + assign wci_9_reqF_x_wire_wget = MUX_wci_9_reqF_q_0_write_1__VAL_1 ; assign wci_9_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || @@ -11045,9 +10907,7 @@ module mkOCCP(pciDevice, MUX_cpReq_write_1__VAL_4 or WILL_FIRE_RL_completeWorkerRead or WILL_FIRE_RL_completeWorkerWrite or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T or @@ -11062,9 +10922,7 @@ module mkOCCP(pciDevice, cpReq_D_IN = 65'h02AAAAAAAAAAAAAAA; WILL_FIRE_RL_reqRcv: cpReq_D_IN = MUX_cpReq_write_1__VAL_4; WILL_FIRE_RL_completeWorkerRead || WILL_FIRE_RL_completeWorkerWrite || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T || @@ -11079,9 +10937,7 @@ module mkOCCP(pciDevice, endcase assign cpReq_EN = WILL_FIRE_RL_reqRcv || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T || @@ -11381,15 +11237,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways or WILL_FIRE_RL_cpDispatch_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_T_T_F_F or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T or + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F or WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T or WILL_FIRE_RL_cpDispatch_F_T_T_T or - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T or @@ -11679,15 +11531,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways || WILL_FIRE_RL_cpDispatch_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_F || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T || + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_T_T_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T || @@ -11977,15 +11825,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways || WILL_FIRE_RL_cpDispatch_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_F || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T || + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_T_T_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_T || @@ -12054,9 +11898,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways || WILL_FIRE_RL_cpDispatch_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_F || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T || + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_T_T_T ; @@ -12084,13 +11926,13 @@ module mkOCCP(pciDevice, timeServ_refFromRise_3_ULT_200200000___d50 ; // register timeServ_fracInc - assign timeServ_fracInc_D_IN = timeServ_fracInc + x__h4412 ; + assign timeServ_fracInc_D_IN = timeServ_fracInc + x__h4408 ; assign timeServ_fracInc_EN = timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 ; // register timeServ_fracSeconds assign timeServ_fracSeconds_D_IN = - timeServ_jamFrac ? timeServ_jamFracVal : x__h4640 ; + timeServ_jamFrac ? timeServ_jamFracVal : x__h4636 ; assign timeServ_fracSeconds_EN = 1'd1 ; // register timeServ_gpsInSticky @@ -12103,7 +11945,7 @@ module mkOCCP(pciDevice, // register timeServ_jamFracVal assign timeServ_jamFracVal_D_IN = - timeServ_jamFrac_1_whas ? x__h3692 : 50'd0 ; + timeServ_jamFrac_1_whas ? x__h3688 : 50'd0 ; assign timeServ_jamFracVal_EN = 1'd1 ; // register timeServ_lastSecond @@ -12206,7 +12048,7 @@ module mkOCCP(pciDevice, assign timeServ_refSecCount_D_IN = timeServ_setRefF_dEMPTY_N ? timeServ_setRefF_dD_OUT[63:32] : - x__h4706 ; + x__h4702 ; assign timeServ_refSecCount_EN = timeServ_setRefF_dEMPTY_N || IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39 ; @@ -12228,14 +12070,6 @@ module mkOCCP(pciDevice, assign timeServ_xo2_D_IN = !timeServ_xo2 ; assign timeServ_xo2_EN = 1'd1 ; - // register uartInited - assign uartInited_D_IN = 1'd1 ; - assign uartInited_EN = WILL_FIRE_RL_init_uart_text && uartTxtP == 6'd43 ; - - // register uartTxtP - assign uartTxtP_D_IN = uartTxtP + 6'd1 ; - assign uartTxtP_EN = WILL_FIRE_RL_init_uart_text ; - // register warmResetP assign warmResetP_D_IN = WILL_FIRE_RL_cpDispatch_T_F_F_F_T && @@ -12246,7 +12080,7 @@ module mkOCCP(pciDevice, assign wci_0_busy_D_IN = !MUX_wci_0_busy_write_1__SEL_1 ; assign wci_0_busy_EN = WILL_FIRE_RL_wci_0_wrkBusy && - (!wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 || + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || wci_0_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || @@ -12319,15 +12153,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqF_q_0 - always@(WILL_FIRE_RL_wci_0_reqF_both or + always@(MUX_wci_0_reqF_q_0_write_1__SEL_1 or MUX_wci_0_reqF_q_0_write_1__VAL_1 or - MUX_wci_0_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_0_reqF_both or MUX_wci_0_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_0_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_0_reqF_both: + MUX_wci_0_reqF_q_0_write_1__SEL_1: wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_1; - MUX_wci_0_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_0_reqF_both: wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_0_reqF_decCtr: wci_0_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -12336,8 +12170,8 @@ module mkOCCP(pciDevice, endcase end assign wci_0_reqF_q_0_EN = - WILL_FIRE_RL_wci_0_reqF_both || WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || + WILL_FIRE_RL_wci_0_reqF_both || WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqPend @@ -12368,7 +12202,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_0_reqTO_EN = WILL_FIRE_RL_wci_0_wrkBusy && - wci_0_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d269 || + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; @@ -12381,7 +12215,7 @@ module mkOCCP(pciDevice, assign wci_0_respTimrAct_D_IN = wci_0_reqF_cntr_r ; assign wci_0_respTimrAct_EN = WILL_FIRE_RL_wci_0_wrkBusy && - (!wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 || + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || wci_0_wciResponse_wget[33:32] != 2'd0) || wci_0_reqF_cntr_r ; @@ -12417,7 +12251,7 @@ module mkOCCP(pciDevice, assign wci_0_wStatus_D_IN = { 4'b0, !wci_0_lastOpWrite[1] || wci_0_lastOpWrite[0], - IF_wci_0_lastControlOp_30_BIT_3_31_THEN_wci_0__ETC___d345 } ; + IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328 } ; assign wci_0_wStatus_EN = 1'd1 ; // register wci_0_wTimeout @@ -12432,7 +12266,7 @@ module mkOCCP(pciDevice, assign wci_10_busy_D_IN = !MUX_wci_10_busy_write_1__SEL_1 ; assign wci_10_busy_EN = WILL_FIRE_RL_wci_10_wrkBusy && - (!wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 || + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || wci_10_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || @@ -12555,7 +12389,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_10_reqTO_EN = WILL_FIRE_RL_wci_10_wrkBusy && - wci_10_wciResponse_wget__640_BITS_33_TO_32_641_ETC___d1669 || + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 || WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; @@ -12569,7 +12403,7 @@ module mkOCCP(pciDevice, assign wci_10_respTimrAct_D_IN = wci_10_reqF_cntr_r ; assign wci_10_respTimrAct_EN = WILL_FIRE_RL_wci_10_wrkBusy && - (!wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 || + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || wci_10_wciResponse_wget[33:32] != 2'd0) || wci_10_reqF_cntr_r ; @@ -12605,7 +12439,7 @@ module mkOCCP(pciDevice, assign wci_10_wStatus_D_IN = { 4'b0, !wci_10_lastOpWrite[1] || wci_10_lastOpWrite[0], - IF_wci_10_lastControlOp_730_BIT_3_731_THEN_wci_ETC___d1745 } ; + IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728 } ; assign wci_10_wStatus_EN = 1'd1 ; // register wci_10_wTimeout @@ -12620,7 +12454,7 @@ module mkOCCP(pciDevice, assign wci_11_busy_D_IN = !MUX_wci_11_busy_write_1__SEL_1 ; assign wci_11_busy_EN = WILL_FIRE_RL_wci_11_wrkBusy && - (!wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 || + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || wci_11_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || @@ -12743,7 +12577,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_11_reqTO_EN = WILL_FIRE_RL_wci_11_wrkBusy && - wci_11_wciResponse_wget__780_BITS_33_TO_32_781_ETC___d1809 || + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 || WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; @@ -12757,7 +12591,7 @@ module mkOCCP(pciDevice, assign wci_11_respTimrAct_D_IN = wci_11_reqF_cntr_r ; assign wci_11_respTimrAct_EN = WILL_FIRE_RL_wci_11_wrkBusy && - (!wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 || + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || wci_11_wciResponse_wget[33:32] != 2'd0) || wci_11_reqF_cntr_r ; @@ -12793,7 +12627,7 @@ module mkOCCP(pciDevice, assign wci_11_wStatus_D_IN = { 4'b0, !wci_11_lastOpWrite[1] || wci_11_lastOpWrite[0], - IF_wci_11_lastControlOp_870_BIT_3_871_THEN_wci_ETC___d1885 } ; + IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868 } ; assign wci_11_wStatus_EN = 1'd1 ; // register wci_11_wTimeout @@ -12808,7 +12642,7 @@ module mkOCCP(pciDevice, assign wci_12_busy_D_IN = !MUX_wci_12_busy_write_1__SEL_1 ; assign wci_12_busy_EN = WILL_FIRE_RL_wci_12_wrkBusy && - (!wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 || + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || wci_12_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || @@ -12931,7 +12765,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_12_reqTO_EN = WILL_FIRE_RL_wci_12_wrkBusy && - wci_12_wciResponse_wget__920_BITS_33_TO_32_921_ETC___d1949 || + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 || WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; @@ -12945,7 +12779,7 @@ module mkOCCP(pciDevice, assign wci_12_respTimrAct_D_IN = wci_12_reqF_cntr_r ; assign wci_12_respTimrAct_EN = WILL_FIRE_RL_wci_12_wrkBusy && - (!wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 || + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || wci_12_wciResponse_wget[33:32] != 2'd0) || wci_12_reqF_cntr_r ; @@ -12981,7 +12815,7 @@ module mkOCCP(pciDevice, assign wci_12_wStatus_D_IN = { 4'b0, !wci_12_lastOpWrite[1] || wci_12_lastOpWrite[0], - IF_wci_12_lastControlOp_010_BIT_3_011_THEN_wci_ETC___d2025 } ; + IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008 } ; assign wci_12_wStatus_EN = 1'd1 ; // register wci_12_wTimeout @@ -12996,7 +12830,7 @@ module mkOCCP(pciDevice, assign wci_13_busy_D_IN = !MUX_wci_13_busy_write_1__SEL_1 ; assign wci_13_busy_EN = WILL_FIRE_RL_wci_13_wrkBusy && - (!wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 || + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || wci_13_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || @@ -13119,7 +12953,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_13_reqTO_EN = WILL_FIRE_RL_wci_13_wrkBusy && - wci_13_wciResponse_wget__060_BITS_33_TO_32_061_ETC___d2089 || + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 || WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; @@ -13133,7 +12967,7 @@ module mkOCCP(pciDevice, assign wci_13_respTimrAct_D_IN = wci_13_reqF_cntr_r ; assign wci_13_respTimrAct_EN = WILL_FIRE_RL_wci_13_wrkBusy && - (!wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 || + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || wci_13_wciResponse_wget[33:32] != 2'd0) || wci_13_reqF_cntr_r ; @@ -13169,7 +13003,7 @@ module mkOCCP(pciDevice, assign wci_13_wStatus_D_IN = { 4'b0, !wci_13_lastOpWrite[1] || wci_13_lastOpWrite[0], - IF_wci_13_lastControlOp_150_BIT_3_151_THEN_wci_ETC___d2165 } ; + IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148 } ; assign wci_13_wStatus_EN = 1'd1 ; // register wci_13_wTimeout @@ -13184,7 +13018,7 @@ module mkOCCP(pciDevice, assign wci_14_busy_D_IN = !MUX_wci_14_busy_write_1__SEL_1 ; assign wci_14_busy_EN = WILL_FIRE_RL_wci_14_wrkBusy && - (!wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 || + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || wci_14_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || @@ -13307,7 +13141,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_14_reqTO_EN = WILL_FIRE_RL_wci_14_wrkBusy && - wci_14_wciResponse_wget__200_BITS_33_TO_32_201_ETC___d2229 || + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 || WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; @@ -13321,7 +13155,7 @@ module mkOCCP(pciDevice, assign wci_14_respTimrAct_D_IN = wci_14_reqF_cntr_r ; assign wci_14_respTimrAct_EN = WILL_FIRE_RL_wci_14_wrkBusy && - (!wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 || + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || wci_14_wciResponse_wget[33:32] != 2'd0) || wci_14_reqF_cntr_r ; @@ -13357,7 +13191,7 @@ module mkOCCP(pciDevice, assign wci_14_wStatus_D_IN = { 4'b0, !wci_14_lastOpWrite[1] || wci_14_lastOpWrite[0], - IF_wci_14_lastControlOp_290_BIT_3_291_THEN_wci_ETC___d2305 } ; + IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288 } ; assign wci_14_wStatus_EN = 1'd1 ; // register wci_14_wTimeout @@ -13372,7 +13206,7 @@ module mkOCCP(pciDevice, assign wci_1_busy_D_IN = !MUX_wci_1_busy_write_1__SEL_1 ; assign wci_1_busy_EN = WILL_FIRE_RL_wci_1_wrkBusy && - (!wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 || + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || wci_1_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || @@ -13445,15 +13279,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqF_q_0 - always@(WILL_FIRE_RL_wci_1_reqF_both or + always@(MUX_wci_1_reqF_q_0_write_1__SEL_1 or MUX_wci_1_reqF_q_0_write_1__VAL_1 or - MUX_wci_1_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_1_reqF_both or MUX_wci_1_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_1_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_1_reqF_both: + MUX_wci_1_reqF_q_0_write_1__SEL_1: wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_1; - MUX_wci_1_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_1_reqF_both: wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_1_reqF_decCtr: wci_1_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13462,8 +13296,8 @@ module mkOCCP(pciDevice, endcase end assign wci_1_reqF_q_0_EN = - WILL_FIRE_RL_wci_1_reqF_both || WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || + WILL_FIRE_RL_wci_1_reqF_both || WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqPend @@ -13494,7 +13328,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_1_reqTO_EN = WILL_FIRE_RL_wci_1_wrkBusy && - wci_1_wciResponse_wget__80_BITS_33_TO_32_81_EQ_ETC___d409 || + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; @@ -13507,7 +13341,7 @@ module mkOCCP(pciDevice, assign wci_1_respTimrAct_D_IN = wci_1_reqF_cntr_r ; assign wci_1_respTimrAct_EN = WILL_FIRE_RL_wci_1_wrkBusy && - (!wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 || + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || wci_1_wciResponse_wget[33:32] != 2'd0) || wci_1_reqF_cntr_r ; @@ -13543,7 +13377,7 @@ module mkOCCP(pciDevice, assign wci_1_wStatus_D_IN = { 4'b0, !wci_1_lastOpWrite[1] || wci_1_lastOpWrite[0], - IF_wci_1_lastControlOp_70_BIT_3_71_THEN_wci_1__ETC___d485 } ; + IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468 } ; assign wci_1_wStatus_EN = 1'd1 ; // register wci_1_wTimeout @@ -13558,7 +13392,7 @@ module mkOCCP(pciDevice, assign wci_2_busy_D_IN = !MUX_wci_2_busy_write_1__SEL_1 ; assign wci_2_busy_EN = WILL_FIRE_RL_wci_2_wrkBusy && - (!wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 || + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || wci_2_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || @@ -13631,15 +13465,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqF_q_0 - always@(WILL_FIRE_RL_wci_2_reqF_both or + always@(MUX_wci_2_reqF_q_0_write_1__SEL_1 or MUX_wci_2_reqF_q_0_write_1__VAL_1 or - MUX_wci_2_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_2_reqF_both or MUX_wci_2_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_2_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_2_reqF_both: + MUX_wci_2_reqF_q_0_write_1__SEL_1: wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_1; - MUX_wci_2_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_2_reqF_both: wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_2_reqF_decCtr: wci_2_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13648,8 +13482,8 @@ module mkOCCP(pciDevice, endcase end assign wci_2_reqF_q_0_EN = - WILL_FIRE_RL_wci_2_reqF_both || WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || + WILL_FIRE_RL_wci_2_reqF_both || WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqPend @@ -13680,7 +13514,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_2_reqTO_EN = WILL_FIRE_RL_wci_2_wrkBusy && - wci_2_wciResponse_wget__20_BITS_33_TO_32_21_EQ_ETC___d549 || + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; @@ -13693,7 +13527,7 @@ module mkOCCP(pciDevice, assign wci_2_respTimrAct_D_IN = wci_2_reqF_cntr_r ; assign wci_2_respTimrAct_EN = WILL_FIRE_RL_wci_2_wrkBusy && - (!wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 || + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || wci_2_wciResponse_wget[33:32] != 2'd0) || wci_2_reqF_cntr_r ; @@ -13729,7 +13563,7 @@ module mkOCCP(pciDevice, assign wci_2_wStatus_D_IN = { 4'b0, !wci_2_lastOpWrite[1] || wci_2_lastOpWrite[0], - IF_wci_2_lastControlOp_10_BIT_3_11_THEN_wci_2__ETC___d625 } ; + IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608 } ; assign wci_2_wStatus_EN = 1'd1 ; // register wci_2_wTimeout @@ -13744,7 +13578,7 @@ module mkOCCP(pciDevice, assign wci_3_busy_D_IN = !MUX_wci_3_busy_write_1__SEL_1 ; assign wci_3_busy_EN = WILL_FIRE_RL_wci_3_wrkBusy && - (!wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 || + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || wci_3_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || @@ -13817,15 +13651,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqF_q_0 - always@(WILL_FIRE_RL_wci_3_reqF_both or + always@(MUX_wci_3_reqF_q_0_write_1__SEL_1 or MUX_wci_3_reqF_q_0_write_1__VAL_1 or - MUX_wci_3_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_3_reqF_both or MUX_wci_3_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_3_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_3_reqF_both: + MUX_wci_3_reqF_q_0_write_1__SEL_1: wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_1; - MUX_wci_3_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_3_reqF_both: wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_3_reqF_decCtr: wci_3_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13834,8 +13668,8 @@ module mkOCCP(pciDevice, endcase end assign wci_3_reqF_q_0_EN = - WILL_FIRE_RL_wci_3_reqF_both || WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || + WILL_FIRE_RL_wci_3_reqF_both || WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqPend @@ -13866,7 +13700,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_3_reqTO_EN = WILL_FIRE_RL_wci_3_wrkBusy && - wci_3_wciResponse_wget__60_BITS_33_TO_32_61_EQ_ETC___d689 || + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; @@ -13879,7 +13713,7 @@ module mkOCCP(pciDevice, assign wci_3_respTimrAct_D_IN = wci_3_reqF_cntr_r ; assign wci_3_respTimrAct_EN = WILL_FIRE_RL_wci_3_wrkBusy && - (!wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 || + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || wci_3_wciResponse_wget[33:32] != 2'd0) || wci_3_reqF_cntr_r ; @@ -13915,7 +13749,7 @@ module mkOCCP(pciDevice, assign wci_3_wStatus_D_IN = { 4'b0, !wci_3_lastOpWrite[1] || wci_3_lastOpWrite[0], - IF_wci_3_lastControlOp_50_BIT_3_51_THEN_wci_3__ETC___d765 } ; + IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748 } ; assign wci_3_wStatus_EN = 1'd1 ; // register wci_3_wTimeout @@ -13930,7 +13764,7 @@ module mkOCCP(pciDevice, assign wci_4_busy_D_IN = !MUX_wci_4_busy_write_1__SEL_1 ; assign wci_4_busy_EN = WILL_FIRE_RL_wci_4_wrkBusy && - (!wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 || + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || wci_4_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || @@ -14003,15 +13837,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqF_q_0 - always@(WILL_FIRE_RL_wci_4_reqF_both or + always@(MUX_wci_4_reqF_q_0_write_1__SEL_1 or MUX_wci_4_reqF_q_0_write_1__VAL_1 or - MUX_wci_4_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_4_reqF_both or MUX_wci_4_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_4_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_4_reqF_both: + MUX_wci_4_reqF_q_0_write_1__SEL_1: wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_1; - MUX_wci_4_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_4_reqF_both: wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_4_reqF_decCtr: wci_4_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14020,8 +13854,8 @@ module mkOCCP(pciDevice, endcase end assign wci_4_reqF_q_0_EN = - WILL_FIRE_RL_wci_4_reqF_both || WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || + WILL_FIRE_RL_wci_4_reqF_both || WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqPend @@ -14052,7 +13886,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_4_reqTO_EN = WILL_FIRE_RL_wci_4_wrkBusy && - wci_4_wciResponse_wget__00_BITS_33_TO_32_01_EQ_ETC___d829 || + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; @@ -14065,7 +13899,7 @@ module mkOCCP(pciDevice, assign wci_4_respTimrAct_D_IN = wci_4_reqF_cntr_r ; assign wci_4_respTimrAct_EN = WILL_FIRE_RL_wci_4_wrkBusy && - (!wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 || + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || wci_4_wciResponse_wget[33:32] != 2'd0) || wci_4_reqF_cntr_r ; @@ -14101,7 +13935,7 @@ module mkOCCP(pciDevice, assign wci_4_wStatus_D_IN = { 4'b0, !wci_4_lastOpWrite[1] || wci_4_lastOpWrite[0], - IF_wci_4_lastControlOp_90_BIT_3_91_THEN_wci_4__ETC___d905 } ; + IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888 } ; assign wci_4_wStatus_EN = 1'd1 ; // register wci_4_wTimeout @@ -14116,7 +13950,7 @@ module mkOCCP(pciDevice, assign wci_5_busy_D_IN = !MUX_wci_5_busy_write_1__SEL_1 ; assign wci_5_busy_EN = WILL_FIRE_RL_wci_5_wrkBusy && - (!wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 || + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || wci_5_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || @@ -14189,15 +14023,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqF_q_0 - always@(WILL_FIRE_RL_wci_5_reqF_both or + always@(MUX_wci_5_reqF_q_0_write_1__SEL_1 or MUX_wci_5_reqF_q_0_write_1__VAL_1 or - MUX_wci_5_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_5_reqF_both or MUX_wci_5_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_5_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_5_reqF_both: + MUX_wci_5_reqF_q_0_write_1__SEL_1: wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_1; - MUX_wci_5_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_5_reqF_both: wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_5_reqF_decCtr: wci_5_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14206,8 +14040,8 @@ module mkOCCP(pciDevice, endcase end assign wci_5_reqF_q_0_EN = - WILL_FIRE_RL_wci_5_reqF_both || WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || + WILL_FIRE_RL_wci_5_reqF_both || WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqPend @@ -14238,7 +14072,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_5_reqTO_EN = WILL_FIRE_RL_wci_5_wrkBusy && - wci_5_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d969 || + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 || WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; @@ -14251,7 +14085,7 @@ module mkOCCP(pciDevice, assign wci_5_respTimrAct_D_IN = wci_5_reqF_cntr_r ; assign wci_5_respTimrAct_EN = WILL_FIRE_RL_wci_5_wrkBusy && - (!wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 || + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || wci_5_wciResponse_wget[33:32] != 2'd0) || wci_5_reqF_cntr_r ; @@ -14287,7 +14121,7 @@ module mkOCCP(pciDevice, assign wci_5_wStatus_D_IN = { 4'b0, !wci_5_lastOpWrite[1] || wci_5_lastOpWrite[0], - IF_wci_5_lastControlOp_030_BIT_3_031_THEN_wci__ETC___d1045 } ; + IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028 } ; assign wci_5_wStatus_EN = 1'd1 ; // register wci_5_wTimeout @@ -14302,7 +14136,7 @@ module mkOCCP(pciDevice, assign wci_6_busy_D_IN = !MUX_wci_6_busy_write_1__SEL_1 ; assign wci_6_busy_EN = WILL_FIRE_RL_wci_6_wrkBusy && - (!wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 || + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || wci_6_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || @@ -14375,15 +14209,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_6_reqF_decCtr ; // register wci_6_reqF_q_0 - always@(WILL_FIRE_RL_wci_6_reqF_both or + always@(MUX_wci_6_reqF_q_0_write_1__SEL_1 or MUX_wci_6_reqF_q_0_write_1__VAL_1 or - MUX_wci_6_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_6_reqF_both or MUX_wci_6_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_6_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_6_reqF_both: + MUX_wci_6_reqF_q_0_write_1__SEL_1: wci_6_reqF_q_0_D_IN = MUX_wci_6_reqF_q_0_write_1__VAL_1; - MUX_wci_6_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_6_reqF_both: wci_6_reqF_q_0_D_IN = MUX_wci_6_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_6_reqF_decCtr: wci_6_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14392,8 +14226,8 @@ module mkOCCP(pciDevice, endcase end assign wci_6_reqF_q_0_EN = - WILL_FIRE_RL_wci_6_reqF_both || WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r || + WILL_FIRE_RL_wci_6_reqF_both || WILL_FIRE_RL_wci_6_reqF_decCtr ; // register wci_6_reqPend @@ -14424,7 +14258,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_6_reqTO_EN = WILL_FIRE_RL_wci_6_wrkBusy && - wci_6_wciResponse_wget__080_BITS_33_TO_32_081__ETC___d1109 || + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 || WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; @@ -14437,7 +14271,7 @@ module mkOCCP(pciDevice, assign wci_6_respTimrAct_D_IN = wci_6_reqF_cntr_r ; assign wci_6_respTimrAct_EN = WILL_FIRE_RL_wci_6_wrkBusy && - (!wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 || + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || wci_6_wciResponse_wget[33:32] != 2'd0) || wci_6_reqF_cntr_r ; @@ -14473,7 +14307,7 @@ module mkOCCP(pciDevice, assign wci_6_wStatus_D_IN = { 4'b0, !wci_6_lastOpWrite[1] || wci_6_lastOpWrite[0], - IF_wci_6_lastControlOp_170_BIT_3_171_THEN_wci__ETC___d1185 } ; + IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168 } ; assign wci_6_wStatus_EN = 1'd1 ; // register wci_6_wTimeout @@ -14488,7 +14322,7 @@ module mkOCCP(pciDevice, assign wci_7_busy_D_IN = !MUX_wci_7_busy_write_1__SEL_1 ; assign wci_7_busy_EN = WILL_FIRE_RL_wci_7_wrkBusy && - (!wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 || + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || wci_7_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || @@ -14561,15 +14395,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_7_reqF_decCtr ; // register wci_7_reqF_q_0 - always@(WILL_FIRE_RL_wci_7_reqF_both or + always@(MUX_wci_7_reqF_q_0_write_1__SEL_1 or MUX_wci_7_reqF_q_0_write_1__VAL_1 or - MUX_wci_7_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_7_reqF_both or MUX_wci_7_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_7_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_7_reqF_both: + MUX_wci_7_reqF_q_0_write_1__SEL_1: wci_7_reqF_q_0_D_IN = MUX_wci_7_reqF_q_0_write_1__VAL_1; - MUX_wci_7_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_7_reqF_both: wci_7_reqF_q_0_D_IN = MUX_wci_7_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_7_reqF_decCtr: wci_7_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14578,8 +14412,8 @@ module mkOCCP(pciDevice, endcase end assign wci_7_reqF_q_0_EN = - WILL_FIRE_RL_wci_7_reqF_both || WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r || + WILL_FIRE_RL_wci_7_reqF_both || WILL_FIRE_RL_wci_7_reqF_decCtr ; // register wci_7_reqPend @@ -14610,7 +14444,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_7_reqTO_EN = WILL_FIRE_RL_wci_7_wrkBusy && - wci_7_wciResponse_wget__220_BITS_33_TO_32_221__ETC___d1249 || + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 || WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; @@ -14623,7 +14457,7 @@ module mkOCCP(pciDevice, assign wci_7_respTimrAct_D_IN = wci_7_reqF_cntr_r ; assign wci_7_respTimrAct_EN = WILL_FIRE_RL_wci_7_wrkBusy && - (!wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 || + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || wci_7_wciResponse_wget[33:32] != 2'd0) || wci_7_reqF_cntr_r ; @@ -14659,7 +14493,7 @@ module mkOCCP(pciDevice, assign wci_7_wStatus_D_IN = { 4'b0, !wci_7_lastOpWrite[1] || wci_7_lastOpWrite[0], - IF_wci_7_lastControlOp_310_BIT_3_311_THEN_wci__ETC___d1325 } ; + IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308 } ; assign wci_7_wStatus_EN = 1'd1 ; // register wci_7_wTimeout @@ -14674,7 +14508,7 @@ module mkOCCP(pciDevice, assign wci_8_busy_D_IN = !MUX_wci_8_busy_write_1__SEL_1 ; assign wci_8_busy_EN = WILL_FIRE_RL_wci_8_wrkBusy && - (!wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 || + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || wci_8_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || @@ -14747,15 +14581,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_8_reqF_decCtr ; // register wci_8_reqF_q_0 - always@(WILL_FIRE_RL_wci_8_reqF_both or + always@(MUX_wci_8_reqF_q_0_write_1__SEL_1 or MUX_wci_8_reqF_q_0_write_1__VAL_1 or - MUX_wci_8_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_8_reqF_both or MUX_wci_8_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_8_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_8_reqF_both: + MUX_wci_8_reqF_q_0_write_1__SEL_1: wci_8_reqF_q_0_D_IN = MUX_wci_8_reqF_q_0_write_1__VAL_1; - MUX_wci_8_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_8_reqF_both: wci_8_reqF_q_0_D_IN = MUX_wci_8_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_8_reqF_decCtr: wci_8_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14764,8 +14598,8 @@ module mkOCCP(pciDevice, endcase end assign wci_8_reqF_q_0_EN = - WILL_FIRE_RL_wci_8_reqF_both || WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r || + WILL_FIRE_RL_wci_8_reqF_both || WILL_FIRE_RL_wci_8_reqF_decCtr ; // register wci_8_reqPend @@ -14796,7 +14630,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_8_reqTO_EN = WILL_FIRE_RL_wci_8_wrkBusy && - wci_8_wciResponse_wget__360_BITS_33_TO_32_361__ETC___d1389 || + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 || WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; @@ -14809,7 +14643,7 @@ module mkOCCP(pciDevice, assign wci_8_respTimrAct_D_IN = wci_8_reqF_cntr_r ; assign wci_8_respTimrAct_EN = WILL_FIRE_RL_wci_8_wrkBusy && - (!wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 || + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || wci_8_wciResponse_wget[33:32] != 2'd0) || wci_8_reqF_cntr_r ; @@ -14845,7 +14679,7 @@ module mkOCCP(pciDevice, assign wci_8_wStatus_D_IN = { 4'b0, !wci_8_lastOpWrite[1] || wci_8_lastOpWrite[0], - IF_wci_8_lastControlOp_450_BIT_3_451_THEN_wci__ETC___d1465 } ; + IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448 } ; assign wci_8_wStatus_EN = 1'd1 ; // register wci_8_wTimeout @@ -14860,7 +14694,7 @@ module mkOCCP(pciDevice, assign wci_9_busy_D_IN = !MUX_wci_9_busy_write_1__SEL_1 ; assign wci_9_busy_EN = WILL_FIRE_RL_wci_9_wrkBusy && - (!wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 || + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || wci_9_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || @@ -14933,15 +14767,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_9_reqF_decCtr ; // register wci_9_reqF_q_0 - always@(WILL_FIRE_RL_wci_9_reqF_both or + always@(MUX_wci_9_reqF_q_0_write_1__SEL_1 or MUX_wci_9_reqF_q_0_write_1__VAL_1 or - MUX_wci_9_reqF_q_0_write_1__SEL_2 or + WILL_FIRE_RL_wci_9_reqF_both or MUX_wci_9_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_9_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_9_reqF_both: + MUX_wci_9_reqF_q_0_write_1__SEL_1: wci_9_reqF_q_0_D_IN = MUX_wci_9_reqF_q_0_write_1__VAL_1; - MUX_wci_9_reqF_q_0_write_1__SEL_2: + WILL_FIRE_RL_wci_9_reqF_both: wci_9_reqF_q_0_D_IN = MUX_wci_9_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_9_reqF_decCtr: wci_9_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14950,8 +14784,8 @@ module mkOCCP(pciDevice, endcase end assign wci_9_reqF_q_0_EN = - WILL_FIRE_RL_wci_9_reqF_both || WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r || + WILL_FIRE_RL_wci_9_reqF_both || WILL_FIRE_RL_wci_9_reqF_decCtr ; // register wci_9_reqPend @@ -14982,7 +14816,7 @@ module mkOCCP(pciDevice, 3'd0 ; assign wci_9_reqTO_EN = WILL_FIRE_RL_wci_9_wrkBusy && - wci_9_wciResponse_wget__500_BITS_33_TO_32_501__ETC___d1529 || + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 || WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; @@ -14995,7 +14829,7 @@ module mkOCCP(pciDevice, assign wci_9_respTimrAct_D_IN = wci_9_reqF_cntr_r ; assign wci_9_respTimrAct_EN = WILL_FIRE_RL_wci_9_wrkBusy && - (!wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 || + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || wci_9_wciResponse_wget[33:32] != 2'd0) || wci_9_reqF_cntr_r ; @@ -15031,7 +14865,7 @@ module mkOCCP(pciDevice, assign wci_9_wStatus_D_IN = { 4'b0, !wci_9_lastOpWrite[1] || wci_9_lastOpWrite[0], - IF_wci_9_lastControlOp_590_BIT_3_591_THEN_wci__ETC___d1605 } ; + IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588 } ; assign wci_9_wStatus_EN = 1'd1 ; // register wci_9_wTimeout @@ -15044,13 +14878,13 @@ module mkOCCP(pciDevice, // register wrkAct always@(MUX_wrkAct_write_1__SEL_1 or - _theResult_____1__h78175 or + _theResult_____1__h75724 or MUX_wrkAct_write_1__SEL_2 or - _theResult_____1__h78190 or MUX_wrkAct_write_1__SEL_3) + _theResult_____1__h75739 or MUX_wrkAct_write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_wrkAct_write_1__SEL_1: wrkAct_D_IN = _theResult_____1__h78175; - MUX_wrkAct_write_1__SEL_2: wrkAct_D_IN = _theResult_____1__h78190; + MUX_wrkAct_write_1__SEL_1: wrkAct_D_IN = _theResult_____1__h75724; + MUX_wrkAct_write_1__SEL_2: wrkAct_D_IN = _theResult_____1__h75739; MUX_wrkAct_write_1__SEL_3: wrkAct_D_IN = 4'd0; default: wrkAct_D_IN = 4'b1010 /* unspecified value */ ; endcase @@ -15344,40 +15178,34 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'h24 || cpReq[11:4] == 8'h28 || cpReq[11:4] == 8'h2C, - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 } ; assign adminResp1F_ENQ = WILL_FIRE_RL_cpDispatch_F_T_T_T ; assign adminResp1F_DEQ = WILL_FIRE_RL_readAdminResponseCollect && adminResp1F_EMPTY_N ; assign adminResp1F_CLR = 1'b0 ; // submodule adminResp2F - always@(MUX_adminResp2F_enq_1__SEL_1 or + always@(WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T or MUX_adminResp2F_enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T or + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T or MUX_adminResp2F_enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T or - MUX_adminResp2F_enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F or - MUX_adminResp2F_enq_1__VAL_4) + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F or + MUX_adminResp2F_enq_1__VAL_3) begin case (1'b1) // synopsys parallel_case - MUX_adminResp2F_enq_1__SEL_1: - adminResp2F_D_IN = MUX_adminResp2F_enq_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T: + adminResp2F_D_IN = MUX_adminResp2F_enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T: adminResp2F_D_IN = MUX_adminResp2F_enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T: + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F: adminResp2F_D_IN = MUX_adminResp2F_enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F: - adminResp2F_D_IN = MUX_adminResp2F_enq_1__VAL_4; default: adminResp2F_D_IN = 33'h0AAAAAAAA /* unspecified value */ ; endcase end assign adminResp2F_ENQ = - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_F ; + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F ; assign adminResp2F_DEQ = WILL_FIRE_RL_readAdminResponseCollect && !adminResp1F_EMPTY_N && adminResp2F_EMPTY_N ; @@ -15422,7 +15250,7 @@ module mkOCCP(pciDevice, assign adminRespF_D_IN = adminResp1F_EMPTY_N ? adminResp1F_D_OUT : - IF_adminResp2F_notEmpty__321_THEN_adminResp2F__ETC___d2359 ; + IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342 ; assign adminRespF_ENQ = WILL_FIRE_RL_readAdminResponseCollect && (adminResp1F_EMPTY_N || adminResp2F_EMPTY_N || @@ -15431,21 +15259,6 @@ module mkOCCP(pciDevice, assign adminRespF_DEQ = WILL_FIRE_RL_responseAdminRd ; assign adminRespF_CLR = 1'b0 ; - // submodule bluart - assign bluart_pads_cts_arg = upads_cts_arg ; - assign bluart_pads_rx_arg = upads_rx_arg ; - assign bluart_setClkDiv_put = cpReq[43:28] ; - assign bluart_txChar_put = - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T ? - cpReq[35:28] : - MUX_bluart_txChar_put_1__VAL_2 ; - assign bluart_EN_setClkDiv_put = - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_T ; - assign bluart_EN_txChar_put = - WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F_F_T || - WILL_FIRE_RL_init_uart_text ; - assign bluart_EN_rxChar_get = WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F_F_T ; - // submodule cpReqF assign cpReqF_D_IN = server_request_put ; assign cpReqF_ENQ = EN_server_request_put ; @@ -15566,7 +15379,7 @@ module mkOCCP(pciDevice, end assign wci_0_respF_ENQ = WILL_FIRE_RL_wci_0_wrkBusy && - (!wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 || + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || wci_0_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || @@ -15624,7 +15437,7 @@ module mkOCCP(pciDevice, end assign wci_10_respF_ENQ = WILL_FIRE_RL_wci_10_wrkBusy && - (!wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 || + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || wci_10_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || @@ -15682,7 +15495,7 @@ module mkOCCP(pciDevice, end assign wci_11_respF_ENQ = WILL_FIRE_RL_wci_11_wrkBusy && - (!wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 || + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || wci_11_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || @@ -15740,7 +15553,7 @@ module mkOCCP(pciDevice, end assign wci_12_respF_ENQ = WILL_FIRE_RL_wci_12_wrkBusy && - (!wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 || + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || wci_12_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || @@ -15798,7 +15611,7 @@ module mkOCCP(pciDevice, end assign wci_13_respF_ENQ = WILL_FIRE_RL_wci_13_wrkBusy && - (!wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 || + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || wci_13_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || @@ -15856,7 +15669,7 @@ module mkOCCP(pciDevice, end assign wci_14_respF_ENQ = WILL_FIRE_RL_wci_14_wrkBusy && - (!wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 || + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || wci_14_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || @@ -15913,7 +15726,7 @@ module mkOCCP(pciDevice, end assign wci_1_respF_ENQ = WILL_FIRE_RL_wci_1_wrkBusy && - (!wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 || + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || wci_1_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || @@ -15970,7 +15783,7 @@ module mkOCCP(pciDevice, end assign wci_2_respF_ENQ = WILL_FIRE_RL_wci_2_wrkBusy && - (!wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 || + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || wci_2_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || @@ -16027,7 +15840,7 @@ module mkOCCP(pciDevice, end assign wci_3_respF_ENQ = WILL_FIRE_RL_wci_3_wrkBusy && - (!wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 || + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || wci_3_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || @@ -16084,7 +15897,7 @@ module mkOCCP(pciDevice, end assign wci_4_respF_ENQ = WILL_FIRE_RL_wci_4_wrkBusy && - (!wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 || + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || wci_4_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || @@ -16141,7 +15954,7 @@ module mkOCCP(pciDevice, end assign wci_5_respF_ENQ = WILL_FIRE_RL_wci_5_wrkBusy && - (!wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 || + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || wci_5_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || @@ -16198,7 +16011,7 @@ module mkOCCP(pciDevice, end assign wci_6_respF_ENQ = WILL_FIRE_RL_wci_6_wrkBusy && - (!wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 || + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || wci_6_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || @@ -16255,7 +16068,7 @@ module mkOCCP(pciDevice, end assign wci_7_respF_ENQ = WILL_FIRE_RL_wci_7_wrkBusy && - (!wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 || + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || wci_7_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || @@ -16312,7 +16125,7 @@ module mkOCCP(pciDevice, end assign wci_8_respF_ENQ = WILL_FIRE_RL_wci_8_wrkBusy && - (!wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 || + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || wci_8_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || @@ -16369,7 +16182,7 @@ module mkOCCP(pciDevice, end assign wci_9_respF_ENQ = WILL_FIRE_RL_wci_9_wrkBusy && - (!wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 || + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || wci_9_wciResponse_wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || @@ -16390,202 +16203,202 @@ module mkOCCP(pciDevice, assign wci_9_respF_CLR = 1'b0 ; // remaining internal signals - assign IF_adminResp2F_notEmpty__321_THEN_adminResp2F__ETC___d2359 = + assign IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342 = adminResp2F_EMPTY_N ? adminResp2F_D_OUT : (adminResp3F_EMPTY_N ? adminResp3F_D_OUT : adminResp4F_D_OUT) ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5025 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934 = (cpReq[37:36] == 2'd2) ? !wci_0_wReset_n || !wci_0_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5024 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5031 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940 = (cpReq[37:36] == 2'd2) ? !wci_1_wReset_n || !wci_1_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5030 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5037 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946 = (cpReq[37:36] == 2'd2) ? !wci_2_wReset_n || !wci_2_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5036 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5043 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952 = (cpReq[37:36] == 2'd2) ? !wci_3_wReset_n || !wci_3_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5042 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5049 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958 = (cpReq[37:36] == 2'd2) ? !wci_4_wReset_n || !wci_4_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5048 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5055 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964 = (cpReq[37:36] == 2'd2) ? !wci_5_wReset_n || !wci_5_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5054 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5061 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970 = (cpReq[37:36] == 2'd2) ? !wci_6_wReset_n || !wci_6_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5060 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5067 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976 = (cpReq[37:36] == 2'd2) ? !wci_7_wReset_n || !wci_7_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5066 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5073 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982 = (cpReq[37:36] == 2'd2) ? !wci_8_wReset_n || !wci_8_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5072 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5079 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988 = (cpReq[37:36] == 2'd2) ? !wci_9_wReset_n || !wci_9_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5078 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5085 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994 = (cpReq[37:36] == 2'd2) ? !wci_10_wReset_n || !wci_10_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5084 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5091 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000 = (cpReq[37:36] == 2'd2) ? !wci_11_wReset_n || !wci_11_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5090 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5097 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006 = (cpReq[37:36] == 2'd2) ? !wci_12_wReset_n || !wci_12_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5096 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5103 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012 = (cpReq[37:36] == 2'd2) ? !wci_13_wReset_n || !wci_13_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5102 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5109 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018 = (cpReq[37:36] == 2'd2) ? !wci_14_wReset_n || !wci_14_reqF_cntr_r : - NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5108 ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5023 = + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 = (cpReq[37:36] == 2'd2) ? wci_0_wReset_n || wci_0_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_0_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5029 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 = (cpReq[37:36] == 2'd2) ? wci_1_wReset_n || wci_1_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_1_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5035 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 = (cpReq[37:36] == 2'd2) ? wci_2_wReset_n || wci_2_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_2_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5041 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 = (cpReq[37:36] == 2'd2) ? wci_3_wReset_n || wci_3_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_3_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5047 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 = (cpReq[37:36] == 2'd2) ? wci_4_wReset_n || wci_4_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_4_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5053 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 = (cpReq[37:36] == 2'd2) ? wci_5_wReset_n || wci_5_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_5_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5059 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 = (cpReq[37:36] == 2'd2) ? wci_6_wReset_n || wci_6_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_6_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5065 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 = (cpReq[37:36] == 2'd2) ? wci_7_wReset_n || wci_7_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_7_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5071 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 = (cpReq[37:36] == 2'd2) ? wci_8_wReset_n || wci_8_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_8_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5077 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 = (cpReq[37:36] == 2'd2) ? wci_9_wReset_n || wci_9_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_9_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5083 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 = (cpReq[37:36] == 2'd2) ? wci_10_wReset_n || wci_10_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_10_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5089 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 = (cpReq[37:36] == 2'd2) ? wci_11_wReset_n || wci_11_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_11_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5095 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 = (cpReq[37:36] == 2'd2) ? wci_12_wReset_n || wci_12_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_12_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5101 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 = (cpReq[37:36] == 2'd2) ? wci_13_wReset_n || wci_13_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_13_respF_FULL_N ; - assign IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5107 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 = (cpReq[37:36] == 2'd2) ? wci_14_wReset_n || wci_14_respF_FULL_N : cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || wci_14_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3671 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580 = (cpReq[61:60] == 2'd2) ? !wci_0_wReset_n || !wci_0_reqF_cntr_r : wci_0_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3675 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584 = (cpReq[61:60] == 2'd2) ? !wci_1_wReset_n || !wci_1_reqF_cntr_r : wci_1_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3679 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588 = (cpReq[61:60] == 2'd2) ? !wci_2_wReset_n || !wci_2_reqF_cntr_r : wci_2_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3683 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592 = (cpReq[61:60] == 2'd2) ? !wci_3_wReset_n || !wci_3_reqF_cntr_r : wci_3_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3687 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596 = (cpReq[61:60] == 2'd2) ? !wci_4_wReset_n || !wci_4_reqF_cntr_r : wci_4_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3691 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600 = (cpReq[61:60] == 2'd2) ? !wci_5_wReset_n || !wci_5_reqF_cntr_r : wci_5_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3695 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604 = (cpReq[61:60] == 2'd2) ? !wci_6_wReset_n || !wci_6_reqF_cntr_r : wci_6_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3699 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608 = (cpReq[61:60] == 2'd2) ? !wci_7_wReset_n || !wci_7_reqF_cntr_r : wci_7_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3703 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612 = (cpReq[61:60] == 2'd2) ? !wci_8_wReset_n || !wci_8_reqF_cntr_r : wci_8_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3707 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616 = (cpReq[61:60] == 2'd2) ? !wci_9_wReset_n || !wci_9_reqF_cntr_r : wci_9_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3711 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620 = (cpReq[61:60] == 2'd2) ? !wci_10_wReset_n || !wci_10_reqF_cntr_r : wci_10_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3715 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624 = (cpReq[61:60] == 2'd2) ? !wci_11_wReset_n || !wci_11_reqF_cntr_r : wci_11_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3719 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628 = (cpReq[61:60] == 2'd2) ? !wci_12_wReset_n || !wci_12_reqF_cntr_r : wci_12_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3723 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632 = (cpReq[61:60] == 2'd2) ? !wci_13_wReset_n || !wci_13_reqF_cntr_r : wci_13_respF_FULL_N ; - assign IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3727 = + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636 = (cpReq[61:60] == 2'd2) ? !wci_14_wReset_n || !wci_14_reqF_cntr_r : wci_14_respF_FULL_N ; @@ -16593,7 +16406,7 @@ module mkOCCP(pciDevice, timeServ_ppsOK ? timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD : timeServ_delSec != timeServ_fracSeconds[49:48] ; - assign IF_wci_0_lastControlOp_30_BIT_3_31_THEN_wci_0__ETC___d345 = + assign IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328 = { wci_0_lastControlOp[3] ? wci_0_lastControlOp[2:0] : 3'b111, wci_0_lastConfigBE[4] ? wci_0_lastConfigBE[3:0] : 4'hF, wci_0_lastOpWrite[1], @@ -16605,7 +16418,7 @@ module mkOCCP(pciDevice, wci_0_reqTO, wci_0_reqFAIL, wci_0_reqERR } ; - assign IF_wci_10_lastControlOp_730_BIT_3_731_THEN_wci_ETC___d1745 = + assign IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728 = { wci_10_lastControlOp[3] ? wci_10_lastControlOp[2:0] : 3'b111, wci_10_lastConfigBE[4] ? wci_10_lastConfigBE[3:0] : 4'hF, wci_10_lastOpWrite[1], @@ -16617,7 +16430,7 @@ module mkOCCP(pciDevice, wci_10_reqTO, wci_10_reqFAIL, wci_10_reqERR } ; - assign IF_wci_11_lastControlOp_870_BIT_3_871_THEN_wci_ETC___d1885 = + assign IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868 = { wci_11_lastControlOp[3] ? wci_11_lastControlOp[2:0] : 3'b111, wci_11_lastConfigBE[4] ? wci_11_lastConfigBE[3:0] : 4'hF, wci_11_lastOpWrite[1], @@ -16629,7 +16442,7 @@ module mkOCCP(pciDevice, wci_11_reqTO, wci_11_reqFAIL, wci_11_reqERR } ; - assign IF_wci_12_lastControlOp_010_BIT_3_011_THEN_wci_ETC___d2025 = + assign IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008 = { wci_12_lastControlOp[3] ? wci_12_lastControlOp[2:0] : 3'b111, wci_12_lastConfigBE[4] ? wci_12_lastConfigBE[3:0] : 4'hF, wci_12_lastOpWrite[1], @@ -16641,7 +16454,7 @@ module mkOCCP(pciDevice, wci_12_reqTO, wci_12_reqFAIL, wci_12_reqERR } ; - assign IF_wci_13_lastControlOp_150_BIT_3_151_THEN_wci_ETC___d2165 = + assign IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148 = { wci_13_lastControlOp[3] ? wci_13_lastControlOp[2:0] : 3'b111, wci_13_lastConfigBE[4] ? wci_13_lastConfigBE[3:0] : 4'hF, wci_13_lastOpWrite[1], @@ -16653,7 +16466,7 @@ module mkOCCP(pciDevice, wci_13_reqTO, wci_13_reqFAIL, wci_13_reqERR } ; - assign IF_wci_14_lastControlOp_290_BIT_3_291_THEN_wci_ETC___d2305 = + assign IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288 = { wci_14_lastControlOp[3] ? wci_14_lastControlOp[2:0] : 3'b111, wci_14_lastConfigBE[4] ? wci_14_lastConfigBE[3:0] : 4'hF, wci_14_lastOpWrite[1], @@ -16665,7 +16478,7 @@ module mkOCCP(pciDevice, wci_14_reqTO, wci_14_reqFAIL, wci_14_reqERR } ; - assign IF_wci_1_lastControlOp_70_BIT_3_71_THEN_wci_1__ETC___d485 = + assign IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468 = { wci_1_lastControlOp[3] ? wci_1_lastControlOp[2:0] : 3'b111, wci_1_lastConfigBE[4] ? wci_1_lastConfigBE[3:0] : 4'hF, wci_1_lastOpWrite[1], @@ -16677,7 +16490,7 @@ module mkOCCP(pciDevice, wci_1_reqTO, wci_1_reqFAIL, wci_1_reqERR } ; - assign IF_wci_2_lastControlOp_10_BIT_3_11_THEN_wci_2__ETC___d625 = + assign IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608 = { wci_2_lastControlOp[3] ? wci_2_lastControlOp[2:0] : 3'b111, wci_2_lastConfigBE[4] ? wci_2_lastConfigBE[3:0] : 4'hF, wci_2_lastOpWrite[1], @@ -16689,7 +16502,7 @@ module mkOCCP(pciDevice, wci_2_reqTO, wci_2_reqFAIL, wci_2_reqERR } ; - assign IF_wci_3_lastControlOp_50_BIT_3_51_THEN_wci_3__ETC___d765 = + assign IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748 = { wci_3_lastControlOp[3] ? wci_3_lastControlOp[2:0] : 3'b111, wci_3_lastConfigBE[4] ? wci_3_lastConfigBE[3:0] : 4'hF, wci_3_lastOpWrite[1], @@ -16701,7 +16514,7 @@ module mkOCCP(pciDevice, wci_3_reqTO, wci_3_reqFAIL, wci_3_reqERR } ; - assign IF_wci_4_lastControlOp_90_BIT_3_91_THEN_wci_4__ETC___d905 = + assign IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888 = { wci_4_lastControlOp[3] ? wci_4_lastControlOp[2:0] : 3'b111, wci_4_lastConfigBE[4] ? wci_4_lastConfigBE[3:0] : 4'hF, wci_4_lastOpWrite[1], @@ -16713,7 +16526,7 @@ module mkOCCP(pciDevice, wci_4_reqTO, wci_4_reqFAIL, wci_4_reqERR } ; - assign IF_wci_5_lastControlOp_030_BIT_3_031_THEN_wci__ETC___d1045 = + assign IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028 = { wci_5_lastControlOp[3] ? wci_5_lastControlOp[2:0] : 3'b111, wci_5_lastConfigBE[4] ? wci_5_lastConfigBE[3:0] : 4'hF, wci_5_lastOpWrite[1], @@ -16725,7 +16538,7 @@ module mkOCCP(pciDevice, wci_5_reqTO, wci_5_reqFAIL, wci_5_reqERR } ; - assign IF_wci_6_lastControlOp_170_BIT_3_171_THEN_wci__ETC___d1185 = + assign IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168 = { wci_6_lastControlOp[3] ? wci_6_lastControlOp[2:0] : 3'b111, wci_6_lastConfigBE[4] ? wci_6_lastConfigBE[3:0] : 4'hF, wci_6_lastOpWrite[1], @@ -16737,7 +16550,7 @@ module mkOCCP(pciDevice, wci_6_reqTO, wci_6_reqFAIL, wci_6_reqERR } ; - assign IF_wci_7_lastControlOp_310_BIT_3_311_THEN_wci__ETC___d1325 = + assign IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308 = { wci_7_lastControlOp[3] ? wci_7_lastControlOp[2:0] : 3'b111, wci_7_lastConfigBE[4] ? wci_7_lastConfigBE[3:0] : 4'hF, wci_7_lastOpWrite[1], @@ -16749,7 +16562,7 @@ module mkOCCP(pciDevice, wci_7_reqTO, wci_7_reqFAIL, wci_7_reqERR } ; - assign IF_wci_8_lastControlOp_450_BIT_3_451_THEN_wci__ETC___d1465 = + assign IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448 = { wci_8_lastControlOp[3] ? wci_8_lastControlOp[2:0] : 3'b111, wci_8_lastConfigBE[4] ? wci_8_lastConfigBE[3:0] : 4'hF, wci_8_lastOpWrite[1], @@ -16761,7 +16574,7 @@ module mkOCCP(pciDevice, wci_8_reqTO, wci_8_reqFAIL, wci_8_reqERR } ; - assign IF_wci_9_lastControlOp_590_BIT_3_591_THEN_wci__ETC___d1605 = + assign IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588 = { wci_9_lastControlOp[3] ? wci_9_lastControlOp[2:0] : 3'b111, wci_9_lastConfigBE[4] ? wci_9_lastConfigBE[3:0] : 4'hF, wci_9_lastOpWrite[1], @@ -16773,698 +16586,708 @@ module mkOCCP(pciDevice, wci_9_reqTO, wci_9_reqFAIL, wci_9_reqERR } ; - assign NOT_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_TH_ETC___d5114 = - _theResult_____1__h78190 != 4'd0 && - _theResult_____1__h78190 != 4'd1 && - _theResult_____1__h78190 != 4'd2 && - _theResult_____1__h78190 != 4'd3 && - _theResult_____1__h78190 != 4'd4 && - _theResult_____1__h78190 != 4'd5 && - _theResult_____1__h78190 != 4'd6 && - _theResult_____1__h78190 != 4'd7 && - _theResult_____1__h78190 != 4'd8 && - _theResult_____1__h78190 != 4'd9 && - _theResult_____1__h78190 != 4'd10 && - _theResult_____1__h78190 != 4'd11 && - _theResult_____1__h78190 != 4'd12 && - _theResult_____1__h78190 != 4'd13 && - _theResult_____1__h78190 != 4'd14 && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 && + assign NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023 = + _theResult_____1__h75739 != 4'd0 && + _theResult_____1__h75739 != 4'd1 && + _theResult_____1__h75739 != 4'd2 && + _theResult_____1__h75739 != 4'd3 && + _theResult_____1__h75739 != 4'd4 && + _theResult_____1__h75739 != 4'd5 && + _theResult_____1__h75739 != 4'd6 && + _theResult_____1__h75739 != 4'd7 && + _theResult_____1__h75739 != 4'd8 && + _theResult_____1__h75739 != 4'd9 && + _theResult_____1__h75739 != 4'd10 && + _theResult_____1__h75739 != 4'd11 && + _theResult_____1__h75739 != 4'd12 && + _theResult_____1__h75739 != 4'd13 && + _theResult_____1__h75739 != 4'd14 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 && !dispatched ; - assign NOT_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_TH_ETC___d3732 = - _theResult_____1__h78175 != 4'd0 && - _theResult_____1__h78175 != 4'd1 && - _theResult_____1__h78175 != 4'd2 && - _theResult_____1__h78175 != 4'd3 && - _theResult_____1__h78175 != 4'd4 && - _theResult_____1__h78175 != 4'd5 && - _theResult_____1__h78175 != 4'd6 && - _theResult_____1__h78175 != 4'd7 && - _theResult_____1__h78175 != 4'd8 && - _theResult_____1__h78175 != 4'd9 && - _theResult_____1__h78175 != 4'd10 && - _theResult_____1__h78175 != 4'd11 && - _theResult_____1__h78175 != 4'd12 && - _theResult_____1__h78175 != 4'd13 && - _theResult_____1__h78175 != 4'd14 && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 && + assign NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641 = + _theResult_____1__h75724 != 4'd0 && + _theResult_____1__h75724 != 4'd1 && + _theResult_____1__h75724 != 4'd2 && + _theResult_____1__h75724 != 4'd3 && + _theResult_____1__h75724 != 4'd4 && + _theResult_____1__h75724 != 4'd5 && + _theResult_____1__h75724 != 4'd6 && + _theResult_____1__h75724 != 4'd7 && + _theResult_____1__h75724 != 4'd8 && + _theResult_____1__h75724 != 4'd9 && + _theResult_____1__h75724 != 4'd10 && + _theResult_____1__h75724 != 4'd11 && + _theResult_____1__h75724 != 4'd12 && + _theResult_____1__h75724 != 4'd13 && + _theResult_____1__h75724 != 4'd14 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 && + !dispatched ; + assign NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712 = + cpReq[11:4] != 8'h30 && cpReq[11:4] != 8'h34 && + cpReq[11:4] != 8'h38 && + cpReq[11:4] != 8'h3C && + cpReq[11:4] != 8'h40 && + cpReq[11:4] != 8'h44 && + cpReq[11:4] != 8'h48 && + cpReq[11:4] != 8'h4C && + adminResp2F_FULL_N && !dispatched ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3887 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 = cpReq[9:6] == 4'h8 && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3896 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 = cpReq[9:6] == 4'h9 && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3907 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 = cpReq[9:6] == 4'hA && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d3918 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 = cpReq[9:6] == 4'hC && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5024 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_0_wReset_n || wci_0_respF_FULL_N) && (!wci_0_wReset_n || !wci_0_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5030 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_1_wReset_n || wci_1_respF_FULL_N) && (!wci_1_wReset_n || !wci_1_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5036 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_2_wReset_n || wci_2_respF_FULL_N) && (!wci_2_wReset_n || !wci_2_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5042 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_3_wReset_n || wci_3_respF_FULL_N) && (!wci_3_wReset_n || !wci_3_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5048 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_4_wReset_n || wci_4_respF_FULL_N) && (!wci_4_wReset_n || !wci_4_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5054 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_5_wReset_n || wci_5_respF_FULL_N) && (!wci_5_wReset_n || !wci_5_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5060 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_6_wReset_n || wci_6_respF_FULL_N) && (!wci_6_wReset_n || !wci_6_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5066 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_7_wReset_n || wci_7_respF_FULL_N) && (!wci_7_wReset_n || !wci_7_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5072 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_8_wReset_n || wci_8_respF_FULL_N) && (!wci_8_wReset_n || !wci_8_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5078 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_9_wReset_n || wci_9_respF_FULL_N) && (!wci_9_wReset_n || !wci_9_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5084 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_10_wReset_n || wci_10_respF_FULL_N) && (!wci_10_wReset_n || !wci_10_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5090 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_11_wReset_n || wci_11_respF_FULL_N) && (!wci_11_wReset_n || !wci_11_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5096 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_12_wReset_n || wci_12_respF_FULL_N) && (!wci_12_wReset_n || !wci_12_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5102 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_13_wReset_n || wci_13_respF_FULL_N) && (!wci_13_wReset_n || !wci_13_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_37_TO_36_740_EQ_1_794_851_O_ETC___d5108 = + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017 = cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || (wci_14_wReset_n || wci_14_respF_FULL_N) && (!wci_14_wReset_n || !wci_14_reqF_cntr_r) ; - assign NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3120 = + assign NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 = cpReq[9:6] == 4'hC && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign NOT_cpReq_380_BITS_61_TO_60_939_EQ_1_058_084_O_ETC___d3130 = + assign NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 = (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && cpReq[9:6] != 4'hC && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3779 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] == 2'd2 && wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3792 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] == 2'd2 && !wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3833 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3848 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_0_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3949 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] == 2'd2 && wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3961 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] == 2'd2 && !wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3974 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d3984 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_1_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4026 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] == 2'd2 && wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4038 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] == 2'd2 && !wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4049 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4059 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_2_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4101 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] == 2'd2 && wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4113 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] == 2'd2 && !wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4124 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4134 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_3_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4176 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] == 2'd2 && wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4188 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] == 2'd2 && !wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4199 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4209 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_4_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4251 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] == 2'd2 && wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4263 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] == 2'd2 && !wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4274 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4284 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_5_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4326 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] == 2'd2 && wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4338 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] == 2'd2 && !wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4349 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4359 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_6_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4401 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] == 2'd2 && wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4413 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] == 2'd2 && !wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4424 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4434 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_7_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4476 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] == 2'd2 && wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4488 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] == 2'd2 && !wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4499 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4509 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_8_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4551 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] == 2'd2 && wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4563 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] == 2'd2 && !wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4574 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4584 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_9_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4626 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] == 2'd2 && wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4638 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] == 2'd2 && !wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4649 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4659 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_10_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4701 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] == 2'd2 && wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4713 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] == 2'd2 && !wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4724 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4734 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_11_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4776 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] == 2'd2 && wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4788 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] == 2'd2 && !wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4799 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4809 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_12_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4851 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] == 2'd2 && wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4863 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] == 2'd2 && !wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4874 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4884 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_13_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4926 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] == 2'd2 && wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4938 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] == 2'd2 && !wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4949 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 && !dispatched ; - assign NOT_cpReq_380_BITS_64_TO_62_381_EQ_2_465_737_A_ETC___d4959 = + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868 = cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h78190 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_14_wReset_n && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 && !dispatched ; - assign NOT_cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_126_A_ETC___d3930 = + assign NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 = cpReq[9:6] != 4'h9 && cpReq[9:6] != 4'hA && cpReq[9:6] != 4'hC && - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 = + assign NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 = !wci_0_busy && (wci_0_wReset_n || wci_0_respF_FULL_N) && (!wci_0_wReset_n || !wci_0_reqF_cntr_r) ; - assign NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 = + assign NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 = !wci_10_busy && (wci_10_wReset_n || wci_10_respF_FULL_N) && (!wci_10_wReset_n || !wci_10_reqF_cntr_r) ; - assign NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 = + assign NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 = !wci_11_busy && (wci_11_wReset_n || wci_11_respF_FULL_N) && (!wci_11_wReset_n || !wci_11_reqF_cntr_r) ; - assign NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 = + assign NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 = !wci_12_busy && (wci_12_wReset_n || wci_12_respF_FULL_N) && (!wci_12_wReset_n || !wci_12_reqF_cntr_r) ; - assign NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 = + assign NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 = !wci_13_busy && (wci_13_wReset_n || wci_13_respF_FULL_N) && (!wci_13_wReset_n || !wci_13_reqF_cntr_r) ; - assign NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033 = + assign NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942 = !wci_14_busy && (wci_14_wReset_n || wci_14_respF_FULL_N) && (!wci_14_wReset_n || !wci_14_reqF_cntr_r) ; - assign NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 = + assign NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 = !wci_1_busy && (wci_1_wReset_n || wci_1_respF_FULL_N) && (!wci_1_wReset_n || !wci_1_reqF_cntr_r) ; - assign NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 = + assign NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 = !wci_2_busy && (wci_2_wReset_n || wci_2_respF_FULL_N) && (!wci_2_wReset_n || !wci_2_reqF_cntr_r) ; - assign NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 = + assign NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 = !wci_3_busy && (wci_3_wReset_n || wci_3_respF_FULL_N) && (!wci_3_wReset_n || !wci_3_reqF_cntr_r) ; - assign NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 = + assign NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 = !wci_4_busy && (wci_4_wReset_n || wci_4_respF_FULL_N) && (!wci_4_wReset_n || !wci_4_reqF_cntr_r) ; - assign NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 = + assign NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 = !wci_5_busy && (wci_5_wReset_n || wci_5_respF_FULL_N) && (!wci_5_wReset_n || !wci_5_reqF_cntr_r) ; - assign NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 = + assign NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 = !wci_6_busy && (wci_6_wReset_n || wci_6_respF_FULL_N) && (!wci_6_wReset_n || !wci_6_reqF_cntr_r) ; - assign NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 = + assign NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 = !wci_7_busy && (wci_7_wReset_n || wci_7_respF_FULL_N) && (!wci_7_wReset_n || !wci_7_reqF_cntr_r) ; - assign NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 = + assign NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 = !wci_8_busy && (wci_8_wReset_n || wci_8_respF_FULL_N) && (!wci_8_wReset_n || !wci_8_reqF_cntr_r) ; - assign NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 = + assign NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 = !wci_9_busy && (wci_9_wReset_n || wci_9_respF_FULL_N) && (!wci_9_wReset_n || !wci_9_reqF_cntr_r) ; assign _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 = _281474976710656_MINUS_timeServ_delSecond__q1[49:28] ; assign _281474976710656_MINUS_timeServ_delSecond__q1 = 50'h1000000000000 - timeServ_delSecond ; - assign _theResult_____1__h78175 = - (cpReq[61:60] == 2'd2) ? wn___1__h79049 : wn__h78174 ; - assign _theResult_____1__h78190 = - (cpReq[37:36] == 2'd2) ? wn___1__h79049 : wn__h78174 ; - assign bAddr__h113646 = { cpReqF_D_OUT[57:36], 2'b0 } ; - assign bAddr__h114105 = { cpReqF_D_OUT[25:4], 2'b0 } ; - assign cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_OR_cpRe_ETC___d2673 = + assign _theResult_____1__h75724 = + (cpReq[61:60] == 2'd2) ? wn___1__h76499 : wn__h75723 ; + assign _theResult_____1__h75739 = + (cpReq[37:36] == 2'd2) ? wn___1__h76499 : wn__h75723 ; + assign bAddr__h110990 = { cpReqF_D_OUT[57:36], 2'b0 } ; + assign bAddr__h111449 = { cpReqF_D_OUT[25:4], 2'b0 } ; + assign cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632 = (cpReq[11:4] == 8'h30 || cpReq[11:4] == 8'h34 || cpReq[11:4] == 8'h38 || cpReq[11:4] == 8'h3C || @@ -17472,75 +17295,31 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'h44 || cpReq[11:4] == 8'h48) && adminResp2F_FULL_N && - (cpReq[11:4] != 8'h68 || bluart_RDY_rxChar_get) && - !dispatched ; - assign cpReq_380_BITS_11_TO_4_383_EQ_0x50_637_OR_cpRe_ETC___d2768 = - (cpReq[11:4] == 8'h50 || cpReq[11:4] == 8'h54 || - cpReq[11:4] == 8'h60 || - cpReq[11:4] == 8'h64) && - adminResp2F_FULL_N && - (cpReq[11:4] != 8'h68 || bluart_RDY_rxChar_get) && !dispatched ; - assign cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 = cpReq[11:4] < 8'h30 ; - assign cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2771 = - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && - cpReq[11:4] != 8'h30 && - cpReq[11:4] != 8'h34 && - cpReq[11:4] != 8'h38 && - cpReq[11:4] != 8'h3C && - cpReq[11:4] != 8'h40 && - cpReq[11:4] != 8'h44 && - cpReq[11:4] != 8'h48 && - cpReq[11:4] != 8'h4C && - cpReq_380_BITS_11_TO_4_383_EQ_0x50_637_OR_cpRe_ETC___d2768 ; - assign cpReq_380_BITS_11_TO_4_383_ULT_0xC0_623_AND_NO_ETC___d2799 = - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && - cpReq[11:4] != 8'h30 && - cpReq[11:4] != 8'h34 && - cpReq[11:4] != 8'h38 && - cpReq[11:4] != 8'h3C && - cpReq[11:4] != 8'h40 && - cpReq[11:4] != 8'h44 && - cpReq[11:4] != 8'h48 && - cpReq[11:4] != 8'h4C && - cpReq[11:4] != 8'h50 && - cpReq[11:4] != 8'h54 && - cpReq[11:4] != 8'h60 && - cpReq[11:4] != 8'h64 && - cpReq[11:4] != 8'h68 && - adminResp2F_FULL_N && - !dispatched ; - assign cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 = cpReq[11:4] < 8'hC0 ; - assign cpReq_380_BITS_27_TO_4_466_ULT_0x1000___d2927 = + assign cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 = cpReq[11:4] < 8'h30 ; + assign cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 = cpReq[11:4] < 8'hC0 ; + assign cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 = cpReq[27:4] < 24'h001000 ; - assign cpReq_380_BITS_27_TO_4_466_ULT_0x100_467_AND_N_ETC___d2790 = - cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 && - !cpReq_380_BITS_11_TO_4_383_ULT_0x30___d2468 && - cpReq_380_BITS_11_TO_4_383_ULT_0xC0___d2623 && - cpReq[11:4] == 8'h68 && - adminResp2F_FULL_N && - bluart_RDY_rxChar_get && - !dispatched ; - assign cpReq_380_BITS_27_TO_4_466_ULT_0x100___d2467 = + assign cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 = cpReq[27:4] < 24'h000100 ; - assign cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3107 = + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 = cpReq[9:6] == 4'h9 && !cpReq[37] && cpReq[36] && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_NOT_c_ETC___d3113 = + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 = cpReq[9:6] == 4'h9 && !cpReq[37] && !cpReq[36] && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3092 = + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 = cpReq[9:6] == 4'h9 && cpReq[37] && cpReq[36] && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_380_BITS_9_TO_6_922_EQ_0x9_087_AND_cpReq_ETC___d3100 = + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 = cpReq[9:6] == 4'h9 && cpReq[37] && !cpReq[36] && - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpStatus__h77314 = { 28'd0, rogueTLP } ; - assign crr_data__h77984 = + assign cpStatus__h74863 = { 28'd0, rogueTLP } ; + assign crr_data__h75533 = adminRespF_D_OUT[32] ? adminRespF_D_OUT[31:0] : 32'hDEADC0DE ; assign rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135 = rom_serverAdapter_cnt + @@ -17563,144 +17342,144 @@ module mkOCCP(pciDevice, timeServ_refFromRise <= 28'd199800000 ; assign timeServ_refFromRise_3_ULT_200200000___d50 = timeServ_refFromRise < 28'd200200000 ; - assign toCount__h14143 = 32'd1 << wci_0_wTimeout ; - assign toCount__h18518 = 32'd1 << wci_1_wTimeout ; - assign toCount__h22887 = 32'd1 << wci_2_wTimeout ; - assign toCount__h27256 = 32'd1 << wci_3_wTimeout ; - assign toCount__h31625 = 32'd1 << wci_4_wTimeout ; - assign toCount__h35994 = 32'd1 << wci_5_wTimeout ; - assign toCount__h40363 = 32'd1 << wci_6_wTimeout ; - assign toCount__h44732 = 32'd1 << wci_7_wTimeout ; - assign toCount__h49101 = 32'd1 << wci_8_wTimeout ; - assign toCount__h53470 = 32'd1 << wci_9_wTimeout ; - assign toCount__h57839 = 32'd1 << wci_10_wTimeout ; - assign toCount__h62208 = 32'd1 << wci_11_wTimeout ; - assign toCount__h66577 = 32'd1 << wci_12_wTimeout ; - assign toCount__h70946 = 32'd1 << wci_13_wTimeout ; - assign toCount__h75315 = 32'd1 << wci_14_wTimeout ; - assign wciAddr__h79587 = { wci_0_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79655 = { wci_1_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79723 = { wci_2_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79791 = { wci_3_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79859 = { wci_4_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79927 = { wci_5_pageWindow, cpReq[23:4] } ; - assign wciAddr__h79995 = { wci_6_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80063 = { wci_7_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80131 = { wci_8_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80199 = { wci_9_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80267 = { wci_10_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80335 = { wci_11_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80403 = { wci_12_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80471 = { wci_13_pageWindow, cpReq[23:4] } ; - assign wciAddr__h80539 = { wci_14_pageWindow, cpReq[23:4] } ; - assign wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 = - wci_0_respTimr < toCount__h14143 ; - assign wci_0_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d269 = + assign toCount__h11692 = 32'd1 << wci_0_wTimeout ; + assign toCount__h16067 = 32'd1 << wci_1_wTimeout ; + assign toCount__h20436 = 32'd1 << wci_2_wTimeout ; + assign toCount__h24805 = 32'd1 << wci_3_wTimeout ; + assign toCount__h29174 = 32'd1 << wci_4_wTimeout ; + assign toCount__h33543 = 32'd1 << wci_5_wTimeout ; + assign toCount__h37912 = 32'd1 << wci_6_wTimeout ; + assign toCount__h42281 = 32'd1 << wci_7_wTimeout ; + assign toCount__h46650 = 32'd1 << wci_8_wTimeout ; + assign toCount__h51019 = 32'd1 << wci_9_wTimeout ; + assign toCount__h55388 = 32'd1 << wci_10_wTimeout ; + assign toCount__h59757 = 32'd1 << wci_11_wTimeout ; + assign toCount__h64126 = 32'd1 << wci_12_wTimeout ; + assign toCount__h68495 = 32'd1 << wci_13_wTimeout ; + assign toCount__h72864 = 32'd1 << wci_14_wTimeout ; + assign wciAddr__h77037 = { wci_0_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77105 = { wci_1_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77173 = { wci_2_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77241 = { wci_3_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77309 = { wci_4_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77377 = { wci_5_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77445 = { wci_6_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77513 = { wci_7_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77581 = { wci_8_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77649 = { wci_9_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77717 = { wci_10_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77785 = { wci_11_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77853 = { wci_12_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77921 = { wci_13_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77989 = { wci_14_pageWindow, cpReq[23:4] } ; + assign wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 = + wci_0_respTimr < toCount__h11692 ; + assign wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 = wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || wci_0_reqPend == 2'd3) ; - assign wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 = - wci_10_respTimr < toCount__h57839 ; - assign wci_10_wciResponse_wget__640_BITS_33_TO_32_641_ETC___d1669 = + assign wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 = + wci_10_respTimr < toCount__h55388 ; + assign wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 = wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || wci_10_reqPend == 2'd3) ; - assign wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 = - wci_11_respTimr < toCount__h62208 ; - assign wci_11_wciResponse_wget__780_BITS_33_TO_32_781_ETC___d1809 = + assign wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 = + wci_11_respTimr < toCount__h59757 ; + assign wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 = wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || wci_11_reqPend == 2'd3) ; - assign wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 = - wci_12_respTimr < toCount__h66577 ; - assign wci_12_wciResponse_wget__920_BITS_33_TO_32_921_ETC___d1949 = + assign wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 = + wci_12_respTimr < toCount__h64126 ; + assign wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 = wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || wci_12_reqPend == 2'd3) ; - assign wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 = - wci_13_respTimr < toCount__h70946 ; - assign wci_13_wciResponse_wget__060_BITS_33_TO_32_061_ETC___d2089 = + assign wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 = + wci_13_respTimr < toCount__h68495 ; + assign wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 = wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || wci_13_reqPend == 2'd3) ; - assign wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 = - wci_14_respTimr < toCount__h75315 ; - assign wci_14_wciResponse_wget__200_BITS_33_TO_32_201_ETC___d2229 = + assign wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 = + wci_14_respTimr < toCount__h72864 ; + assign wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 = wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || wci_14_reqPend == 2'd3) ; - assign wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 = - wci_1_respTimr < toCount__h18518 ; - assign wci_1_wciResponse_wget__80_BITS_33_TO_32_81_EQ_ETC___d409 = + assign wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 = + wci_1_respTimr < toCount__h16067 ; + assign wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 = wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || wci_1_reqPend == 2'd3) ; - assign wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 = - wci_2_respTimr < toCount__h22887 ; - assign wci_2_wciResponse_wget__20_BITS_33_TO_32_21_EQ_ETC___d549 = + assign wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 = + wci_2_respTimr < toCount__h20436 ; + assign wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 = wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || wci_2_reqPend == 2'd3) ; - assign wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 = - wci_3_respTimr < toCount__h27256 ; - assign wci_3_wciResponse_wget__60_BITS_33_TO_32_61_EQ_ETC___d689 = + assign wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 = + wci_3_respTimr < toCount__h24805 ; + assign wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 = wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || wci_3_reqPend == 2'd3) ; - assign wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 = - wci_4_respTimr < toCount__h31625 ; - assign wci_4_wciResponse_wget__00_BITS_33_TO_32_01_EQ_ETC___d829 = + assign wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 = + wci_4_respTimr < toCount__h29174 ; + assign wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 = wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || wci_4_reqPend == 2'd3) ; - assign wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 = - wci_5_respTimr < toCount__h35994 ; - assign wci_5_wciResponse_wget__40_BITS_33_TO_32_41_EQ_ETC___d969 = + assign wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 = + wci_5_respTimr < toCount__h33543 ; + assign wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 = wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || wci_5_reqPend == 2'd3) ; - assign wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 = - wci_6_respTimr < toCount__h40363 ; - assign wci_6_wciResponse_wget__080_BITS_33_TO_32_081__ETC___d1109 = + assign wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 = + wci_6_respTimr < toCount__h37912 ; + assign wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 = wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || wci_6_reqPend == 2'd3) ; - assign wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 = - wci_7_respTimr < toCount__h44732 ; - assign wci_7_wciResponse_wget__220_BITS_33_TO_32_221__ETC___d1249 = + assign wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 = + wci_7_respTimr < toCount__h42281 ; + assign wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 = wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || wci_7_reqPend == 2'd3) ; - assign wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 = - wci_8_respTimr < toCount__h49101 ; - assign wci_8_wciResponse_wget__360_BITS_33_TO_32_361__ETC___d1389 = + assign wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 = + wci_8_respTimr < toCount__h46650 ; + assign wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 = wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || wci_8_reqPend == 2'd3) ; - assign wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 = - wci_9_respTimr < toCount__h53470 ; - assign wci_9_wciResponse_wget__500_BITS_33_TO_32_501__ETC___d1529 = + assign wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 = + wci_9_respTimr < toCount__h51019 ; + assign wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 = wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || wci_9_reqPend == 2'd3) ; - assign wn___1__h79049 = cpReq[27:24] - 4'd1 ; - assign wn__h78174 = cpReq[23:20] - 4'd1 ; - assign x__h106938 = + assign wn___1__h76499 = cpReq[27:24] - 4'd1 ; + assign wn__h75723 = cpReq[23:20] - 4'd1 ; + assign x__h104311 = { wci_14_slvPresent, wci_13_slvPresent, wci_12_slvPresent, @@ -17716,7 +17495,7 @@ module mkOCCP(pciDevice, wci_2_slvPresent, wci_1_slvPresent, wci_0_slvPresent } ; - assign x__h107487 = + assign x__h104860 = { wci_14_wStatus[15:0] != 16'd0, wci_13_wStatus[15:0] != 16'd0, wci_12_wStatus[15:0] != 16'd0, @@ -17732,107 +17511,106 @@ module mkOCCP(pciDevice, wci_2_wStatus[15:0] != 16'd0, wci_1_wStatus[15:0] != 16'd0, wci_0_wStatus[15:0] != 16'd0 } ; - assign x__h14303 = wci_0_respTimr + 32'd1 ; - assign x__h18675 = wci_1_respTimr + 32'd1 ; - assign x__h23044 = wci_2_respTimr + 32'd1 ; - assign x__h27413 = wci_3_respTimr + 32'd1 ; - assign x__h31782 = wci_4_respTimr + 32'd1 ; - assign x__h36151 = wci_5_respTimr + 32'd1 ; - assign x__h3692 = { 2'b0, x_f__h4839 } ; - assign x__h40520 = wci_6_respTimr + 32'd1 ; - assign x__h4412 = + assign x__h11852 = wci_0_respTimr + 32'd1 ; + assign x__h16224 = wci_1_respTimr + 32'd1 ; + assign x__h20593 = wci_2_respTimr + 32'd1 ; + assign x__h24962 = wci_3_respTimr + 32'd1 ; + assign x__h29331 = wci_4_respTimr + 32'd1 ; + assign x__h33700 = wci_5_respTimr + 32'd1 ; + assign x__h3688 = { 2'b0, x_f__h4835 } ; + assign x__h38069 = wci_6_respTimr + 32'd1 ; + assign x__h42438 = wci_7_respTimr + 32'd1 ; + assign x__h4408 = { {28{_281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2[21]}}, _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 } ; - assign x__h44889 = wci_7_respTimr + 32'd1 ; - assign x__h4640 = timeServ_fracSeconds + timeServ_fracInc ; - assign x__h4706 = timeServ_refSecCount + 32'd1 ; - assign x__h49258 = wci_8_respTimr + 32'd1 ; - assign x__h53627 = wci_9_respTimr + 32'd1 ; - assign x__h57996 = wci_10_respTimr + 32'd1 ; - assign x__h62365 = wci_11_respTimr + 32'd1 ; - assign x__h66734 = wci_12_respTimr + 32'd1 ; - assign x__h71103 = wci_13_respTimr + 32'd1 ; - assign x__h75472 = wci_14_respTimr + 32'd1 ; - assign x__h9243 = uartTxtP - 6'd2 ; - assign x__h99158 = { cpReq[8:6], 2'b0 } ; - assign x_addr__h99156 = { 27'd0, x__h99158 } ; - assign x_data__h105345 = { wci_0_wReset_n, 26'd0, wci_0_wTimeout } ; - assign x_data__h105351 = + assign x__h4636 = timeServ_fracSeconds + timeServ_fracInc ; + assign x__h46807 = wci_8_respTimr + 32'd1 ; + assign x__h4702 = timeServ_refSecCount + 32'd1 ; + assign x__h51176 = wci_9_respTimr + 32'd1 ; + assign x__h55545 = wci_10_respTimr + 32'd1 ; + assign x__h59914 = wci_11_respTimr + 32'd1 ; + assign x__h64283 = wci_12_respTimr + 32'd1 ; + assign x__h68652 = wci_13_respTimr + 32'd1 ; + assign x__h73021 = wci_14_respTimr + 32'd1 ; + assign x__h96608 = { cpReq[8:6], 2'b0 } ; + assign x_addr__h96606 = { 27'd0, x__h96608 } ; + assign x_data__h102795 = { wci_0_wReset_n, 26'd0, wci_0_wTimeout } ; + assign x_data__h102801 = wci_0_lastConfigAddr[32] ? wci_0_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105396 = { wci_1_wReset_n, 26'd0, wci_1_wTimeout } ; - assign x_data__h105402 = + assign x_data__h102846 = { wci_1_wReset_n, 26'd0, wci_1_wTimeout } ; + assign x_data__h102852 = wci_1_lastConfigAddr[32] ? wci_1_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105447 = { wci_2_wReset_n, 26'd0, wci_2_wTimeout } ; - assign x_data__h105453 = + assign x_data__h102897 = { wci_2_wReset_n, 26'd0, wci_2_wTimeout } ; + assign x_data__h102903 = wci_2_lastConfigAddr[32] ? wci_2_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105498 = { wci_3_wReset_n, 26'd0, wci_3_wTimeout } ; - assign x_data__h105504 = + assign x_data__h102948 = { wci_3_wReset_n, 26'd0, wci_3_wTimeout } ; + assign x_data__h102954 = wci_3_lastConfigAddr[32] ? wci_3_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105549 = { wci_4_wReset_n, 26'd0, wci_4_wTimeout } ; - assign x_data__h105555 = + assign x_data__h102999 = { wci_4_wReset_n, 26'd0, wci_4_wTimeout } ; + assign x_data__h103005 = wci_4_lastConfigAddr[32] ? wci_4_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105600 = { wci_5_wReset_n, 26'd0, wci_5_wTimeout } ; - assign x_data__h105606 = + assign x_data__h103050 = { wci_5_wReset_n, 26'd0, wci_5_wTimeout } ; + assign x_data__h103056 = wci_5_lastConfigAddr[32] ? wci_5_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105651 = { wci_6_wReset_n, 26'd0, wci_6_wTimeout } ; - assign x_data__h105657 = + assign x_data__h103101 = { wci_6_wReset_n, 26'd0, wci_6_wTimeout } ; + assign x_data__h103107 = wci_6_lastConfigAddr[32] ? wci_6_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105702 = { wci_7_wReset_n, 26'd0, wci_7_wTimeout } ; - assign x_data__h105708 = + assign x_data__h103152 = { wci_7_wReset_n, 26'd0, wci_7_wTimeout } ; + assign x_data__h103158 = wci_7_lastConfigAddr[32] ? wci_7_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105753 = { wci_8_wReset_n, 26'd0, wci_8_wTimeout } ; - assign x_data__h105759 = + assign x_data__h103203 = { wci_8_wReset_n, 26'd0, wci_8_wTimeout } ; + assign x_data__h103209 = wci_8_lastConfigAddr[32] ? wci_8_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105804 = { wci_9_wReset_n, 26'd0, wci_9_wTimeout } ; - assign x_data__h105810 = + assign x_data__h103254 = { wci_9_wReset_n, 26'd0, wci_9_wTimeout } ; + assign x_data__h103260 = wci_9_lastConfigAddr[32] ? wci_9_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105855 = { wci_10_wReset_n, 26'd0, wci_10_wTimeout } ; - assign x_data__h105861 = + assign x_data__h103305 = { wci_10_wReset_n, 26'd0, wci_10_wTimeout } ; + assign x_data__h103311 = wci_10_lastConfigAddr[32] ? wci_10_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105906 = { wci_11_wReset_n, 26'd0, wci_11_wTimeout } ; - assign x_data__h105912 = + assign x_data__h103356 = { wci_11_wReset_n, 26'd0, wci_11_wTimeout } ; + assign x_data__h103362 = wci_11_lastConfigAddr[32] ? wci_11_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h105957 = { wci_12_wReset_n, 26'd0, wci_12_wTimeout } ; - assign x_data__h105963 = + assign x_data__h103407 = { wci_12_wReset_n, 26'd0, wci_12_wTimeout } ; + assign x_data__h103413 = wci_12_lastConfigAddr[32] ? wci_12_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h106008 = { wci_13_wReset_n, 26'd0, wci_13_wTimeout } ; - assign x_data__h106014 = + assign x_data__h103458 = { wci_13_wReset_n, 26'd0, wci_13_wTimeout } ; + assign x_data__h103464 = wci_13_lastConfigAddr[32] ? wci_13_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h106059 = { wci_14_wReset_n, 26'd0, wci_14_wTimeout } ; - assign x_data__h106065 = + assign x_data__h103509 = { wci_14_wReset_n, 26'd0, wci_14_wTimeout } ; + assign x_data__h103515 = wci_14_lastConfigAddr[32] ? wci_14_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_f__h4839 = { timeServ_setRefF_dD_OUT[31:0], 16'h0 } ; - assign x_wget__h5217 = { 7'd0, dna_sr } ; + assign x_f__h4835 = { timeServ_setRefF_dD_OUT[31:0], 16'h0 } ; + assign x_wget__h5213 = { 7'd0, dna_sr } ; always@(wrkAct or wci_0_respF_D_OUT or wci_1_respF_D_OUT or @@ -17849,193 +17627,162 @@ module mkOCCP(pciDevice, wci_12_respF_D_OUT or wci_13_respF_D_OUT or wci_14_respF_D_OUT) begin case (wrkAct) - 4'd0: rtnData__h113157 = wci_0_respF_D_OUT[31:0]; - 4'd1: rtnData__h113157 = wci_1_respF_D_OUT[31:0]; - 4'd2: rtnData__h113157 = wci_2_respF_D_OUT[31:0]; - 4'd3: rtnData__h113157 = wci_3_respF_D_OUT[31:0]; - 4'd4: rtnData__h113157 = wci_4_respF_D_OUT[31:0]; - 4'd5: rtnData__h113157 = wci_5_respF_D_OUT[31:0]; - 4'd6: rtnData__h113157 = wci_6_respF_D_OUT[31:0]; - 4'd7: rtnData__h113157 = wci_7_respF_D_OUT[31:0]; - 4'd8: rtnData__h113157 = wci_8_respF_D_OUT[31:0]; - 4'd9: rtnData__h113157 = wci_9_respF_D_OUT[31:0]; - 4'd10: rtnData__h113157 = wci_10_respF_D_OUT[31:0]; - 4'd11: rtnData__h113157 = wci_11_respF_D_OUT[31:0]; - 4'd12: rtnData__h113157 = wci_12_respF_D_OUT[31:0]; - 4'd13: rtnData__h113157 = wci_13_respF_D_OUT[31:0]; - 4'd14: rtnData__h113157 = wci_14_respF_D_OUT[31:0]; - 4'd15: rtnData__h113157 = 32'hAAAAAAAA /* unspecified value */ ; + 4'd0: rtnData__h110501 = wci_0_respF_D_OUT[31:0]; + 4'd1: rtnData__h110501 = wci_1_respF_D_OUT[31:0]; + 4'd2: rtnData__h110501 = wci_2_respF_D_OUT[31:0]; + 4'd3: rtnData__h110501 = wci_3_respF_D_OUT[31:0]; + 4'd4: rtnData__h110501 = wci_4_respF_D_OUT[31:0]; + 4'd5: rtnData__h110501 = wci_5_respF_D_OUT[31:0]; + 4'd6: rtnData__h110501 = wci_6_respF_D_OUT[31:0]; + 4'd7: rtnData__h110501 = wci_7_respF_D_OUT[31:0]; + 4'd8: rtnData__h110501 = wci_8_respF_D_OUT[31:0]; + 4'd9: rtnData__h110501 = wci_9_respF_D_OUT[31:0]; + 4'd10: rtnData__h110501 = wci_10_respF_D_OUT[31:0]; + 4'd11: rtnData__h110501 = wci_11_respF_D_OUT[31:0]; + 4'd12: rtnData__h110501 = wci_12_respF_D_OUT[31:0]; + 4'd13: rtnData__h110501 = wci_13_respF_D_OUT[31:0]; + 4'd14: rtnData__h110501 = wci_14_respF_D_OUT[31:0]; + 4'd15: rtnData__h110501 = 32'hAAAAAAAA /* unspecified value */ ; endcase end - always@(x__h9243) - begin - case (x__h9243) - 6'd0: put__h9199 = 8'd79; - 6'd1: put__h9199 = 8'd112; - 6'd2, 6'd38: put__h9199 = 8'd101; - 6'd3: put__h9199 = 8'd110; - 6'd4: put__h9199 = 8'd67; - 6'd5: put__h9199 = 8'd80; - 6'd6: put__h9199 = 8'd73; - 6'd7, 6'd16, 6'd22, 6'd33: put__h9199 = 8'd32; - 6'd8, 6'd12: put__h9199 = 8'd85; - 6'd9: put__h9199 = 8'd83; - 6'd10: put__h9199 = 8'd66; - 6'd11, 6'd27, 6'd30: put__h9199 = 8'd45; - 6'd13: put__h9199 = 8'd65; - 6'd14: put__h9199 = 8'd82; - 6'd15: put__h9199 = 8'd84; - 6'd17: put__h9199 = 8'd118; - 6'd18, 6'd20, 6'd24, 6'd28: put__h9199 = 8'd48; - 6'd19: put__h9199 = 8'd46; - 6'd21, 6'd25, 6'd29: put__h9199 = 8'd49; - 6'd23, 6'd31: put__h9199 = 8'd50; - 6'd26, 6'd32: put__h9199 = 8'd52; - 6'd34, 6'd39: put__h9199 = 8'd42; - 6'd35: put__h9199 = 8'd115; - 6'd36: put__h9199 = 8'd97; - 6'd37: put__h9199 = 8'd102; - default: put__h9199 = 8'b10101010 /* unspecified value */ ; - endcase - end - always@(_theResult_____1__h78175 or + always@(_theResult_____1__h75724 or wci_0_busy or wci_0_reqF_cntr_r or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = !wci_0_busy && !wci_0_reqF_cntr_r; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3034 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = 1'd1; endcase end - always@(_theResult_____1__h78175 or + always@(_theResult_____1__h75724 or wci_0_busy or wci_0_wReset_n or wci_0_respF_FULL_N or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = !wci_0_busy && (wci_0_wReset_n || wci_0_respF_FULL_N); 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3052 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = 1'd1; endcase end - always@(_theResult_____1__h78175 or + always@(_theResult_____1__h75724 or wci_0_busy or wci_0_respF_FULL_N or wci_1_busy or @@ -18065,2404 +17812,2404 @@ module mkOCCP(pciDevice, wci_13_busy or wci_13_respF_FULL_N or wci_14_busy or wci_14_respF_FULL_N) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_0_busy && wci_0_respF_FULL_N; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_1_busy && wci_1_respF_FULL_N; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_2_busy && wci_2_respF_FULL_N; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_3_busy && wci_3_respF_FULL_N; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_4_busy && wci_4_respF_FULL_N; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_5_busy && wci_5_respF_FULL_N; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_6_busy && wci_6_respF_FULL_N; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_7_busy && wci_7_respF_FULL_N; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_8_busy && wci_8_respF_FULL_N; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_9_busy && wci_9_respF_FULL_N; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_10_busy && wci_10_respF_FULL_N; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_11_busy && wci_11_respF_FULL_N; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_12_busy && wci_12_respF_FULL_N; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_13_busy && wci_13_respF_FULL_N; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = !wci_14_busy && wci_14_respF_FULL_N; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3077 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_reqF_cntr_r or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = !wci_1_busy && !wci_1_reqF_cntr_r; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3140 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_wReset_n or wci_1_respF_FULL_N or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = !wci_1_busy && (wci_1_wReset_n || wci_1_respF_FULL_N); 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3151 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_reqF_cntr_r or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = !wci_2_busy && !wci_2_reqF_cntr_r; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3176 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_wReset_n or wci_2_respF_FULL_N or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = !wci_2_busy && (wci_2_wReset_n || wci_2_respF_FULL_N); 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3187 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_reqF_cntr_r or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = !wci_3_busy && !wci_3_reqF_cntr_r; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3212 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_wReset_n or wci_3_respF_FULL_N or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = !wci_3_busy && (wci_3_wReset_n || wci_3_respF_FULL_N); 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3223 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_reqF_cntr_r or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = !wci_4_busy && !wci_4_reqF_cntr_r; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3248 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_wReset_n or wci_4_respF_FULL_N or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = !wci_4_busy && (wci_4_wReset_n || wci_4_respF_FULL_N); 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3259 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_reqF_cntr_r or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = !wci_5_busy && !wci_5_reqF_cntr_r; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3284 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_wReset_n or wci_5_respF_FULL_N or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = !wci_5_busy && (wci_5_wReset_n || wci_5_respF_FULL_N); 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3295 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_reqF_cntr_r or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = !wci_6_busy && !wci_6_reqF_cntr_r; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3320 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_wReset_n or wci_6_respF_FULL_N or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = !wci_6_busy && (wci_6_wReset_n || wci_6_respF_FULL_N); 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3331 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or wci_7_busy or wci_7_reqF_cntr_r or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = !wci_7_busy && !wci_7_reqF_cntr_r; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3356 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - wci_7_busy or - wci_7_wReset_n or - wci_7_respF_FULL_N or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_wReset_n or + wci_8_respF_FULL_N or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - !wci_7_busy && (wci_7_wReset_n || wci_7_respF_FULL_N); + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + !wci_8_busy && (wci_8_wReset_n || wci_8_respF_FULL_N); 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3367 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - wci_8_busy or - wci_8_reqF_cntr_r or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_wReset_n or + wci_7_respF_FULL_N or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + !wci_7_busy && (wci_7_wReset_n || wci_7_respF_FULL_N); 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - !wci_8_busy && !wci_8_reqF_cntr_r; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3392 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or wci_8_busy or - wci_8_wReset_n or - wci_8_respF_FULL_N or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + wci_8_reqF_cntr_r or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - !wci_8_busy && (wci_8_wReset_n || wci_8_respF_FULL_N); + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + !wci_8_busy && !wci_8_reqF_cntr_r; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3403 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_reqF_cntr_r or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = !wci_9_busy && !wci_9_reqF_cntr_r; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3428 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_wReset_n or wci_9_respF_FULL_N or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = !wci_9_busy && (wci_9_wReset_n || wci_9_respF_FULL_N); 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3439 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_reqF_cntr_r or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = !wci_10_busy && !wci_10_reqF_cntr_r; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3464 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_wReset_n or wci_10_respF_FULL_N or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = !wci_10_busy && (wci_10_wReset_n || wci_10_respF_FULL_N); 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3475 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_reqF_cntr_r or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = !wci_11_busy && !wci_11_reqF_cntr_r; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3500 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_wReset_n or wci_11_respF_FULL_N or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = !wci_11_busy && (wci_11_wReset_n || wci_11_respF_FULL_N); 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3511 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_reqF_cntr_r or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = !wci_12_busy && !wci_12_reqF_cntr_r; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3536 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_wReset_n or wci_12_respF_FULL_N or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = !wci_12_busy && (wci_12_wReset_n || wci_12_respF_FULL_N); 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3547 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_reqF_cntr_r or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = !wci_13_busy && !wci_13_reqF_cntr_r; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3572 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_wReset_n or wci_13_respF_FULL_N or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = !wci_13_busy && (wci_13_wReset_n || wci_13_respF_FULL_N); 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3583 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_reqF_cntr_r) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = !wci_14_busy && !wci_14_reqF_cntr_r; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3608 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = 1'd1; endcase end - always@(_theResult_____1__h78175 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_wReset_n or wci_14_respF_FULL_N) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = !wci_14_busy && (wci_14_wReset_n || wci_14_respF_FULL_N); 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3619 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = 1'd1; endcase end - always@(_theResult_____1__h78175 or + always@(_theResult_____1__h75724 or wci_0_busy or cpReq or wci_0_wReset_n or wci_0_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3671 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580 or wci_1_busy or wci_1_wReset_n or wci_1_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3675 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584 or wci_2_busy or wci_2_wReset_n or wci_2_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3679 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588 or wci_3_busy or wci_3_wReset_n or wci_3_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3683 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592 or wci_4_busy or wci_4_wReset_n or wci_4_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3687 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596 or wci_5_busy or wci_5_wReset_n or wci_5_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3691 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600 or wci_6_busy or wci_6_wReset_n or wci_6_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3695 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604 or wci_7_busy or wci_7_wReset_n or wci_7_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3699 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608 or wci_8_busy or wci_8_wReset_n or wci_8_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3703 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612 or wci_9_busy or wci_9_wReset_n or wci_9_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3707 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616 or wci_10_busy or wci_10_wReset_n or wci_10_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3711 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620 or wci_11_busy or wci_11_wReset_n or wci_11_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3715 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624 or wci_12_busy or wci_12_wReset_n or wci_12_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3719 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628 or wci_13_busy or wci_13_wReset_n or wci_13_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3723 or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632 or wci_14_busy or wci_14_wReset_n or wci_14_respF_FULL_N or - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3727) + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636) begin - case (_theResult_____1__h78175) + case (_theResult_____1__h75724) 4'd0: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_0_busy && (cpReq[61:60] != 2'd2 || wci_0_wReset_n || wci_0_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3671; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580; 4'd1: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_1_busy && (cpReq[61:60] != 2'd2 || wci_1_wReset_n || wci_1_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3675; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584; 4'd2: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_2_busy && (cpReq[61:60] != 2'd2 || wci_2_wReset_n || wci_2_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3679; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588; 4'd3: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_3_busy && (cpReq[61:60] != 2'd2 || wci_3_wReset_n || wci_3_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3683; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592; 4'd4: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_4_busy && (cpReq[61:60] != 2'd2 || wci_4_wReset_n || wci_4_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3687; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596; 4'd5: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_5_busy && (cpReq[61:60] != 2'd2 || wci_5_wReset_n || wci_5_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3691; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600; 4'd6: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_6_busy && (cpReq[61:60] != 2'd2 || wci_6_wReset_n || wci_6_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3695; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604; 4'd7: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_7_busy && (cpReq[61:60] != 2'd2 || wci_7_wReset_n || wci_7_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3699; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608; 4'd8: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_8_busy && (cpReq[61:60] != 2'd2 || wci_8_wReset_n || wci_8_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3703; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612; 4'd9: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_9_busy && (cpReq[61:60] != 2'd2 || wci_9_wReset_n || wci_9_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3707; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616; 4'd10: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_10_busy && (cpReq[61:60] != 2'd2 || wci_10_wReset_n || wci_10_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3711; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620; 4'd11: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_11_busy && (cpReq[61:60] != 2'd2 || wci_11_wReset_n || wci_11_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3715; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624; 4'd12: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_12_busy && (cpReq[61:60] != 2'd2 || wci_12_wReset_n || wci_12_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3719; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628; 4'd13: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_13_busy && (cpReq[61:60] != 2'd2 || wci_13_wReset_n || wci_13_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3723; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632; 4'd14: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = !wci_14_busy && (cpReq[61:60] != 2'd2 || wci_14_wReset_n || wci_14_respF_FULL_N) && - IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_THEN_N_ETC___d3727; + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636; 4'd15: - CASE_IF_cpReq_380_BITS_61_TO_60_939_EQ_2_940_T_ETC___d3730 = 1'd1; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or wci_0_reqF_cntr_r or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = !wci_0_busy && !wci_0_reqF_cntr_r; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3772 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or wci_0_wReset_n or wci_0_respF_FULL_N or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = !wci_0_busy && (wci_0_wReset_n || wci_0_respF_FULL_N); 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3785 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or wci_0_reqF_cntr_r or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = !wci_0_busy && !wci_0_reqF_cntr_r; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3826 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or wci_0_wReset_n or wci_0_respF_FULL_N or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = !wci_0_busy && (wci_0_wReset_n || wci_0_respF_FULL_N); 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3841 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or wci_0_respF_FULL_N or wci_1_busy or @@ -20492,4011 +20239,4011 @@ module mkOCCP(pciDevice, wci_13_busy or wci_13_respF_FULL_N or wci_14_busy or wci_14_respF_FULL_N) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_0_busy && wci_0_respF_FULL_N; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_1_busy && wci_1_respF_FULL_N; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_2_busy && wci_2_respF_FULL_N; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_3_busy && wci_3_respF_FULL_N; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_4_busy && wci_4_respF_FULL_N; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_5_busy && wci_5_respF_FULL_N; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_6_busy && wci_6_respF_FULL_N; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_7_busy && wci_7_respF_FULL_N; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_8_busy && wci_8_respF_FULL_N; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_9_busy && wci_9_respF_FULL_N; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_10_busy && wci_10_respF_FULL_N; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_11_busy && wci_11_respF_FULL_N; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_12_busy && wci_12_respF_FULL_N; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_13_busy && wci_13_respF_FULL_N; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = !wci_14_busy && wci_14_respF_FULL_N; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3884 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_reqF_cntr_r or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = !wci_1_busy && !wci_1_reqF_cntr_r; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3942 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_wReset_n or wci_1_respF_FULL_N or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = !wci_1_busy && (wci_1_wReset_n || wci_1_respF_FULL_N); 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3954 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_reqF_cntr_r or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = !wci_1_busy && !wci_1_reqF_cntr_r; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3967 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or wci_1_busy or wci_1_wReset_n or wci_1_respF_FULL_N or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = !wci_1_busy && (wci_1_wReset_n || wci_1_respF_FULL_N); 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d3977 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_reqF_cntr_r or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = !wci_2_busy && !wci_2_reqF_cntr_r; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4019 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_wReset_n or wci_2_respF_FULL_N or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = !wci_2_busy && (wci_2_wReset_n || wci_2_respF_FULL_N); 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4031 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_reqF_cntr_r or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = !wci_2_busy && !wci_2_reqF_cntr_r; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4042 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or wci_2_busy or wci_2_wReset_n or wci_2_respF_FULL_N or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = !wci_2_busy && (wci_2_wReset_n || wci_2_respF_FULL_N); 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4052 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_reqF_cntr_r or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = !wci_3_busy && !wci_3_reqF_cntr_r; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4094 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_wReset_n or wci_3_respF_FULL_N or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = !wci_3_busy && (wci_3_wReset_n || wci_3_respF_FULL_N); 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4106 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_reqF_cntr_r or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = !wci_3_busy && !wci_3_reqF_cntr_r; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4117 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or wci_3_busy or wci_3_wReset_n or wci_3_respF_FULL_N or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = !wci_3_busy && (wci_3_wReset_n || wci_3_respF_FULL_N); 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4127 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_reqF_cntr_r or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = !wci_4_busy && !wci_4_reqF_cntr_r; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4169 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_wReset_n or wci_4_respF_FULL_N or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = !wci_4_busy && (wci_4_wReset_n || wci_4_respF_FULL_N); 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4181 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_reqF_cntr_r or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = !wci_4_busy && !wci_4_reqF_cntr_r; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4192 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or wci_4_busy or wci_4_wReset_n or wci_4_respF_FULL_N or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = !wci_4_busy && (wci_4_wReset_n || wci_4_respF_FULL_N); 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4202 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_reqF_cntr_r or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = !wci_5_busy && !wci_5_reqF_cntr_r; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4244 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_wReset_n or wci_5_respF_FULL_N or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = !wci_5_busy && (wci_5_wReset_n || wci_5_respF_FULL_N); 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4256 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_reqF_cntr_r or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = !wci_5_busy && !wci_5_reqF_cntr_r; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4267 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or wci_5_busy or wci_5_wReset_n or wci_5_respF_FULL_N or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = !wci_5_busy && (wci_5_wReset_n || wci_5_respF_FULL_N); 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4277 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_reqF_cntr_r or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = !wci_6_busy && !wci_6_reqF_cntr_r; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4319 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_wReset_n or wci_6_respF_FULL_N or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = !wci_6_busy && (wci_6_wReset_n || wci_6_respF_FULL_N); 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4331 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_reqF_cntr_r or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = !wci_6_busy && !wci_6_reqF_cntr_r; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4342 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or wci_6_busy or wci_6_wReset_n or wci_6_respF_FULL_N or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = !wci_6_busy && (wci_6_wReset_n || wci_6_respF_FULL_N); 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4352 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or wci_7_busy or wci_7_reqF_cntr_r or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = !wci_7_busy && !wci_7_reqF_cntr_r; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4394 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or wci_7_busy or wci_7_wReset_n or wci_7_respF_FULL_N or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = !wci_7_busy && (wci_7_wReset_n || wci_7_respF_FULL_N); 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4406 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or wci_7_busy or wci_7_reqF_cntr_r or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = !wci_7_busy && !wci_7_reqF_cntr_r; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4417 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or wci_7_busy or wci_7_wReset_n or wci_7_respF_FULL_N or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = !wci_7_busy && (wci_7_wReset_n || wci_7_respF_FULL_N); 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4427 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or wci_8_busy or wci_8_reqF_cntr_r or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = !wci_8_busy && !wci_8_reqF_cntr_r; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4469 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or wci_8_busy or wci_8_wReset_n or wci_8_respF_FULL_N or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = !wci_8_busy && (wci_8_wReset_n || wci_8_respF_FULL_N); 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4481 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or wci_8_busy or wci_8_reqF_cntr_r or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = !wci_8_busy && !wci_8_reqF_cntr_r; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4492 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or wci_8_busy or wci_8_wReset_n or wci_8_respF_FULL_N or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = !wci_8_busy && (wci_8_wReset_n || wci_8_respF_FULL_N); 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4502 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_reqF_cntr_r or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = !wci_9_busy && !wci_9_reqF_cntr_r; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4544 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_wReset_n or wci_9_respF_FULL_N or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = !wci_9_busy && (wci_9_wReset_n || wci_9_respF_FULL_N); 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4556 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_reqF_cntr_r or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = !wci_9_busy && !wci_9_reqF_cntr_r; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4567 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or wci_9_busy or wci_9_wReset_n or wci_9_respF_FULL_N or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = !wci_9_busy && (wci_9_wReset_n || wci_9_respF_FULL_N); 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4577 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_reqF_cntr_r or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = !wci_10_busy && !wci_10_reqF_cntr_r; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4619 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_wReset_n or wci_10_respF_FULL_N or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = !wci_10_busy && (wci_10_wReset_n || wci_10_respF_FULL_N); 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4631 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_reqF_cntr_r or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = !wci_10_busy && !wci_10_reqF_cntr_r; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4642 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or wci_10_busy or wci_10_wReset_n or wci_10_respF_FULL_N or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = !wci_10_busy && (wci_10_wReset_n || wci_10_respF_FULL_N); 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4652 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_reqF_cntr_r or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = !wci_11_busy && !wci_11_reqF_cntr_r; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4694 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_wReset_n or wci_11_respF_FULL_N or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = !wci_11_busy && (wci_11_wReset_n || wci_11_respF_FULL_N); 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4706 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_reqF_cntr_r or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = !wci_11_busy && !wci_11_reqF_cntr_r; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4717 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or wci_11_busy or wci_11_wReset_n or wci_11_respF_FULL_N or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = !wci_11_busy && (wci_11_wReset_n || wci_11_respF_FULL_N); 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4727 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_reqF_cntr_r or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = !wci_12_busy && !wci_12_reqF_cntr_r; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4769 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_wReset_n or wci_12_respF_FULL_N or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = !wci_12_busy && (wci_12_wReset_n || wci_12_respF_FULL_N); 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4781 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_reqF_cntr_r or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = !wci_12_busy && !wci_12_reqF_cntr_r; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4792 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or wci_12_busy or wci_12_wReset_n or wci_12_respF_FULL_N or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = !wci_12_busy && (wci_12_wReset_n || wci_12_respF_FULL_N); 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4802 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_reqF_cntr_r or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = !wci_13_busy && !wci_13_reqF_cntr_r; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4844 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_wReset_n or wci_13_respF_FULL_N or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = !wci_13_busy && (wci_13_wReset_n || wci_13_respF_FULL_N); 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4856 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_reqF_cntr_r or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = !wci_13_busy && !wci_13_reqF_cntr_r; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4867 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or wci_13_busy or wci_13_wReset_n or wci_13_respF_FULL_N or - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033) + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = !wci_13_busy && (wci_13_wReset_n || wci_13_respF_FULL_N); 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = - NOT_wci_14_busy_213_028_AND_0_OR_wci_14_wReset_ETC___d3033; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4877 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_reqF_cntr_r) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = !wci_14_busy && !wci_14_reqF_cntr_r; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4919 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_wReset_n or wci_14_respF_FULL_N) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = !wci_14_busy && (wci_14_wReset_n || wci_14_respF_FULL_N); 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4931 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_reqF_cntr_r) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = !wci_14_busy && !wci_14_reqF_cntr_r; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4942 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = 1'd1; endcase end - always@(_theResult_____1__h78190 or - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137 or - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955 or - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961 or - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967 or - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973 or - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979 or - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985 or - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991 or - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997 or - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003 or - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009 or - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015 or - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021 or - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027 or + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or wci_14_busy or wci_14_wReset_n or wci_14_respF_FULL_N) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_0_busy_53_947_AND_0_OR_wci_0_wReset_n__ETC___d3137; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_1_busy_93_950_AND_0_OR_wci_1_wReset_n__ETC___d2955; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_2_busy_33_956_AND_0_OR_wci_2_wReset_n__ETC___d2961; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_3_busy_73_962_AND_0_OR_wci_3_wReset_n__ETC___d2967; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_4_busy_13_968_AND_0_OR_wci_4_wReset_n__ETC___d2973; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_5_busy_53_974_AND_0_OR_wci_5_wReset_n__ETC___d2979; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_6_busy_093_980_AND_0_OR_wci_6_wReset_n_ETC___d2985; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_7_busy_233_986_AND_0_OR_wci_7_wReset_n_ETC___d2991; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_8_busy_373_992_AND_0_OR_wci_8_wReset_n_ETC___d2997; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_9_busy_513_998_AND_0_OR_wci_9_wReset_n_ETC___d3003; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_10_busy_653_004_AND_0_OR_wci_10_wReset_ETC___d3009; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_11_busy_793_010_AND_0_OR_wci_11_wReset_ETC___d3015; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_12_busy_933_016_AND_0_OR_wci_12_wReset_ETC___d3021; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = - NOT_wci_13_busy_073_022_AND_0_OR_wci_13_wReset_ETC___d3027; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = !wci_14_busy && (wci_14_wReset_n || wci_14_respF_FULL_N); 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d4952 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = 1'd1; endcase end - always@(_theResult_____1__h78190 or + always@(_theResult_____1__h75739 or wci_0_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5023 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5025 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934 or wci_1_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5029 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5031 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940 or wci_2_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5035 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5037 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946 or wci_3_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5041 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5043 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952 or wci_4_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5047 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5049 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958 or wci_5_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5053 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5055 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964 or wci_6_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5059 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5061 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970 or wci_7_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5065 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5067 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976 or wci_8_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5071 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5073 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982 or wci_9_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5077 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5079 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988 or wci_10_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5083 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5085 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994 or wci_11_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5089 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5091 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000 or wci_12_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5095 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5097 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006 or wci_13_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5101 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5103 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012 or wci_14_busy or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5107 or - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5109) + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018) begin - case (_theResult_____1__h78190) + case (_theResult_____1__h75739) 4'd0: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_0_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5023 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5025; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934; 4'd1: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_1_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5029 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5031; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940; 4'd2: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_2_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5035 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5037; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946; 4'd3: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_3_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5041 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5043; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952; 4'd4: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_4_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5047 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5049; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958; 4'd5: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_5_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5053 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5055; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964; 4'd6: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_6_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5059 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5061; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970; 4'd7: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_7_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5065 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5067; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976; 4'd8: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_8_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5071 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5073; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982; 4'd9: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_9_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5077 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5079; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988; 4'd10: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_10_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5083 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5085; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994; 4'd11: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_11_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5089 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5091; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000; 4'd12: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_12_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5095 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5097; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006; 4'd13: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_13_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5101 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5103; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012; 4'd14: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = !wci_14_busy && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_w_ETC___d5107 && - IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_THEN_N_ETC___d5109; + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018; 4'd15: - CASE_IF_cpReq_380_BITS_37_TO_36_740_EQ_2_741_T_ETC___d5112 = 1'd1; + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = 1'd1; endcase end always@(wrkAct or @@ -24517,95 +24264,95 @@ module mkOCCP(pciDevice, begin case (wrkAct) 4'd0: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_0_respF_EMPTY_N; 4'd1: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_1_respF_EMPTY_N; 4'd2: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_2_respF_EMPTY_N; 4'd3: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_3_respF_EMPTY_N; 4'd4: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_4_respF_EMPTY_N; 4'd5: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_5_respF_EMPTY_N; 4'd6: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_6_respF_EMPTY_N; 4'd7: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_7_respF_EMPTY_N; 4'd8: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_8_respF_EMPTY_N; 4'd9: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_9_respF_EMPTY_N; 4'd10: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_10_respF_EMPTY_N; 4'd11: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_11_respF_EMPTY_N; 4'd12: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_12_respF_EMPTY_N; 4'd13: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_13_respF_EMPTY_N; 4'd14: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = wci_14_respF_EMPTY_N; 4'd15: - CASE_wrkAct_119_0_wci_0_respF_i_notEmpty__120__ETC___d5135 = 1'd1; + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = 1'd1; endcase end always@(cpReq or - x__h106938 or + x__h104311 or pciDevice or - x__h107487 or - cpStatus__h77314 or scratch20 or scratch24 or cpControl) + x__h104860 or + cpStatus__h74863 or scratch20 or scratch24 or cpControl) begin case (cpReq[11:4]) 8'h0: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = 32'h4F70656E; 8'h04: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = 32'h43504900; 8'h08: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = 32'h00000001; 8'h0C: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = - 32'd1390838362; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'd1391113942; 8'h10: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = - { 17'd0, x__h106938 }; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + { 17'd0, x__h104311 }; 8'h14: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = { 16'd0, pciDevice }; 8'h18: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = - { 17'd0, x__h107487 }; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + { 17'd0, x__h104860 }; 8'h1C: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = - cpStatus__h77314; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + cpStatus__h74863; 8'h20: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = scratch20; 8'h24: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = scratch24; 8'h28: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = cpControl; - default: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x0_474_THEN__ETC___d2619 = + default: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = 32'd0; endcase end @@ -24620,14 +24367,11 @@ module mkOCCP(pciDevice, timeServ_rplTimeControl or timeServ_nowInCC_dD_OUT or deltaTime or - timeServ_refPerPPS_dD_OUT or - readCntReg or - devDNAV_wget or - bluart_txLevel or bluart_rxLevel or bluart_rxChar_get) + timeServ_refPerPPS_dD_OUT or readCntReg or devDNAV_wget) begin case (cpReq[11:4]) 8'h30: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = { timeServ_ppsLostSticky, timeServ_gpsInSticky, timeServ_ppsInSticky, @@ -24637,47 +24381,38 @@ module mkOCCP(pciDevice, 18'h0, timeServ_rollingPPSIn_dD_OUT }; 8'h34: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = { 27'd0, timeServ_rplTimeControl }; 8'h38: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = timeServ_nowInCC_dD_OUT[63:32]; 8'h3C: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = timeServ_nowInCC_dD_OUT[31:0]; 8'h40: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = deltaTime[63:32]; 8'h44: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = deltaTime[31:0]; 8'h48: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = { 4'd0, timeServ_refPerPPS_dD_OUT }; 8'h4C: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = readCntReg; 8'h50: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = devDNAV_wget[31:0]; 8'h54: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = devDNAV_wget[63:32]; - 8'h60: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = - { 24'd0, bluart_txLevel }; - 8'h64: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = - { 24'd0, bluart_rxLevel }; - 8'h68: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = - { 24'd0, bluart_rxChar_get }; 8'h7C: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = 32'd2; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = 32'd2; 8'h80: - IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = 32'd268435464; - default: IF_cpReq_380_BITS_11_TO_4_383_EQ_0x30_624_THEN_ETC___d2744 = + default: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = 32'd268566536; endcase end @@ -24760,8 +24495,6 @@ module mkOCCP(pciDevice, timeServ_ppsLostSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; timeServ_rplTimeControl <= `BSV_ASSIGNMENT_DELAY 5'd0; timeServ_timeSetSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; - uartInited <= `BSV_ASSIGNMENT_DELAY 1'd0; - uartTxtP <= `BSV_ASSIGNMENT_DELAY 6'd0; warmResetP <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_0_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_0_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; @@ -25133,9 +24866,6 @@ module mkOCCP(pciDevice, if (timeServ_timeSetSticky_EN) timeServ_timeSetSticky <= `BSV_ASSIGNMENT_DELAY timeServ_timeSetSticky_D_IN; - if (uartInited_EN) - uartInited <= `BSV_ASSIGNMENT_DELAY uartInited_D_IN; - if (uartTxtP_EN) uartTxtP <= `BSV_ASSIGNMENT_DELAY uartTxtP_D_IN; if (warmResetP_EN) warmResetP <= `BSV_ASSIGNMENT_DELAY warmResetP_D_IN; if (wci_0_busy_EN) @@ -26028,8 +25758,6 @@ module mkOCCP(pciDevice, timeServ_rplTimeControl = 5'h0A; timeServ_timeSetSticky = 1'h0; timeServ_xo2 = 1'h0; - uartInited = 1'h0; - uartTxtP = 6'h2A; warmResetP = 1'h0; wci_0_busy = 1'h0; wci_0_lastConfigAddr = 33'h0AAAAAAAA; @@ -26390,14 +26118,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26405,23 +26133,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) begin - v__h80654 = $time; + v__h78104 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80654); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78104); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26429,25 +26157,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) begin - v__h81242 = $time; + v__h78692 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h81242, + v__h78692, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26455,14 +26183,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26470,14 +26198,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26485,23 +26213,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) begin - v__h81350 = $time; + v__h78800 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81350); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78800); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26509,25 +26237,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) begin - v__h81929 = $time; + v__h79379 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h81929, + v__h79379, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26535,14 +26263,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26550,14 +26278,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26565,23 +26293,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) begin - v__h82037 = $time; + v__h79487 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82037); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79487); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26589,25 +26317,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) begin - v__h82616 = $time; + v__h80066 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h82616, + v__h80066, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26615,14 +26343,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26630,14 +26358,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26645,23 +26373,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) begin - v__h82724 = $time; + v__h80174 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82724); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80174); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26669,25 +26397,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) begin - v__h83303 = $time; + v__h80753 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h83303, + v__h80753, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26695,14 +26423,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26710,14 +26438,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26725,23 +26453,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) begin - v__h83411 = $time; + v__h80861 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83411); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80861); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26749,25 +26477,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) begin - v__h83990 = $time; + v__h81440 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h83990, + v__h81440, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26775,14 +26503,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26790,14 +26518,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26805,23 +26533,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) begin - v__h84098 = $time; + v__h81548 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84098); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81548); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26829,25 +26557,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) begin - v__h84677 = $time; + v__h82127 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h84677, + v__h82127, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26855,14 +26583,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26870,14 +26598,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26885,23 +26613,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) begin - v__h84785 = $time; + v__h82235 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84785); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82235); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26909,25 +26637,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) begin - v__h85364 = $time; + v__h82814 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h85364, + v__h82814, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26935,14 +26663,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26950,14 +26678,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26965,23 +26693,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) begin - v__h85472 = $time; + v__h82922 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85472); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82922); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -26989,25 +26717,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) begin - v__h86051 = $time; + v__h83501 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h86051, + v__h83501, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27015,14 +26743,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27030,14 +26758,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27045,23 +26773,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) begin - v__h86159 = $time; + v__h83609 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86159); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27069,25 +26797,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) begin - v__h86738 = $time; + v__h84188 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h86738, + v__h84188, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27095,14 +26823,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27110,14 +26838,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27125,23 +26853,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) begin - v__h86846 = $time; + v__h84296 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86846); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84296); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27149,25 +26877,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) begin - v__h87425 = $time; + v__h84875 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h87425, + v__h84875, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27175,14 +26903,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27190,14 +26918,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27205,23 +26933,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) begin - v__h87533 = $time; + v__h84983 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87533); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84983); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27229,25 +26957,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) begin - v__h88112 = $time; + v__h85562 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h88112, + v__h85562, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27255,14 +26983,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27270,14 +26998,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27285,23 +27013,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) begin - v__h88220 = $time; + v__h85670 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h88220); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85670); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27309,25 +27037,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) begin - v__h88799 = $time; + v__h86249 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h88799, + v__h86249, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27335,14 +27063,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27350,14 +27078,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27365,23 +27093,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) begin - v__h88907 = $time; + v__h86357 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h88907); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86357); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27389,25 +27117,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) begin - v__h89486 = $time; + v__h86936 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h89486, + v__h86936, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27415,14 +27143,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27430,14 +27158,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27445,23 +27173,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) begin - v__h89594 = $time; + v__h87044 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h89594); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87044); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27469,25 +27197,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) begin - v__h90173 = $time; + v__h87623 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h90173, + v__h87623, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27495,14 +27223,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27510,14 +27238,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27525,23 +27253,23 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) begin - v__h90281 = $time; + v__h87731 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h90281); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87731); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27549,25 +27277,25 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) begin - v__h90860 = $time; + v__h88310 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h90860, + v__h88310, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27575,14 +27303,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27590,14 +27318,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_OOB) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_OOB) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -27605,1619 +27333,1619 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) begin - v__h97758 = $time; + v__h95208 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97758); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95208); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) begin - v__h97829 = $time; + v__h95279 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97829); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95279); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) begin - v__h97900 = $time; + v__h95350 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97900); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95350); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) begin - v__h97971 = $time; + v__h95421 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97971); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95421); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) begin - v__h98042 = $time; + v__h95492 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98042); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95492); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) begin - v__h98113 = $time; + v__h95563 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98113); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95563); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) begin - v__h98184 = $time; + v__h95634 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98184); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95634); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) begin - v__h98255 = $time; + v__h95705 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98255); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95705); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) begin - v__h98326 = $time; + v__h95776 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98326); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95776); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) begin - v__h98397 = $time; + v__h95847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98397); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95847); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) begin - v__h98468 = $time; + v__h95918 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98468); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) begin - v__h98539 = $time; + v__h95989 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98539); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95989); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) begin - v__h98610 = $time; + v__h96060 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98610); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96060); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) begin - v__h98681 = $time; + v__h96131 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98681); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96131); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) begin - v__h98752 = $time; + v__h96202 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98752); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96202); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); @@ -29227,14 +28955,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29242,14 +28970,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29257,14 +28985,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29272,14 +29000,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29287,14 +29015,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29302,51 +29030,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) begin - v__h97758 = $time; + v__h95208 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97758); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95208); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29354,14 +29082,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29369,14 +29097,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29384,14 +29112,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29399,14 +29127,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29414,51 +29142,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) begin - v__h97829 = $time; + v__h95279 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97829); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95279); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29466,14 +29194,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29481,14 +29209,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29496,14 +29224,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29511,14 +29239,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29526,51 +29254,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) begin - v__h97900 = $time; + v__h95350 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97900); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95350); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29578,14 +29306,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29593,14 +29321,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29608,14 +29336,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29623,14 +29351,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29638,51 +29366,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) begin - v__h97971 = $time; + v__h95421 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97971); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95421); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29690,14 +29418,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29705,14 +29433,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29720,14 +29448,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29735,14 +29463,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29750,51 +29478,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) begin - v__h98042 = $time; + v__h95492 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98042); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95492); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29802,14 +29530,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29817,14 +29545,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29832,14 +29560,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29847,14 +29575,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29862,51 +29590,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) begin - v__h98113 = $time; + v__h95563 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98113); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95563); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29914,14 +29642,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29929,14 +29657,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29944,14 +29672,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29959,14 +29687,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -29974,51 +29702,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) begin - v__h98184 = $time; + v__h95634 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98184); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95634); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30026,14 +29754,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30041,14 +29769,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30056,14 +29784,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30071,14 +29799,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30086,51 +29814,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) begin - v__h98255 = $time; + v__h95705 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98255); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95705); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30138,14 +29866,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30153,14 +29881,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30168,14 +29896,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30183,14 +29911,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30198,51 +29926,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) begin - v__h98326 = $time; + v__h95776 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98326); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95776); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30250,14 +29978,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30265,14 +29993,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30280,14 +30008,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30295,14 +30023,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30310,51 +30038,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) begin - v__h98397 = $time; + v__h95847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98397); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95847); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30362,14 +30090,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30377,14 +30105,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30392,14 +30120,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30407,14 +30135,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30422,51 +30150,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) begin - v__h98468 = $time; + v__h95918 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98468); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95918); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30474,14 +30202,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30489,14 +30217,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30504,14 +30232,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30519,14 +30247,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30534,51 +30262,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) begin - v__h98539 = $time; + v__h95989 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98539); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95989); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30586,14 +30314,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30601,14 +30329,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30616,14 +30344,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30631,14 +30359,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30646,51 +30374,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) begin - v__h98610 = $time; + v__h96060 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98610); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96060); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30698,14 +30426,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30713,14 +30441,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30728,14 +30456,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30743,14 +30471,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30758,51 +30486,51 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) begin - v__h98681 = $time; + v__h96131 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98681); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96131); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30810,14 +30538,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30825,14 +30553,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30840,14 +30568,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30855,14 +30583,14 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T) begin - v__h106736 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h106736, - _theResult_____1__h78175, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], @@ -30870,1885 +30598,1885 @@ module mkOCCP(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) begin - v__h98752 = $time; + v__h96202 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h98752); + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96202); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) begin - v__h106789 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h106789, - _theResult_____1__h78190, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd1) begin - v__h14436 = $time; + v__h11985 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h14436); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h11985); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd2) begin - v__h14526 = $time; + v__h12075 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h14526); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h12075); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd3) begin - v__h14615 = $time; + v__h12164 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd0 && - !wci_0_respTimr_45_ULT_1_SL_wci_0_wTimeout_46_47___d248 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && wci_0_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h14615); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h12164); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd1) begin - v__h14839 = $time; + v__h12388 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h14839); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h12388); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd2) begin - v__h14929 = $time; + v__h12478 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h14929); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h12478); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd3) begin - v__h15018 = $time; + v__h12567 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd2 && wci_0_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h15018); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h12567); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd1) begin - v__h15247 = $time; + v__h12796 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h15247); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h12796); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd2) begin - v__h15337 = $time; + v__h12886 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h15337); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h12886); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd3) begin - v__h15426 = $time; + v__h12975 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_0_wrkBusy && wci_0_wciResponse_wget[33:32] == 2'd3 && wci_0_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h15426); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h12975); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd1) begin - v__h18805 = $time; + v__h16354 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h18805); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h16354); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd2) begin - v__h18895 = $time; + v__h16444 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h18895); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h16444); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd3) begin - v__h18984 = $time; + v__h16533 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd0 && - !wci_1_respTimr_85_ULT_1_SL_wci_1_wTimeout_86_87___d388 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && wci_1_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h18984); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h16533); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd1) begin - v__h19208 = $time; + v__h16757 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h19208); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h16757); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd2) begin - v__h19298 = $time; + v__h16847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h19298); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h16847); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd3) begin - v__h19387 = $time; + v__h16936 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd2 && wci_1_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h19387); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h16936); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd1) begin - v__h19616 = $time; + v__h17165 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h19616); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h17165); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd2) begin - v__h19706 = $time; + v__h17255 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h19706); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h17255); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd3) begin - v__h19795 = $time; + v__h17344 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_1_wrkBusy && wci_1_wciResponse_wget[33:32] == 2'd3 && wci_1_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h19795); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h17344); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd1) begin - v__h23174 = $time; + v__h20723 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h23174); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h20723); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd2) begin - v__h23264 = $time; + v__h20813 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h23264); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h20813); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd3) begin - v__h23353 = $time; + v__h20902 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd0 && - !wci_2_respTimr_25_ULT_1_SL_wci_2_wTimeout_26_27___d528 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && wci_2_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h23353); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h20902); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd1) begin - v__h23577 = $time; + v__h21126 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h23577); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h21126); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd2) begin - v__h23667 = $time; + v__h21216 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h23667); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h21216); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd3) begin - v__h23756 = $time; + v__h21305 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd2 && wci_2_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h23756); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h21305); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd1) begin - v__h23985 = $time; + v__h21534 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h23985); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h21534); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd2) begin - v__h24075 = $time; + v__h21624 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h24075); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h21624); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd3) begin - v__h24164 = $time; + v__h21713 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_2_wrkBusy && wci_2_wciResponse_wget[33:32] == 2'd3 && wci_2_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h24164); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h21713); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd1) begin - v__h27543 = $time; + v__h25092 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h27543); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h25092); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd2) begin - v__h27633 = $time; + v__h25182 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h27633); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h25182); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd3) begin - v__h27722 = $time; + v__h25271 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd0 && - !wci_3_respTimr_65_ULT_1_SL_wci_3_wTimeout_66_67___d668 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && wci_3_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h27722); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h25271); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd1) begin - v__h27946 = $time; + v__h25495 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h27946); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h25495); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd2) begin - v__h28036 = $time; + v__h25585 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h28036); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h25585); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd3) begin - v__h28125 = $time; + v__h25674 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd2 && wci_3_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h28125); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h25674); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd1) begin - v__h28354 = $time; + v__h25903 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h28354); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h25903); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd2) begin - v__h28444 = $time; + v__h25993 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h28444); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h25993); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd3) begin - v__h28533 = $time; + v__h26082 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_3_wrkBusy && wci_3_wciResponse_wget[33:32] == 2'd3 && wci_3_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h28533); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h26082); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd1) begin - v__h31912 = $time; + v__h29461 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h31912); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h29461); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd2) begin - v__h32002 = $time; + v__h29551 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h32002); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h29551); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd3) begin - v__h32091 = $time; + v__h29640 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd0 && - !wci_4_respTimr_05_ULT_1_SL_wci_4_wTimeout_06_07___d808 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && wci_4_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h32091); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29640); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd1) begin - v__h32315 = $time; + v__h29864 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h32315); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h29864); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd2) begin - v__h32405 = $time; + v__h29954 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h32405); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h29954); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd3) begin - v__h32494 = $time; + v__h30043 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd2 && wci_4_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h32494); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h30043); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd1) begin - v__h32723 = $time; + v__h30272 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h32723); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h30272); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd2) begin - v__h32813 = $time; + v__h30362 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h32813); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h30362); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd3) begin - v__h32902 = $time; + v__h30451 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_4_wrkBusy && wci_4_wciResponse_wget[33:32] == 2'd3 && wci_4_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h32902); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h30451); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd1) begin - v__h36281 = $time; + v__h33830 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h36281); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h33830); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd2) begin - v__h36371 = $time; + v__h33920 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h36371); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h33920); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd3) begin - v__h36460 = $time; + v__h34009 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd0 && - !wci_5_respTimr_45_ULT_1_SL_wci_5_wTimeout_46_47___d948 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && wci_5_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h36460); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h34009); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd1) begin - v__h36684 = $time; + v__h34233 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h36684); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h34233); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd2) begin - v__h36774 = $time; + v__h34323 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h36774); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h34323); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd3) begin - v__h36863 = $time; + v__h34412 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd2 && wci_5_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h36863); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h34412); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd1) begin - v__h37092 = $time; + v__h34641 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h37092); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h34641); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd2) begin - v__h37182 = $time; + v__h34731 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h37182); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h34731); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd3) begin - v__h37271 = $time; + v__h34820 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_5_wrkBusy && wci_5_wciResponse_wget[33:32] == 2'd3 && wci_5_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h37271); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h34820); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd1) begin - v__h40650 = $time; + v__h38199 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h40650); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h38199); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd2) begin - v__h40740 = $time; + v__h38289 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h40740); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h38289); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd3) begin - v__h40829 = $time; + v__h38378 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd0 && - !wci_6_respTimr_085_ULT_1_SL_wci_6_wTimeout_086_ETC___d1088 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && wci_6_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h40829); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h38378); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd1) begin - v__h41053 = $time; + v__h38602 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h41053); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h38602); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd2) begin - v__h41143 = $time; + v__h38692 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h41143); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h38692); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd3) begin - v__h41232 = $time; + v__h38781 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd2 && wci_6_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h41232); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h38781); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd1) begin - v__h41461 = $time; + v__h39010 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h41461); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h39010); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd2) begin - v__h41551 = $time; + v__h39100 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h41551); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h39100); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd3) begin - v__h41640 = $time; + v__h39189 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_6_wrkBusy && wci_6_wciResponse_wget[33:32] == 2'd3 && wci_6_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h41640); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h39189); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd1) begin - v__h45019 = $time; + v__h42568 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h45019); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h42568); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd2) begin - v__h45109 = $time; + v__h42658 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h45109); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h42658); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd3) begin - v__h45198 = $time; + v__h42747 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd0 && - !wci_7_respTimr_225_ULT_1_SL_wci_7_wTimeout_226_ETC___d1228 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && wci_7_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h45198); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h42747); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd1) begin - v__h45422 = $time; + v__h42971 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h45422); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h42971); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd2) begin - v__h45512 = $time; + v__h43061 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h45512); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h43061); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd3) begin - v__h45601 = $time; + v__h43150 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd2 && wci_7_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h45601); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h43150); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd1) begin - v__h45830 = $time; + v__h43379 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h45830); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h43379); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd2) begin - v__h45920 = $time; + v__h43469 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h45920); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h43469); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd3) begin - v__h46009 = $time; + v__h43558 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_7_wrkBusy && wci_7_wciResponse_wget[33:32] == 2'd3 && wci_7_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h46009); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h43558); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd1) begin - v__h49388 = $time; + v__h46937 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h49388); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h46937); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd2) begin - v__h49478 = $time; + v__h47027 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h49478); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h47027); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd3) begin - v__h49567 = $time; + v__h47116 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd0 && - !wci_8_respTimr_365_ULT_1_SL_wci_8_wTimeout_366_ETC___d1368 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && wci_8_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h49567); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h47116); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd1) begin - v__h49791 = $time; + v__h47340 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h49791); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h47340); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd2) begin - v__h49881 = $time; + v__h47430 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h49881); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h47430); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd3) begin - v__h49970 = $time; + v__h47519 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd2 && wci_8_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h49970); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h47519); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd1) begin - v__h50199 = $time; + v__h47748 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h50199); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h47748); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd2) begin - v__h50289 = $time; + v__h47838 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h50289); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h47838); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd3) begin - v__h50378 = $time; + v__h47927 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_8_wrkBusy && wci_8_wciResponse_wget[33:32] == 2'd3 && wci_8_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h50378); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h47927); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd1) begin - v__h53757 = $time; + v__h51306 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h53757); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h51306); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd2) begin - v__h53847 = $time; + v__h51396 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h53847); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h51396); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd3) begin - v__h53936 = $time; + v__h51485 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd0 && - !wci_9_respTimr_505_ULT_1_SL_wci_9_wTimeout_506_ETC___d1508 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && wci_9_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h53936); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h51485); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd1) begin - v__h54160 = $time; + v__h51709 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h54160); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h51709); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd2) begin - v__h54250 = $time; + v__h51799 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h54250); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h51799); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd3) begin - v__h54339 = $time; + v__h51888 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd2 && wci_9_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h54339); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h51888); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd1) begin - v__h54568 = $time; + v__h52117 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h54568); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h52117); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd2) begin - v__h54658 = $time; + v__h52207 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h54658); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h52207); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd3) begin - v__h54747 = $time; + v__h52296 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_9_wrkBusy && wci_9_wciResponse_wget[33:32] == 2'd3 && wci_9_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h54747); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h52296); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd1) begin - v__h58126 = $time; + v__h55675 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h58126); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h55675); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd2) begin - v__h58216 = $time; + v__h55765 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h58216); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h55765); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd3) begin - v__h58305 = $time; + v__h55854 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd0 && - !wci_10_respTimr_645_ULT_1_SL_wci_10_wTimeout_6_ETC___d1648 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && wci_10_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h58305); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h55854); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd1) begin - v__h58529 = $time; + v__h56078 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h58529); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h56078); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd2) begin - v__h58619 = $time; + v__h56168 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h58619); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h56168); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd3) begin - v__h58708 = $time; + v__h56257 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd2 && wci_10_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h58708); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h56257); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd1) begin - v__h58937 = $time; + v__h56486 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h58937); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h56486); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd2) begin - v__h59027 = $time; + v__h56576 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h59027); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h56576); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd3) begin - v__h59116 = $time; + v__h56665 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_10_wrkBusy && wci_10_wciResponse_wget[33:32] == 2'd3 && wci_10_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h59116); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h56665); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd1) begin - v__h62495 = $time; + v__h60044 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h62495); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h60044); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd2) begin - v__h62585 = $time; + v__h60134 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h62585); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h60134); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd3) begin - v__h62674 = $time; + v__h60223 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd0 && - !wci_11_respTimr_785_ULT_1_SL_wci_11_wTimeout_7_ETC___d1788 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && wci_11_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h62674); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h60223); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd1) begin - v__h62898 = $time; + v__h60447 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h62898); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h60447); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd2) begin - v__h62988 = $time; + v__h60537 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h62988); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h60537); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd3) begin - v__h63077 = $time; + v__h60626 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd2 && wci_11_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h63077); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h60626); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd1) begin - v__h63306 = $time; + v__h60855 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h63306); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h60855); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd2) begin - v__h63396 = $time; + v__h60945 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h63396); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h60945); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd3) begin - v__h63485 = $time; + v__h61034 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_11_wrkBusy && wci_11_wciResponse_wget[33:32] == 2'd3 && wci_11_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h63485); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h61034); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd1) begin - v__h66864 = $time; + v__h64413 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h66864); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h64413); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd2) begin - v__h66954 = $time; + v__h64503 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h66954); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h64503); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd3) begin - v__h67043 = $time; + v__h64592 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd0 && - !wci_12_respTimr_925_ULT_1_SL_wci_12_wTimeout_9_ETC___d1928 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && wci_12_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h67043); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h64592); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd1) begin - v__h67267 = $time; + v__h64816 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h67267); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h64816); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd2) begin - v__h67357 = $time; + v__h64906 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h67357); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h64906); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd3) begin - v__h67446 = $time; + v__h64995 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd2 && wci_12_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h67446); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h64995); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd1) begin - v__h67675 = $time; + v__h65224 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h67675); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h65224); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd2) begin - v__h67765 = $time; + v__h65314 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h67765); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h65314); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd3) begin - v__h67854 = $time; + v__h65403 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_12_wrkBusy && wci_12_wciResponse_wget[33:32] == 2'd3 && wci_12_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h67854); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h65403); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd1) begin - v__h71233 = $time; + v__h68782 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h71233); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h68782); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd2) begin - v__h71323 = $time; + v__h68872 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h71323); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h68872); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd3) begin - v__h71412 = $time; + v__h68961 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd0 && - !wci_13_respTimr_065_ULT_1_SL_wci_13_wTimeout_0_ETC___d2068 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && wci_13_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h71412); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h68961); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd1) begin - v__h71636 = $time; + v__h69185 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h71636); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h69185); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd2) begin - v__h71726 = $time; + v__h69275 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h71726); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h69275); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd3) begin - v__h71815 = $time; + v__h69364 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd2 && wci_13_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h71815); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h69364); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd1) begin - v__h72044 = $time; + v__h69593 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h72044); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h69593); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd2) begin - v__h72134 = $time; + v__h69683 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h72134); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h69683); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd3) begin - v__h72223 = $time; + v__h69772 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_13_wrkBusy && wci_13_wciResponse_wget[33:32] == 2'd3 && wci_13_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h72223); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h69772); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd1) begin - v__h75602 = $time; + v__h73151 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h75602); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h73151); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd2) begin - v__h75692 = $time; + v__h73241 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h75692); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h73241); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd3) begin - v__h75781 = $time; + v__h73330 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd0 && - !wci_14_respTimr_205_ULT_1_SL_wci_14_wTimeout_2_ETC___d2208 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && wci_14_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h75781); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h73330); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd1) begin - v__h76005 = $time; + v__h73554 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h76005); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h73554); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd2) begin - v__h76095 = $time; + v__h73644 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h76095); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h73644); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd3) begin - v__h76184 = $time; + v__h73733 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd2 && wci_14_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h76184); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h73733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd1) begin - v__h76413 = $time; + v__h73962 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h76413); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h73962); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd2) begin - v__h76503 = $time; + v__h74052 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h76503); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h74052); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd3) begin - v__h76592 = $time; + v__h74141 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_14_wrkBusy && wci_14_wciResponse_wget[33:32] == 2'd3 && wci_14_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h76592); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h74141); end // synopsys translate_on endmodule // mkOCCP diff --git a/rtl/mkOCDP16B.v b/rtl/mkOCDP16B.v index fea9b946..5e432983 100644 --- a/rtl/mkOCDP16B.v +++ b/rtl/mkOCDP16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:41 EST 2014 +// On Thu Jan 30 15:29:35 EST 2014 // // // Ports: @@ -1594,7 +1594,6 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq, - WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq, WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq, @@ -2381,11 +2380,6 @@ module mkOCDP16B(pciDevice, .FULL_N(wmi_wmi_reqF_FULL_N), .EMPTY_N(wmi_wmi_reqF_EMPTY_N)); - // rule RL_bram_2_serverAdapterA_outData_setFirstEnq - assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq = - !bram_2_serverAdapterA_outDataCore_EMPTY_N && - bram_2_serverAdapterA_outData_enqData_whas ; - // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N && @@ -3671,12 +3665,13 @@ module mkOCDP16B(pciDevice, bram_2_serverAdapterA_s1[1] && bram_2_serverAdapterA_s1[0] ; assign bram_2_serverAdapterA_outData_outData_wget = - WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ? - bram_2_memory_DOA : - bram_2_serverAdapterA_outDataCore_D_OUT ; + bram_2_serverAdapterA_outDataCore_EMPTY_N ? + bram_2_serverAdapterA_outDataCore_D_OUT : + bram_2_memory_DOA ; assign bram_2_serverAdapterA_outData_outData_whas = - WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq || - bram_2_serverAdapterA_outDataCore_EMPTY_N ; + bram_2_serverAdapterA_outDataCore_EMPTY_N || + !bram_2_serverAdapterA_outDataCore_EMPTY_N && + bram_2_serverAdapterA_outData_enqData_whas ; assign bram_2_serverAdapterA_cnt_1_wget = 3'd1 ; assign bram_2_serverAdapterA_cnt_1_whas = (MUX_bram_2_memory_a_put_1__SEL_1 || diff --git a/rtl/mkOCInf16B.v b/rtl/mkOCInf16B.v index b03cc3d4..ad72f8e8 100644 --- a/rtl/mkOCInf16B.v +++ b/rtl/mkOCInf16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:46 EST 2014 +// On Thu Jan 30 15:34:06 EST 2014 // // // Ports: @@ -109,8 +109,6 @@ // RDY_cpNow O 1 const // gps_ppsSyncOut O 1 // RDY_uuid O 1 const -// upads_rts O 1 const -// upads_tx O 1 reg // RST_N_wci_m_0 O 1 reset // RST_N_wci_m_1 O 1 reset // RST_N_wci_m_2 O 1 reset @@ -189,8 +187,6 @@ // wmiDP1_arg_mFlag I 32 reg // gps_ppsSyncIn_x I 1 reg // uuid_arg I 512 -// upads_cts_arg I 1 reg -// upads_rx_arg I 1 reg // EN_server_request_put I 1 // EN_cpServer_request_put I 1 // wci_m_0_SThreadBusy I 1 reg @@ -608,14 +604,6 @@ module mkOCInf16B(pciDevice, EN_uuid, RDY_uuid, - upads_rts, - - upads_tx, - - upads_cts_arg, - - upads_rx_arg, - RST_N_wci_m_0, RST_N_wci_m_1, RST_N_wci_m_2, @@ -1184,18 +1172,6 @@ module mkOCInf16B(pciDevice, input EN_uuid; output RDY_uuid; - // value method upads_rts - output upads_rts; - - // value method upads_tx - output upads_tx; - - // action method upads_cts - input upads_cts_arg; - - // action method upads_rx - input upads_rx_arg; - // output resets output RST_N_wci_m_0; output RST_N_wci_m_1; @@ -1306,8 +1282,6 @@ module mkOCInf16B(pciDevice, RST_N_wci_m_8, RST_N_wci_m_9, gps_ppsSyncOut, - upads_rts, - upads_tx, wci_m_0_MAddrSpace, wci_m_10_MAddrSpace, wci_m_11_MAddrSpace, @@ -1483,10 +1457,6 @@ module mkOCInf16B(pciDevice, cp_RST_N_wci_Vm_9, cp_gps_ppsSyncIn_x, cp_gps_ppsSyncOut, - cp_upads_cts_arg, - cp_upads_rts, - cp_upads_rx_arg, - cp_upads_tx, cp_wci_Vm_0_MAddrSpace, cp_wci_Vm_0_SThreadBusy, cp_wci_Vm_10_MAddrSpace, @@ -1745,8 +1715,8 @@ module mkOCInf16B(pciDevice, wire MUX_cpMux_aActF_enq_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h1864; - wire [15 : 0] x__h2831, x__h3125; + reg [63 : 0] v__h1839; + wire [15 : 0] x__h2806, x__h3100; wire cpMux_aActF_i_notEmpty__1_AND_IF_cpMux_aActF_f_ETC___d46; // output resets @@ -2067,12 +2037,6 @@ module mkOCInf16B(pciDevice, // action method uuid assign RDY_uuid = 1'd1 ; - // value method upads_rts - assign upads_rts = cp_upads_rts ; - - // value method upads_tx - assign upads_tx = cp_upads_tx ; - // submodule cp mkOCCP cp(.pciDevice(pciDevice), .CLK_time_clk(CLK_sys0_clk), @@ -2082,8 +2046,6 @@ module mkOCInf16B(pciDevice, .gps_ppsSyncIn_x(cp_gps_ppsSyncIn_x), .server_request_put(cp_server_request_put), .switch_x(cp_switch_x), - .upads_cts_arg(cp_upads_cts_arg), - .upads_rx_arg(cp_upads_rx_arg), .uuid_arg(cp_uuid_arg), .wci_Vm_0_SData(cp_wci_Vm_0_SData), .wci_Vm_0_SFlag(cp_wci_Vm_0_SFlag), @@ -2244,8 +2206,6 @@ module mkOCInf16B(pciDevice, .RDY_cpNow(), .gps_ppsSyncOut(cp_gps_ppsSyncOut), .led(cp_led), - .upads_rts(cp_upads_rts), - .upads_tx(cp_upads_tx), .RST_N_wci_Vm_0(cp_RST_N_wci_Vm_0), .RST_N_wci_Vm_1(cp_RST_N_wci_Vm_1), .RST_N_wci_Vm_2(cp_RST_N_wci_Vm_2), @@ -2359,7 +2319,7 @@ module mkOCInf16B(pciDevice, // submodule dp0 mkOCDP16B #(.hasPush(1'd0), .hasPull(1'd1), - .hasDebugLogic(1'd1)) dp0(.pciDevice(x__h2831), + .hasDebugLogic(1'd1)) dp0(.pciDevice(x__h2806), .CLK(CLK), .RST_N(cp_RST_N_wci_Vm_13), .server_request_put(dp0_server_request_put), @@ -2404,7 +2364,7 @@ module mkOCInf16B(pciDevice, // submodule dp1 mkOCDP16B #(.hasPush(1'd1), .hasPull(1'd0), - .hasDebugLogic(1'd1)) dp1(.pciDevice(x__h3125), + .hasDebugLogic(1'd1)) dp1(.pciDevice(x__h3100), .CLK(CLK), .RST_N(cp_RST_N_wci_Vm_14), .server_request_put(dp1_server_request_put), @@ -2572,8 +2532,6 @@ module mkOCInf16B(pciDevice, assign cp_gps_ppsSyncIn_x = gps_ppsSyncIn_x ; assign cp_server_request_put = cpMux_cpReqF_D_OUT ; assign cp_switch_x = switch_x ; - assign cp_upads_cts_arg = upads_cts_arg ; - assign cp_upads_rx_arg = upads_rx_arg ; assign cp_uuid_arg = uuid_arg ; assign cp_wci_Vm_0_SData = wci_m_0_SData ; assign cp_wci_Vm_0_SFlag = wci_m_0_SFlag ; @@ -2699,9 +2657,9 @@ module mkOCInf16B(pciDevice, assign cpTlp_client_response_put = cpMux_respAF_D_OUT ; assign cpTlp_server_request_put = noc_sm0_c0_request_get ; assign cpTlp_EN_server_request_put = - cpTlp_RDY_server_request_put && noc_sm0_RDY_c0_request_get ; + noc_sm0_RDY_c0_request_get && cpTlp_RDY_server_request_put ; assign cpTlp_EN_server_response_get = - cpTlp_RDY_server_response_get && noc_sm0_RDY_c0_response_put ; + noc_sm0_RDY_c0_response_put && cpTlp_RDY_server_response_get ; assign cpTlp_EN_client_request_get = cpTlp_RDY_client_request_get && cpMux_reqAF_FULL_N ; assign cpTlp_EN_client_response_put = @@ -2729,9 +2687,9 @@ module mkOCInf16B(pciDevice, assign dp0_wmiS0_MDataLast = wmiDP0_MDataLast ; assign dp0_wmiS0_MReset_n = wmiDP0_MReset_n ; assign dp0_EN_server_request_put = - dp0_RDY_server_request_put && noc_sm1_RDY_c0_request_get ; + noc_sm1_RDY_c0_request_get && dp0_RDY_server_request_put ; assign dp0_EN_server_response_get = - dp0_RDY_server_response_get && noc_sm1_RDY_c0_response_put ; + noc_sm1_RDY_c0_response_put && dp0_RDY_server_response_get ; // submodule dp1 assign dp1_server_request_put = noc_sm2_c0_request_get ; @@ -2755,9 +2713,9 @@ module mkOCInf16B(pciDevice, assign dp1_wmiS0_MDataLast = wmiDP1_MDataLast ; assign dp1_wmiS0_MReset_n = wmiDP1_MReset_n ; assign dp1_EN_server_request_put = - dp1_RDY_server_request_put && noc_sm2_RDY_c0_request_get ; + noc_sm2_RDY_c0_request_get && dp1_RDY_server_request_put ; assign dp1_EN_server_response_get = - dp1_RDY_server_response_get && noc_sm2_RDY_c0_response_put ; + noc_sm2_RDY_c0_response_put && dp1_RDY_server_response_get ; // submodule itc0 assign itc0_gpsTime_arg = cp_cpNow ; @@ -2778,43 +2736,43 @@ module mkOCInf16B(pciDevice, assign noc_sm0_EN_s_request_put = EN_server_request_put ; assign noc_sm0_EN_s_response_get = EN_server_response_get ; assign noc_sm0_EN_c0_request_get = - cpTlp_RDY_server_request_put && noc_sm0_RDY_c0_request_get ; + noc_sm0_RDY_c0_request_get && cpTlp_RDY_server_request_put ; assign noc_sm0_EN_c0_response_put = - cpTlp_RDY_server_response_get && noc_sm0_RDY_c0_response_put ; + noc_sm0_RDY_c0_response_put && cpTlp_RDY_server_response_get ; assign noc_sm0_EN_c1_request_get = - noc_sm0_RDY_c1_request_get && noc_sm1_RDY_s_request_put ; + noc_sm1_RDY_s_request_put && noc_sm0_RDY_c1_request_get ; assign noc_sm0_EN_c1_response_put = - noc_sm0_RDY_c1_response_put && noc_sm1_RDY_s_response_get ; + noc_sm1_RDY_s_response_get && noc_sm0_RDY_c1_response_put ; // submodule noc_sm1 assign noc_sm1_c0_response_put = dp0_server_response_get ; assign noc_sm1_c1_response_put = noc_sm2_s_response_get ; assign noc_sm1_s_request_put = noc_sm0_c1_request_get ; assign noc_sm1_EN_s_request_put = - noc_sm0_RDY_c1_request_get && noc_sm1_RDY_s_request_put ; + noc_sm1_RDY_s_request_put && noc_sm0_RDY_c1_request_get ; assign noc_sm1_EN_s_response_get = - noc_sm0_RDY_c1_response_put && noc_sm1_RDY_s_response_get ; + noc_sm1_RDY_s_response_get && noc_sm0_RDY_c1_response_put ; assign noc_sm1_EN_c0_request_get = - dp0_RDY_server_request_put && noc_sm1_RDY_c0_request_get ; + noc_sm1_RDY_c0_request_get && dp0_RDY_server_request_put ; assign noc_sm1_EN_c0_response_put = - dp0_RDY_server_response_get && noc_sm1_RDY_c0_response_put ; + noc_sm1_RDY_c0_response_put && dp0_RDY_server_response_get ; assign noc_sm1_EN_c1_request_get = - noc_sm1_RDY_c1_request_get && noc_sm2_RDY_s_request_put ; + noc_sm2_RDY_s_request_put && noc_sm1_RDY_c1_request_get ; assign noc_sm1_EN_c1_response_put = - noc_sm1_RDY_c1_response_put && noc_sm2_RDY_s_response_get ; + noc_sm2_RDY_s_response_get && noc_sm1_RDY_c1_response_put ; // submodule noc_sm2 assign noc_sm2_c0_response_put = dp1_server_response_get ; assign noc_sm2_c1_response_put = 153'h0 ; assign noc_sm2_s_request_put = noc_sm1_c1_request_get ; assign noc_sm2_EN_s_request_put = - noc_sm1_RDY_c1_request_get && noc_sm2_RDY_s_request_put ; + noc_sm2_RDY_s_request_put && noc_sm1_RDY_c1_request_get ; assign noc_sm2_EN_s_response_get = - noc_sm1_RDY_c1_response_put && noc_sm2_RDY_s_response_get ; + noc_sm2_RDY_s_response_get && noc_sm1_RDY_c1_response_put ; assign noc_sm2_EN_c0_request_get = - dp1_RDY_server_request_put && noc_sm2_RDY_c0_request_get ; + noc_sm2_RDY_c0_request_get && dp1_RDY_server_request_put ; assign noc_sm2_EN_c0_response_put = - dp1_RDY_server_response_get && noc_sm2_RDY_c0_response_put ; + noc_sm2_RDY_c0_response_put && dp1_RDY_server_response_get ; assign noc_sm2_EN_c1_request_get = noc_sm2_RDY_c1_request_get ; assign noc_sm2_EN_c1_response_put = 1'b0 ; @@ -2822,8 +2780,8 @@ module mkOCInf16B(pciDevice, assign cpMux_aActF_i_notEmpty__1_AND_IF_cpMux_aActF_f_ETC___d46 = cpMux_aActF_EMPTY_N && (cpMux_aActF_D_OUT ? cpMux_respAF_FULL_N : cpMux_respBF_FULL_N) ; - assign x__h2831 = { pciDevice[15:3], 3'd0 } ; - assign x__h3125 = { pciDevice[15:3], 3'd1 } ; + assign x__h2806 = { pciDevice[15:3], 3'd0 } ; + assign x__h3100 = { pciDevice[15:3], 3'd1 } ; // handling of inlined registers @@ -2859,13 +2817,13 @@ module mkOCInf16B(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (noc_sm2_RDY_c1_request_get) begin - v__h1864 = $time; + v__h1839 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (noc_sm2_RDY_c1_request_get) $display("[%0d]: %m: UNHANDLED TLP chompCnt:%0x", - v__h1864, + v__h1839, $unsigned(noc_chompCnt)); end // synopsys translate_on diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index b6a7eda9..407528fa 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index c42c1584..57c57caf 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index 499be5a7..0502c515 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:37 EST 2014 +// On Thu Jan 30 14:50:41 EST 2014 // // // Ports: diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index 171db45b..de138fb8 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:38 EST 2014 +// On Thu Jan 30 14:50:43 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index b22972e7..9530ba6d 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:28 EST 2014 +// On Thu Jan 30 15:27:24 EST 2014 // // // Ports: @@ -939,16 +939,16 @@ module mkSMAdapter16B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; wire [168 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1, MUX_wsiM_reqFifo_q_0_write_1__VAL_2, - MUX_wsiM_reqFifo_q_1_write_1__VAL_2, + MUX_wsiM_reqFifo_q_1_write_1__VAL_1, MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3; wire [145 : 0] MUX_wmi_dhF_q_0_write_1__VAL_1, MUX_wmi_dhF_q_0_write_1__VAL_2, - MUX_wmi_dhF_q_1_write_1__VAL_2; + MUX_wmi_dhF_q_1_write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount_write_1__VAL_2, + wire [31 : 0] MUX_mesgCount_write_1__VAL_1, MUX_thisMesg_write_1__VAL_1, MUX_thisMesg_write_1__VAL_2, MUX_wmi_mFlagF_q_0_write_1__VAL_1, @@ -1491,13 +1491,13 @@ module mkSMAdapter16B(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; - assign MUX_wmi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; - assign MUX_wmi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_2 = @@ -1517,13 +1517,13 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wmi_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; + assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; @@ -1539,7 +1539,7 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_fabWordsRemain_write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain_write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount_write_1__VAL_2 = mesgCount + 32'd1 ; + assign MUX_mesgCount_write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgReqAddr_write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ; assign MUX_opcode_write_1__VAL_3 = { 1'd1, wsiS_reqFifo_D_OUT[7:0] } ; @@ -1587,14 +1587,14 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h24937 } ; assign MUX_wmi_dhF_cntr_r_write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__VAL_1 = - { 1'd1, wsiS_reqFifo_D_OUT[165], wsiS_reqFifo_D_OUT[151:8] } ; - assign MUX_wmi_dhF_q_0_write_1__VAL_2 = (wmi_dhF_cntr_r == 2'd1) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1_write_1__VAL_2 = + assign MUX_wmi_dhF_q_0_write_1__VAL_2 = + { 1'd1, wsiS_reqFifo_D_OUT[165], wsiS_reqFifo_D_OUT[151:8] } ; + assign MUX_wmi_dhF_q_1_write_1__VAL_1 = (wmi_dhF_cntr_r == 2'd2) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : 146'd0 ; assign MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__VAL_1 = @@ -1623,17 +1623,17 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2) ? wsiS_reqFifo_D_OUT : MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = - (wsiM_reqFifo_cntr_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__VAL_2 = + assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 = (respF_rCache[181] && respF_rCache[180:169] == respF_rRdPtr) ? @@ -1676,7 +1676,7 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_mFlagF_x_wire_wget = value__h6387 ; assign wmi_mFlagF_x_wire_whas = wmi_mFlagF_enqueueing_whas ; - assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_1 ; + assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_2 ; assign wmi_dhF_x_wire_whas = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_wmiResponse_wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse_whas = 1'd1 ; @@ -1688,7 +1688,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_operateD_1_whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1_wget = 1'd1 ; assign wmi_peerIsReady_1_whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_1 ; + assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ; assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ; assign wsiM_operateD_1_wget = 1'd1 ; assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ; @@ -1865,14 +1865,14 @@ module mkSMAdapter16B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount_write_1__SEL_1 or - MUX_mesgCount_write_1__VAL_2 or + MUX_mesgCount_write_1__VAL_1 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount_write_1__SEL_1: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount_D_IN = 32'd0; default: mesgCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2150,29 +2150,29 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wmi_dhF_q_0_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 always@(MUX_wmi_dhF_q_1_write_1__SEL_1 or - MUX_wmi_dhF_q_0_write_1__VAL_1 or + MUX_wmi_dhF_q_1_write_1__VAL_1 or MUX_wmi_dhF_q_1_write_1__SEL_2 or - MUX_wmi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmi_dhF_q_1_write_1__SEL_1: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_1; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_1; MUX_wmi_dhF_q_1_write_1__SEL_2: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_2; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1_D_IN = 146'd0; default: wmi_dhF_q_1_D_IN = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2391,23 +2391,23 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or - MUX_wsiM_reqFifo_q_1_write_1__VAL_2 or + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wsiM_reqFifo_q_1_write_1__SEL_1: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1; MUX_wsiM_reqFifo_q_1_write_1__SEL_2: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_2; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1_D_IN = 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; @@ -2416,9 +2416,9 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index 7ad22860..52829c87 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:34 EST 2014 +// On Thu Jan 30 15:27:30 EST 2014 // // // Ports: @@ -938,11 +938,11 @@ module mkSMAdapter32B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; wire [312 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1, MUX_wsiM_reqFifo_q_0_write_1__VAL_2, - MUX_wsiM_reqFifo_q_1_write_1__VAL_2, + MUX_wsiM_reqFifo_q_1_write_1__VAL_1, MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3; wire [289 : 0] MUX_wmi_dhF_q_0_write_1__VAL_1, MUX_wmi_dhF_q_0_write_1__VAL_2, - MUX_wmi_dhF_q_1_write_1__VAL_2; + MUX_wmi_dhF_q_1_write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, @@ -1520,13 +1520,13 @@ module mkSMAdapter32B(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; - assign MUX_wmi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; - assign MUX_wmi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_2 = @@ -1546,13 +1546,13 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wmi_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; + assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 = WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2 = @@ -1618,14 +1618,14 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h24896 } ; assign MUX_wmi_dhF_cntr_r_write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__VAL_1 = - { 1'd1, wsiS_reqFifo_D_OUT[309], wsiS_reqFifo_D_OUT[295:8] } ; - assign MUX_wmi_dhF_q_0_write_1__VAL_2 = (wmi_dhF_cntr_r == 2'd1) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1_write_1__VAL_2 = + assign MUX_wmi_dhF_q_0_write_1__VAL_2 = + { 1'd1, wsiS_reqFifo_D_OUT[309], wsiS_reqFifo_D_OUT[295:8] } ; + assign MUX_wmi_dhF_q_1_write_1__VAL_1 = (wmi_dhF_cntr_r == 2'd2) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : 290'd0 ; assign MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__VAL_1 = @@ -1654,17 +1654,17 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2) ? wsiS_reqFifo_D_OUT : MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = - (wsiM_reqFifo_cntr_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__VAL_2 = + assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 = (respF_rCache[325] && respF_rCache[324:313] == respF_rRdPtr) ? @@ -1707,7 +1707,7 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_mFlagF_x_wire_wget = value__h6387 ; assign wmi_mFlagF_x_wire_whas = wmi_mFlagF_enqueueing_whas ; - assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_1 ; + assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_2 ; assign wmi_dhF_x_wire_whas = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_wmiResponse_wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse_whas = 1'd1 ; @@ -1719,7 +1719,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_operateD_1_whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1_wget = 1'd1 ; assign wmi_peerIsReady_1_whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_1 ; + assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ; assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ; assign wsiM_operateD_1_wget = 1'd1 ; assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ; @@ -2182,29 +2182,29 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wmi_dhF_q_0_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 always@(MUX_wmi_dhF_q_1_write_1__SEL_1 or - MUX_wmi_dhF_q_0_write_1__VAL_1 or + MUX_wmi_dhF_q_1_write_1__VAL_1 or MUX_wmi_dhF_q_1_write_1__SEL_2 or - MUX_wmi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmi_dhF_q_1_write_1__SEL_1: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_1; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_1; MUX_wmi_dhF_q_1_write_1__SEL_2: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_2; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1_D_IN = 290'd0; default: wmi_dhF_q_1_D_IN = 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2423,23 +2423,23 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or - MUX_wsiM_reqFifo_q_1_write_1__VAL_2 or + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wsiM_reqFifo_q_1_write_1__SEL_1: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1; MUX_wsiM_reqFifo_q_1_write_1__SEL_2: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_2; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1_D_IN = 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; @@ -2448,9 +2448,9 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index f5a6e353..30328901 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:30 EST 2014 +// On Thu Jan 30 15:27:26 EST 2014 // // // Ports: @@ -937,11 +937,11 @@ module mkSMAdapter4B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; wire [60 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1, MUX_wsiM_reqFifo_q_0_write_1__VAL_2, - MUX_wsiM_reqFifo_q_1_write_1__VAL_2, + MUX_wsiM_reqFifo_q_1_write_1__VAL_1, MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3; wire [37 : 0] MUX_wmi_dhF_q_0_write_1__VAL_1, MUX_wmi_dhF_q_0_write_1__VAL_2, - MUX_wmi_dhF_q_1_write_1__VAL_2; + MUX_wmi_dhF_q_1_write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, @@ -1463,13 +1463,13 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; - assign MUX_wmi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; - assign MUX_wmi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_2 = @@ -1489,13 +1489,13 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wmi_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; + assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 = WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2 = @@ -1561,14 +1561,14 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h23748 } ; assign MUX_wmi_dhF_cntr_r_write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__VAL_1 = - { 1'd1, wsiS_reqFifo_D_OUT[57], wsiS_reqFifo_D_OUT[43:8] } ; - assign MUX_wmi_dhF_q_0_write_1__VAL_2 = (wmi_dhF_cntr_r == 2'd1) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1_write_1__VAL_2 = + assign MUX_wmi_dhF_q_0_write_1__VAL_2 = + { 1'd1, wsiS_reqFifo_D_OUT[57], wsiS_reqFifo_D_OUT[43:8] } ; + assign MUX_wmi_dhF_q_1_write_1__VAL_1 = (wmi_dhF_cntr_r == 2'd2) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : 38'd0 ; assign MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__VAL_1 = @@ -1597,17 +1597,17 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2) ? wsiS_reqFifo_D_OUT : MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = - (wsiM_reqFifo_cntr_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__VAL_2 = + assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : 61'h00000AAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 = (respF_rCache[73] && respF_rCache[72:61] == respF_rRdPtr) ? @@ -1650,7 +1650,7 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_mFlagF_x_wire_wget = value__h6387 ; assign wmi_mFlagF_x_wire_whas = wmi_mFlagF_enqueueing_whas ; - assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_1 ; + assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_2 ; assign wmi_dhF_x_wire_whas = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_wmiResponse_wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse_whas = 1'd1 ; @@ -1662,7 +1662,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_operateD_1_whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1_wget = 1'd1 ; assign wmi_peerIsReady_1_whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_1 ; + assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ; assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ; assign wsiM_operateD_1_wget = 1'd1 ; assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ; @@ -2123,28 +2123,28 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wmi_dhF_q_0_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 always@(MUX_wmi_dhF_q_1_write_1__SEL_1 or - MUX_wmi_dhF_q_0_write_1__VAL_1 or + MUX_wmi_dhF_q_1_write_1__VAL_1 or MUX_wmi_dhF_q_1_write_1__SEL_2 or - MUX_wmi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmi_dhF_q_1_write_1__SEL_1: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_1; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_1; MUX_wmi_dhF_q_1_write_1__SEL_2: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_2; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1_D_IN = 38'd0; default: wmi_dhF_q_1_D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2363,23 +2363,23 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or - MUX_wsiM_reqFifo_q_1_write_1__VAL_2 or + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wsiM_reqFifo_q_1_write_1__SEL_1: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1; MUX_wsiM_reqFifo_q_1_write_1__SEL_2: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_2; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1_D_IN = 61'h00000AAAAAAAAA00; default: wsiM_reqFifo_q_1_D_IN = @@ -2387,9 +2387,9 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index 4bd05a26..5c9e167f 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:32 EST 2014 +// On Thu Jan 30 15:27:28 EST 2014 // // // Ports: @@ -937,16 +937,16 @@ module mkSMAdapter8B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; wire [96 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1, MUX_wsiM_reqFifo_q_0_write_1__VAL_2, - MUX_wsiM_reqFifo_q_1_write_1__VAL_2, + MUX_wsiM_reqFifo_q_1_write_1__VAL_1, MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3; wire [73 : 0] MUX_wmi_dhF_q_0_write_1__VAL_1, MUX_wmi_dhF_q_0_write_1__VAL_2, - MUX_wmi_dhF_q_1_write_1__VAL_2; + MUX_wmi_dhF_q_1_write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount_write_1__VAL_2, + wire [31 : 0] MUX_mesgCount_write_1__VAL_1, MUX_thisMesg_write_1__VAL_1, MUX_thisMesg_write_1__VAL_2, MUX_wmi_mFlagF_q_0_write_1__VAL_1, @@ -1470,13 +1470,13 @@ module mkSMAdapter8B(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; - assign MUX_wmi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; - assign MUX_wmi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0_write_1__SEL_2 = @@ -1496,13 +1496,13 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wmi_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; + assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; @@ -1518,7 +1518,7 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_fabWordsRemain_write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain_write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount_write_1__VAL_2 = mesgCount + 32'd1 ; + assign MUX_mesgCount_write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar_write_1__VAL_1 = mesgLengthSoFar + mlInc__h22205 ; assign MUX_mesgReqAddr_write_1__VAL_2 = @@ -1568,14 +1568,14 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h23912 } ; assign MUX_wmi_dhF_cntr_r_write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0_write_1__VAL_1 = - { 1'd1, wsiS_reqFifo_D_OUT[93], wsiS_reqFifo_D_OUT[79:8] } ; - assign MUX_wmi_dhF_q_0_write_1__VAL_2 = (wmi_dhF_cntr_r == 2'd1) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1_write_1__VAL_2 = + assign MUX_wmi_dhF_q_0_write_1__VAL_2 = + { 1'd1, wsiS_reqFifo_D_OUT[93], wsiS_reqFifo_D_OUT[79:8] } ; + assign MUX_wmi_dhF_q_1_write_1__VAL_1 = (wmi_dhF_cntr_r == 2'd2) ? - MUX_wmi_dhF_q_0_write_1__VAL_1 : + MUX_wmi_dhF_q_0_write_1__VAL_2 : 74'd0 ; assign MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0_write_1__VAL_1 = @@ -1604,17 +1604,17 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2) ? wsiS_reqFifo_D_OUT : MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 = - (wsiM_reqFifo_cntr_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_1_write_1__VAL_2 = + assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 : + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 : 97'h00000AAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 = (respF_rCache[109] && respF_rCache[108:97] == respF_rRdPtr) ? @@ -1657,7 +1657,7 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_mFlagF_x_wire_wget = value__h6387 ; assign wmi_mFlagF_x_wire_whas = wmi_mFlagF_enqueueing_whas ; - assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_1 ; + assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_2 ; assign wmi_dhF_x_wire_whas = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ; assign wmi_wmiResponse_wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse_whas = 1'd1 ; @@ -1669,7 +1669,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_operateD_1_whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1_wget = 1'd1 ; assign wmi_peerIsReady_1_whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_1 ; + assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ; assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ; assign wsiM_operateD_1_wget = 1'd1 ; assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ; @@ -1846,14 +1846,14 @@ module mkSMAdapter8B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount_write_1__SEL_1 or - MUX_mesgCount_write_1__VAL_2 or + MUX_mesgCount_write_1__VAL_1 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount_write_1__SEL_1: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount_D_IN = 32'd0; default: mesgCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2132,29 +2132,29 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wmi_dhF_q_0_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 always@(MUX_wmi_dhF_q_1_write_1__SEL_1 or - MUX_wmi_dhF_q_0_write_1__VAL_1 or + MUX_wmi_dhF_q_1_write_1__VAL_1 or MUX_wmi_dhF_q_1_write_1__SEL_2 or - MUX_wmi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmi_dhF_q_1_write_1__SEL_1: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_1; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_1; MUX_wmi_dhF_q_1_write_1__SEL_2: - wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_2; + wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1_D_IN = 74'd0; default: wmi_dhF_q_1_D_IN = 74'h2AAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1_EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2373,23 +2373,23 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or - MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or - MUX_wsiM_reqFifo_q_1_write_1__VAL_2 or + MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wsiM_reqFifo_q_1_write_1__SEL_1: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1; MUX_wsiM_reqFifo_q_1_write_1__SEL_2: - wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_2; + wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1_D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00; default: wsiM_reqFifo_q_1_D_IN = @@ -2397,9 +2397,9 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1_EN = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 || - WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index daff14c2..c628a386 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index adafefab..62904f66 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index 85984787..0ad67a94 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSerializer.v b/rtl/mkTLPSerializer.v index 64ff6ee9..6911a0f1 100644 --- a/rtl/mkTLPSerializer.v +++ b/rtl/mkTLPSerializer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:32 EST 2014 +// On Thu Jan 30 15:29:26 EST 2014 // // // Ports: diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index adf868cc..01db759e 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:50 EST 2014 +// On Thu Jan 30 15:27:46 EST 2014 // // // Ports: diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index 17989480..c3ed86cf 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:07 EST 2014 +// On Thu Jan 30 14:51:11 EST 2014 // // // Ports: diff --git a/rtl/mkUUID.v b/rtl/mkUUID.v index 1cc25873..0babf473 100644 --- a/rtl/mkUUID.v +++ b/rtl/mkUUID.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:47 EST 2014 +// On Thu Jan 30 14:50:51 EST 2014 // // // Ports: diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index c3dc4a1d..c1eed704 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:16 EST 2014 +// On Thu Jan 30 14:51:21 EST 2014 // // // Ports: diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index dda652a5..2b236a34 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:51 EST 2014 +// On Thu Jan 30 14:50:56 EST 2014 // // // Ports: diff --git a/rtl/mkWciMonitor.v b/rtl/mkWciMonitor.v index d43f8d34..688e34ef 100644 --- a/rtl/mkWciMonitor.v +++ b/rtl/mkWciMonitor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:53 EST 2014 +// On Thu Jan 30 14:50:58 EST 2014 // // // Ports: diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index 09486427..b018265e 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 10:59:52 EST 2014 +// On Thu Jan 30 14:50:56 EST 2014 // // // Ports: diff --git a/rtl/mkWmemiTap.v b/rtl/mkWmemiTap.v new file mode 100644 index 00000000..6dc386c9 --- /dev/null +++ b/rtl/mkWmemiTap.v @@ -0,0 +1,1916 @@ +// +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) +// +// On Thu Jan 30 15:27:16 EST 2014 +// +// +// Ports: +// Name I/O size props +// wmemiS0_SResp O 2 reg +// wmemiS0_SRespLast O 1 reg +// wmemiS0_SData O 128 reg +// wmemiS0_SCmdAccept O 1 +// wmemiS0_SDataAccept O 1 +// wmemiM0_MCmd O 3 reg +// wmemiM0_MReqLast O 1 reg +// wmemiM0_MAddr O 36 reg +// wmemiM0_MBurstLength O 12 reg +// wmemiM0_MDataValid O 1 reg +// wmemiM0_MDataLast O 1 reg +// wmemiM0_MData O 128 reg +// wmemiM0_MDataByteEn O 16 reg +// wmemiM0_MReset_n O 1 +// axiM0_wrAddr_data O 35 reg +// axiM0_wrAddr_valid O 1 +// axiM0_wrData_data O 36 reg +// axiM0_wrData_valid O 1 +// axiM0_wrResp_ready O 1 reg +// axiM0_rdAddr_data O 35 reg +// axiM0_rdAddr_valid O 1 +// axiM0_rdResp_ready O 1 reg +// CLK I 1 clock +// RST_N I 1 reset +// wmemiS0_MCmd I 3 +// wmemiS0_MAddr I 36 +// wmemiS0_MBurstLength I 12 +// wmemiS0_MData I 128 +// wmemiS0_MDataByteEn I 16 +// wmemiM0_SResp I 2 +// wmemiM0_SData I 128 +// axiM0_wrAddr_ready_value I 1 +// axiM0_wrData_ready_value I 1 +// axiM0_wrResp_data_value I 2 reg +// axiM0_wrResp_valid_value I 1 +// axiM0_rdAddr_ready_value I 1 +// axiM0_rdResp_data_value I 34 reg +// axiM0_rdResp_valid_value I 1 +// wmemiS0_MReqLast I 1 +// wmemiS0_MDataValid I 1 +// wmemiS0_MDataLast I 1 +// wmemiS0_MReset_n I 1 reg +// wmemiM0_SRespLast I 1 +// wmemiM0_SCmdAccept I 1 +// wmemiM0_SDataAccept I 1 +// +// Combinational paths from inputs to outputs: +// (wmemiS0_MCmd, +// wmemiS0_MAddr, +// wmemiS0_MBurstLength, +// wmemiS0_MReqLast) -> wmemiS0_SCmdAccept +// (wmemiS0_MData, +// wmemiS0_MDataByteEn, +// wmemiS0_MDataValid, +// wmemiS0_MDataLast) -> wmemiS0_SDataAccept +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkWmemiTap(CLK, + RST_N, + + wmemiS0_MCmd, + + wmemiS0_MReqLast, + + wmemiS0_MAddr, + + wmemiS0_MBurstLength, + + wmemiS0_MDataValid, + + wmemiS0_MDataLast, + + wmemiS0_MData, + + wmemiS0_MDataByteEn, + + wmemiS0_SResp, + + wmemiS0_SRespLast, + + wmemiS0_SData, + + wmemiS0_SCmdAccept, + + wmemiS0_SDataAccept, + + wmemiS0_MReset_n, + + wmemiM0_MCmd, + + wmemiM0_MReqLast, + + wmemiM0_MAddr, + + wmemiM0_MBurstLength, + + wmemiM0_MDataValid, + + wmemiM0_MDataLast, + + wmemiM0_MData, + + wmemiM0_MDataByteEn, + + wmemiM0_SResp, + + wmemiM0_SRespLast, + + wmemiM0_SData, + + wmemiM0_SCmdAccept, + + wmemiM0_SDataAccept, + + wmemiM0_MReset_n, + + axiM0_wrAddr_data, + + axiM0_wrAddr_valid, + + axiM0_wrAddr_ready_value, + + axiM0_wrData_data, + + axiM0_wrData_valid, + + axiM0_wrData_ready_value, + + axiM0_wrResp_data_value, + + axiM0_wrResp_valid_value, + + axiM0_wrResp_ready, + + axiM0_rdAddr_data, + + axiM0_rdAddr_valid, + + axiM0_rdAddr_ready_value, + + axiM0_rdResp_data_value, + + axiM0_rdResp_valid_value, + + axiM0_rdResp_ready); + input CLK; + input RST_N; + + // action method wmemiS0_mCmd + input [2 : 0] wmemiS0_MCmd; + + // action method wmemiS0_mReqLast + input wmemiS0_MReqLast; + + // action method wmemiS0_mAddr + input [35 : 0] wmemiS0_MAddr; + + // action method wmemiS0_mBurstLength + input [11 : 0] wmemiS0_MBurstLength; + + // action method wmemiS0_mDataValid + input wmemiS0_MDataValid; + + // action method wmemiS0_mDataLast + input wmemiS0_MDataLast; + + // action method wmemiS0_mData + input [127 : 0] wmemiS0_MData; + + // action method wmemiS0_mDataByteEn + input [15 : 0] wmemiS0_MDataByteEn; + + // value method wmemiS0_sResp + output [1 : 0] wmemiS0_SResp; + + // value method wmemiS0_sRespLast + output wmemiS0_SRespLast; + + // value method wmemiS0_sData + output [127 : 0] wmemiS0_SData; + + // value method wmemiS0_sCmdAccept + output wmemiS0_SCmdAccept; + + // value method wmemiS0_sDataAccept + output wmemiS0_SDataAccept; + + // action method wmemiS0_mReset_n + input wmemiS0_MReset_n; + + // value method wmemiM0_mCmd + output [2 : 0] wmemiM0_MCmd; + + // value method wmemiM0_mReqLast + output wmemiM0_MReqLast; + + // value method wmemiM0_mAddr + output [35 : 0] wmemiM0_MAddr; + + // value method wmemiM0_mBurstLength + output [11 : 0] wmemiM0_MBurstLength; + + // value method wmemiM0_mDataValid + output wmemiM0_MDataValid; + + // value method wmemiM0_mDataLast + output wmemiM0_MDataLast; + + // value method wmemiM0_mData + output [127 : 0] wmemiM0_MData; + + // value method wmemiM0_mDataByteEn + output [15 : 0] wmemiM0_MDataByteEn; + + // action method wmemiM0_sResp + input [1 : 0] wmemiM0_SResp; + + // action method wmemiM0_sRespLast + input wmemiM0_SRespLast; + + // action method wmemiM0_sData + input [127 : 0] wmemiM0_SData; + + // action method wmemiM0_sCmdAccept + input wmemiM0_SCmdAccept; + + // action method wmemiM0_sDataAccept + input wmemiM0_SDataAccept; + + // value method wmemiM0_mReset_n + output wmemiM0_MReset_n; + + // value method axiM0_wrAddr_data + output [34 : 0] axiM0_wrAddr_data; + + // value method axiM0_wrAddr_valid + output axiM0_wrAddr_valid; + + // action method axiM0_wrAddr_ready + input axiM0_wrAddr_ready_value; + + // value method axiM0_wrData_data + output [35 : 0] axiM0_wrData_data; + + // value method axiM0_wrData_valid + output axiM0_wrData_valid; + + // action method axiM0_wrData_ready + input axiM0_wrData_ready_value; + + // action method axiM0_wrResp_data + input [1 : 0] axiM0_wrResp_data_value; + + // action method axiM0_wrResp_valid + input axiM0_wrResp_valid_value; + + // value method axiM0_wrResp_ready + output axiM0_wrResp_ready; + + // value method axiM0_rdAddr_data + output [34 : 0] axiM0_rdAddr_data; + + // value method axiM0_rdAddr_valid + output axiM0_rdAddr_valid; + + // action method axiM0_rdAddr_ready + input axiM0_rdAddr_ready_value; + + // action method axiM0_rdResp_data + input [33 : 0] axiM0_rdResp_data_value; + + // action method axiM0_rdResp_valid + input axiM0_rdResp_valid_value; + + // value method axiM0_rdResp_ready + output axiM0_rdResp_ready; + + // signals for module outputs + wire [127 : 0] wmemiM0_MData, wmemiS0_SData; + wire [35 : 0] axiM0_wrData_data, wmemiM0_MAddr; + wire [34 : 0] axiM0_rdAddr_data, axiM0_wrAddr_data; + wire [15 : 0] wmemiM0_MDataByteEn; + wire [11 : 0] wmemiM0_MBurstLength; + wire [2 : 0] wmemiM0_MCmd; + wire [1 : 0] wmemiS0_SResp; + wire axiM0_rdAddr_valid, + axiM0_rdResp_ready, + axiM0_wrAddr_valid, + axiM0_wrData_valid, + axiM0_wrResp_ready, + wmemiM0_MDataLast, + wmemiM0_MDataValid, + wmemiM0_MReqLast, + wmemiM0_MReset_n, + wmemiS0_SCmdAccept, + wmemiS0_SDataAccept, + wmemiS0_SRespLast; + + // inlined wires + wire [145 : 0] wmemiM_dhF_x_wire_wget, wmemiS_wmemiDh_wget; + wire [130 : 0] wmemiM_wmemiResponse_wget, wmemiS_respF_x_wire_wget; + wire [127 : 0] wmemi_Em_sData_w_wget, wmemi_Es_mData_w_wget; + wire [51 : 0] wmemiM_reqF_x_wire_wget, wmemiS_wmemiReq_wget; + wire [35 : 0] a4l_a4wrData_fifof_x_wire_wget, wmemi_Es_mAddr_w_wget; + wire [34 : 0] a4l_a4rdAddr_fifof_x_wire_wget, + a4l_a4wrAddr_fifof_x_wire_wget; + wire [33 : 0] a4l_a4rdResp_data_wire_wget; + wire [15 : 0] wmemi_Es_mDataByteEn_w_wget; + wire [11 : 0] wmemi_Es_mBurstLength_w_wget; + wire [2 : 0] wmemi_Es_mCmd_w_wget; + wire [1 : 0] a4l_a4wrResp_data_wire_wget, wmemi_Em_sResp_w_wget; + wire a4l_a4rdAddr_deq_deq_whas, + a4l_a4rdAddr_deq_ready_whas, + a4l_a4rdAddr_fifof_dequeueing_whas, + a4l_a4rdAddr_fifof_enqueueing_whas, + a4l_a4rdAddr_fifof_x_wire_whas, + a4l_a4rdResp_enq_enq_whas, + a4l_a4rdResp_enq_valid_whas, + a4l_a4wrAddr_deq_deq_whas, + a4l_a4wrAddr_deq_ready_whas, + a4l_a4wrAddr_fifof_dequeueing_whas, + a4l_a4wrAddr_fifof_enqueueing_whas, + a4l_a4wrAddr_fifof_x_wire_whas, + a4l_a4wrData_deq_deq_whas, + a4l_a4wrData_deq_ready_whas, + a4l_a4wrData_fifof_dequeueing_whas, + a4l_a4wrData_fifof_enqueueing_whas, + a4l_a4wrData_fifof_x_wire_whas, + a4l_a4wrResp_enq_enq_whas, + a4l_a4wrResp_enq_valid_whas, + wmemiM_dhF_dequeueing_whas, + wmemiM_dhF_enqueueing_whas, + wmemiM_dhF_x_wire_whas, + wmemiM_operateD_1_wget, + wmemiM_operateD_1_whas, + wmemiM_peerIsReady_1_wget, + wmemiM_peerIsReady_1_whas, + wmemiM_reqF_dequeueing_whas, + wmemiM_reqF_enqueueing_whas, + wmemiM_reqF_x_wire_whas, + wmemiM_sCmdAccept_w_wget, + wmemiM_sCmdAccept_w_whas, + wmemiM_sDataAccept_w_wget, + wmemiM_sDataAccept_w_whas, + wmemiM_wmemiResponse_whas, + wmemiS_cmdAccept_w_wget, + wmemiS_cmdAccept_w_whas, + wmemiS_dhAccept_w_wget, + wmemiS_dhAccept_w_whas, + wmemiS_operateD_1_wget, + wmemiS_operateD_1_whas, + wmemiS_peerIsReady_1_wget, + wmemiS_peerIsReady_1_whas, + wmemiS_respF_dequeueing_whas, + wmemiS_respF_enqueueing_whas, + wmemiS_respF_x_wire_whas, + wmemiS_wmemiDh_whas, + wmemiS_wmemiReq_whas, + wmemi_Em_sData_w_whas, + wmemi_Em_sRespLast_w_whas, + wmemi_Em_sResp_w_whas, + wmemi_Es_mAddr_w_whas, + wmemi_Es_mBurstLength_w_whas, + wmemi_Es_mCmd_w_whas, + wmemi_Es_mDataByteEn_w_whas, + wmemi_Es_mDataLast_w_whas, + wmemi_Es_mDataValid_w_whas, + wmemi_Es_mData_w_whas, + wmemi_Es_mReqLast_w_whas; + + // register a4l_a4rdAddr_fifof_cntr_r + reg [1 : 0] a4l_a4rdAddr_fifof_cntr_r; + wire [1 : 0] a4l_a4rdAddr_fifof_cntr_r_D_IN; + wire a4l_a4rdAddr_fifof_cntr_r_EN; + + // register a4l_a4rdAddr_fifof_q_0 + reg [34 : 0] a4l_a4rdAddr_fifof_q_0; + reg [34 : 0] a4l_a4rdAddr_fifof_q_0_D_IN; + wire a4l_a4rdAddr_fifof_q_0_EN; + + // register a4l_a4rdAddr_fifof_q_1 + reg [34 : 0] a4l_a4rdAddr_fifof_q_1; + reg [34 : 0] a4l_a4rdAddr_fifof_q_1_D_IN; + wire a4l_a4rdAddr_fifof_q_1_EN; + + // register a4l_a4wrAddr_fifof_cntr_r + reg [1 : 0] a4l_a4wrAddr_fifof_cntr_r; + wire [1 : 0] a4l_a4wrAddr_fifof_cntr_r_D_IN; + wire a4l_a4wrAddr_fifof_cntr_r_EN; + + // register a4l_a4wrAddr_fifof_q_0 + reg [34 : 0] a4l_a4wrAddr_fifof_q_0; + reg [34 : 0] a4l_a4wrAddr_fifof_q_0_D_IN; + wire a4l_a4wrAddr_fifof_q_0_EN; + + // register a4l_a4wrAddr_fifof_q_1 + reg [34 : 0] a4l_a4wrAddr_fifof_q_1; + reg [34 : 0] a4l_a4wrAddr_fifof_q_1_D_IN; + wire a4l_a4wrAddr_fifof_q_1_EN; + + // register a4l_a4wrData_fifof_cntr_r + reg [1 : 0] a4l_a4wrData_fifof_cntr_r; + wire [1 : 0] a4l_a4wrData_fifof_cntr_r_D_IN; + wire a4l_a4wrData_fifof_cntr_r_EN; + + // register a4l_a4wrData_fifof_q_0 + reg [35 : 0] a4l_a4wrData_fifof_q_0; + reg [35 : 0] a4l_a4wrData_fifof_q_0_D_IN; + wire a4l_a4wrData_fifof_q_0_EN; + + // register a4l_a4wrData_fifof_q_1 + reg [35 : 0] a4l_a4wrData_fifof_q_1; + reg [35 : 0] a4l_a4wrData_fifof_q_1_D_IN; + wire a4l_a4wrData_fifof_q_1_EN; + + // register axiActive + reg axiActive; + wire axiActive_D_IN, axiActive_EN; + + // register wmemiM_busyWithMessage + reg wmemiM_busyWithMessage; + wire wmemiM_busyWithMessage_D_IN, wmemiM_busyWithMessage_EN; + + // register wmemiM_dhF_cntr_r + reg [1 : 0] wmemiM_dhF_cntr_r; + wire [1 : 0] wmemiM_dhF_cntr_r_D_IN; + wire wmemiM_dhF_cntr_r_EN; + + // register wmemiM_dhF_q_0 + reg [145 : 0] wmemiM_dhF_q_0; + reg [145 : 0] wmemiM_dhF_q_0_D_IN; + wire wmemiM_dhF_q_0_EN; + + // register wmemiM_dhF_q_1 + reg [145 : 0] wmemiM_dhF_q_1; + reg [145 : 0] wmemiM_dhF_q_1_D_IN; + wire wmemiM_dhF_q_1_EN; + + // register wmemiM_errorSticky + reg wmemiM_errorSticky; + wire wmemiM_errorSticky_D_IN, wmemiM_errorSticky_EN; + + // register wmemiM_isReset_isInReset + reg wmemiM_isReset_isInReset; + wire wmemiM_isReset_isInReset_D_IN, wmemiM_isReset_isInReset_EN; + + // register wmemiM_operateD + reg wmemiM_operateD; + wire wmemiM_operateD_D_IN, wmemiM_operateD_EN; + + // register wmemiM_peerIsReady + reg wmemiM_peerIsReady; + wire wmemiM_peerIsReady_D_IN, wmemiM_peerIsReady_EN; + + // register wmemiM_reqF_cntr_r + reg [1 : 0] wmemiM_reqF_cntr_r; + wire [1 : 0] wmemiM_reqF_cntr_r_D_IN; + wire wmemiM_reqF_cntr_r_EN; + + // register wmemiM_reqF_q_0 + reg [51 : 0] wmemiM_reqF_q_0; + reg [51 : 0] wmemiM_reqF_q_0_D_IN; + wire wmemiM_reqF_q_0_EN; + + // register wmemiM_reqF_q_1 + reg [51 : 0] wmemiM_reqF_q_1; + reg [51 : 0] wmemiM_reqF_q_1_D_IN; + wire wmemiM_reqF_q_1_EN; + + // register wmemiM_statusR + reg [7 : 0] wmemiM_statusR; + wire [7 : 0] wmemiM_statusR_D_IN; + wire wmemiM_statusR_EN; + + // register wmemiM_trafficSticky + reg wmemiM_trafficSticky; + wire wmemiM_trafficSticky_D_IN, wmemiM_trafficSticky_EN; + + // register wmemiS_errorSticky + reg wmemiS_errorSticky; + wire wmemiS_errorSticky_D_IN, wmemiS_errorSticky_EN; + + // register wmemiS_isReset_isInReset + reg wmemiS_isReset_isInReset; + wire wmemiS_isReset_isInReset_D_IN, wmemiS_isReset_isInReset_EN; + + // register wmemiS_operateD + reg wmemiS_operateD; + wire wmemiS_operateD_D_IN, wmemiS_operateD_EN; + + // register wmemiS_peerIsReady + reg wmemiS_peerIsReady; + wire wmemiS_peerIsReady_D_IN, wmemiS_peerIsReady_EN; + + // register wmemiS_respF_cntr_r + reg [1 : 0] wmemiS_respF_cntr_r; + wire [1 : 0] wmemiS_respF_cntr_r_D_IN; + wire wmemiS_respF_cntr_r_EN; + + // register wmemiS_respF_q_0 + reg [130 : 0] wmemiS_respF_q_0; + reg [130 : 0] wmemiS_respF_q_0_D_IN; + wire wmemiS_respF_q_0_EN; + + // register wmemiS_respF_q_1 + reg [130 : 0] wmemiS_respF_q_1; + reg [130 : 0] wmemiS_respF_q_1_D_IN; + wire wmemiS_respF_q_1_EN; + + // register wmemiS_statusR + reg [7 : 0] wmemiS_statusR; + wire [7 : 0] wmemiS_statusR_D_IN; + wire wmemiS_statusR_EN; + + // register wmemiS_trafficSticky + reg wmemiS_trafficSticky; + wire wmemiS_trafficSticky_D_IN, wmemiS_trafficSticky_EN; + + // ports of submodule a4l_a4rdResp_fifof + wire [33 : 0] a4l_a4rdResp_fifof_D_IN, a4l_a4rdResp_fifof_D_OUT; + wire a4l_a4rdResp_fifof_CLR, + a4l_a4rdResp_fifof_DEQ, + a4l_a4rdResp_fifof_EMPTY_N, + a4l_a4rdResp_fifof_ENQ, + a4l_a4rdResp_fifof_FULL_N; + + // ports of submodule a4l_a4wrResp_fifof + wire [1 : 0] a4l_a4wrResp_fifof_D_IN; + wire a4l_a4wrResp_fifof_CLR, + a4l_a4wrResp_fifof_DEQ, + a4l_a4wrResp_fifof_EMPTY_N, + a4l_a4wrResp_fifof_ENQ, + a4l_a4wrResp_fifof_FULL_N; + + // ports of submodule wmemiM_respF + wire [130 : 0] wmemiM_respF_D_IN, wmemiM_respF_D_OUT; + wire wmemiM_respF_CLR, + wmemiM_respF_DEQ, + wmemiM_respF_EMPTY_N, + wmemiM_respF_ENQ, + wmemiM_respF_FULL_N; + + // ports of submodule wmemiS_dhF + wire [145 : 0] wmemiS_dhF_D_IN, wmemiS_dhF_D_OUT; + wire wmemiS_dhF_CLR, + wmemiS_dhF_DEQ, + wmemiS_dhF_EMPTY_N, + wmemiS_dhF_ENQ, + wmemiS_dhF_FULL_N; + + // ports of submodule wmemiS_reqF + wire [51 : 0] wmemiS_reqF_D_IN, wmemiS_reqF_D_OUT; + wire wmemiS_reqF_CLR, + wmemiS_reqF_DEQ, + wmemiS_reqF_EMPTY_N, + wmemiS_reqF_ENQ, + wmemiS_reqF_FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_axi_read_response, + WILL_FIRE_RL_a4l_a4rdAddr_fifof_both, + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr, + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr, + WILL_FIRE_RL_a4l_a4wrAddr_fifof_both, + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr, + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr, + WILL_FIRE_RL_a4l_a4wrData_fifof_both, + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr, + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr, + WILL_FIRE_RL_advance_request, + WILL_FIRE_RL_axi_read_response, + WILL_FIRE_RL_axi_write_response, + WILL_FIRE_RL_wmemiM_dhF_both, + WILL_FIRE_RL_wmemiM_dhF_decCtr, + WILL_FIRE_RL_wmemiM_dhF_incCtr, + WILL_FIRE_RL_wmemiM_reqF_both, + WILL_FIRE_RL_wmemiM_reqF_decCtr, + WILL_FIRE_RL_wmemiM_reqF_incCtr, + WILL_FIRE_RL_wmemiS_respF_both, + WILL_FIRE_RL_wmemiS_respF_decCtr, + WILL_FIRE_RL_wmemiS_respF_incCtr, + WILL_FIRE_RL_wmemi_response; + + // inputs to muxes for submodule ports + wire [145 : 0] MUX_wmemiM_dhF_q_0_write_1__VAL_1, + MUX_wmemiM_dhF_q_0_write_1__VAL_2, + MUX_wmemiM_dhF_q_1_write_1__VAL_2; + wire [130 : 0] MUX_wmemiS_respF_q_0_write_1__VAL_1, + MUX_wmemiS_respF_q_0_write_1__VAL_2, + MUX_wmemiS_respF_q_1_write_1__VAL_2, + MUX_wmemiS_respF_x_wire_wset_1__VAL_1, + MUX_wmemiS_respF_x_wire_wset_1__VAL_2; + wire [51 : 0] MUX_wmemiM_reqF_q_0_write_1__VAL_1, + MUX_wmemiM_reqF_q_0_write_1__VAL_2, + MUX_wmemiM_reqF_q_1_write_1__VAL_2; + wire [35 : 0] MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1, + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_2, + MUX_a4l_a4wrData_fifof_q_1_write_1__VAL_2; + wire [34 : 0] MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1, + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_2, + MUX_a4l_a4rdAddr_fifof_q_1_write_1__VAL_2, + MUX_a4l_a4wrAddr_fifof_q_0_write_1__VAL_2, + MUX_a4l_a4wrAddr_fifof_q_1_write_1__VAL_2; + wire [1 : 0] MUX_a4l_a4rdAddr_fifof_cntr_r_write_1__VAL_2, + MUX_a4l_a4wrAddr_fifof_cntr_r_write_1__VAL_2, + MUX_a4l_a4wrData_fifof_cntr_r_write_1__VAL_2, + MUX_wmemiM_dhF_cntr_r_write_1__VAL_2, + MUX_wmemiM_reqF_cntr_r_write_1__VAL_2, + MUX_wmemiS_respF_cntr_r_write_1__VAL_2; + wire MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_1, + MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_2, + MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_1, + MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_2, + MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_1, + MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_2, + MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_1, + MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_2, + MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_1, + MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_2, + MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_1, + MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_2, + MUX_axiActive_write_1__SEL_1, + MUX_wmemiM_dhF_q_0_write_1__SEL_1, + MUX_wmemiM_dhF_q_0_write_1__SEL_2, + MUX_wmemiM_dhF_q_1_write_1__SEL_1, + MUX_wmemiM_dhF_q_1_write_1__SEL_2, + MUX_wmemiM_reqF_q_0_write_1__SEL_1, + MUX_wmemiM_reqF_q_0_write_1__SEL_2, + MUX_wmemiM_reqF_q_1_write_1__SEL_1, + MUX_wmemiM_reqF_q_1_write_1__SEL_2, + MUX_wmemiS_respF_q_0_write_1__SEL_1, + MUX_wmemiS_respF_q_0_write_1__SEL_2, + MUX_wmemiS_respF_q_1_write_1__SEL_1, + MUX_wmemiS_respF_q_1_write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h10358, v__h10384, v__h10592, v__h10751; + wire [1 : 0] a4l_a4rdAddr_fifof_cntr_r_09_MINUS_1___d217, + a4l_a4wrAddr_fifof_cntr_r_49_MINUS_1___d157, + a4l_a4wrData_fifof_cntr_r_76_MINUS_1___d184, + wmemiM_dhF_cntr_r_1_MINUS_1___d100, + wmemiM_reqF_cntr_r_8_MINUS_1___d77, + wmemiS_respF_cntr_r_MINUS_1___d16; + wire IF_wmemiS_reqF_first__37_BITS_51_TO_49_39_EQ_1_ETC___d244, + IF_wmemiS_reqF_first__37_BIT_43_38_THEN_IF_wme_ETC___d250, + _dfoo1, + _dfoo11, + _dfoo13, + _dfoo15, + _dfoo17, + _dfoo19, + _dfoo21, + _dfoo23, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wmemiM_operateD_27_AND_wmemiM_peerIsReady_28_2_ETC___d248; + + // value method wmemiS0_sResp + assign wmemiS0_SResp = wmemiS_respF_q_0[130:129] ; + + // value method wmemiS0_sRespLast + assign wmemiS0_SRespLast = wmemiS_respF_q_0[128] ; + + // value method wmemiS0_sData + assign wmemiS0_SData = wmemiS_respF_q_0[127:0] ; + + // value method wmemiS0_sCmdAccept + assign wmemiS0_SCmdAccept = wmemiS_cmdAccept_w_whas ; + + // value method wmemiS0_sDataAccept + assign wmemiS0_SDataAccept = wmemiS_dhAccept_w_whas ; + + // value method wmemiM0_mCmd + assign wmemiM0_MCmd = wmemiM_reqF_q_0[51:49] ; + + // value method wmemiM0_mReqLast + assign wmemiM0_MReqLast = wmemiM_reqF_q_0[48] ; + + // value method wmemiM0_mAddr + assign wmemiM0_MAddr = wmemiM_reqF_q_0[47:12] ; + + // value method wmemiM0_mBurstLength + assign wmemiM0_MBurstLength = wmemiM_reqF_q_0[11:0] ; + + // value method wmemiM0_mDataValid + assign wmemiM0_MDataValid = wmemiM_dhF_q_0[145] ; + + // value method wmemiM0_mDataLast + assign wmemiM0_MDataLast = wmemiM_dhF_q_0[144] ; + + // value method wmemiM0_mData + assign wmemiM0_MData = wmemiM_dhF_q_0[143:16] ; + + // value method wmemiM0_mDataByteEn + assign wmemiM0_MDataByteEn = wmemiM_dhF_q_0[15:0] ; + + // value method wmemiM0_mReset_n + assign wmemiM0_MReset_n = !wmemiM_isReset_isInReset && wmemiM_operateD ; + + // value method axiM0_wrAddr_data + assign axiM0_wrAddr_data = a4l_a4wrAddr_fifof_q_0 ; + + // value method axiM0_wrAddr_valid + assign axiM0_wrAddr_valid = a4l_a4wrAddr_fifof_cntr_r != 2'd0 ; + + // value method axiM0_wrData_data + assign axiM0_wrData_data = a4l_a4wrData_fifof_q_0 ; + + // value method axiM0_wrData_valid + assign axiM0_wrData_valid = a4l_a4wrData_fifof_cntr_r != 2'd0 ; + + // value method axiM0_wrResp_ready + assign axiM0_wrResp_ready = a4l_a4wrResp_fifof_FULL_N ; + + // value method axiM0_rdAddr_data + assign axiM0_rdAddr_data = a4l_a4rdAddr_fifof_q_0 ; + + // value method axiM0_rdAddr_valid + assign axiM0_rdAddr_valid = a4l_a4rdAddr_fifof_cntr_r != 2'd0 ; + + // value method axiM0_rdResp_ready + assign axiM0_rdResp_ready = a4l_a4rdResp_fifof_FULL_N ; + + // submodule a4l_a4rdResp_fifof + FIFO2 #(.width(32'd34), .guarded(32'd1)) a4l_a4rdResp_fifof(.RST(RST_N), + .CLK(CLK), + .D_IN(a4l_a4rdResp_fifof_D_IN), + .ENQ(a4l_a4rdResp_fifof_ENQ), + .DEQ(a4l_a4rdResp_fifof_DEQ), + .CLR(a4l_a4rdResp_fifof_CLR), + .D_OUT(a4l_a4rdResp_fifof_D_OUT), + .FULL_N(a4l_a4rdResp_fifof_FULL_N), + .EMPTY_N(a4l_a4rdResp_fifof_EMPTY_N)); + + // submodule a4l_a4wrResp_fifof + FIFO2 #(.width(32'd2), .guarded(32'd1)) a4l_a4wrResp_fifof(.RST(RST_N), + .CLK(CLK), + .D_IN(a4l_a4wrResp_fifof_D_IN), + .ENQ(a4l_a4wrResp_fifof_ENQ), + .DEQ(a4l_a4wrResp_fifof_DEQ), + .CLR(a4l_a4wrResp_fifof_CLR), + .D_OUT(), + .FULL_N(a4l_a4wrResp_fifof_FULL_N), + .EMPTY_N(a4l_a4wrResp_fifof_EMPTY_N)); + + // submodule wmemiM_respF + FIFO2 #(.width(32'd131), .guarded(32'd1)) wmemiM_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wmemiM_respF_D_IN), + .ENQ(wmemiM_respF_ENQ), + .DEQ(wmemiM_respF_DEQ), + .CLR(wmemiM_respF_CLR), + .D_OUT(wmemiM_respF_D_OUT), + .FULL_N(wmemiM_respF_FULL_N), + .EMPTY_N(wmemiM_respF_EMPTY_N)); + + // submodule wmemiS_dhF + FIFO2 #(.width(32'd146), .guarded(32'd1)) wmemiS_dhF(.RST(RST_N), + .CLK(CLK), + .D_IN(wmemiS_dhF_D_IN), + .ENQ(wmemiS_dhF_ENQ), + .DEQ(wmemiS_dhF_DEQ), + .CLR(wmemiS_dhF_CLR), + .D_OUT(wmemiS_dhF_D_OUT), + .FULL_N(wmemiS_dhF_FULL_N), + .EMPTY_N(wmemiS_dhF_EMPTY_N)); + + // submodule wmemiS_reqF + FIFO2 #(.width(32'd52), .guarded(32'd1)) wmemiS_reqF(.RST(RST_N), + .CLK(CLK), + .D_IN(wmemiS_reqF_D_IN), + .ENQ(wmemiS_reqF_ENQ), + .DEQ(wmemiS_reqF_DEQ), + .CLR(wmemiS_reqF_CLR), + .D_OUT(wmemiS_reqF_D_OUT), + .FULL_N(wmemiS_reqF_FULL_N), + .EMPTY_N(wmemiS_reqF_EMPTY_N)); + + // rule RL_wmemi_response + assign WILL_FIRE_RL_wmemi_response = + wmemiS_respF_cntr_r != 2'd2 && wmemiS_operateD && + wmemiS_peerIsReady && + wmemiM_respF_EMPTY_N && + !axiActive ; + + // rule RL_axi_write_response + assign WILL_FIRE_RL_axi_write_response = + a4l_a4wrResp_fifof_EMPTY_N && axiActive ; + + // rule RL_axi_read_response + assign CAN_FIRE_RL_axi_read_response = + wmemiS_respF_cntr_r != 2'd2 && wmemiS_operateD && + wmemiS_peerIsReady && + a4l_a4rdResp_fifof_EMPTY_N && + axiActive ; + assign WILL_FIRE_RL_axi_read_response = + CAN_FIRE_RL_axi_read_response && + !WILL_FIRE_RL_axi_write_response ; + + // rule RL_wmemiS_respF_incCtr + assign WILL_FIRE_RL_wmemiS_respF_incCtr = + wmemiS_respF_x_wire_whas && wmemiS_respF_enqueueing_whas && + !(wmemiS_respF_cntr_r != 2'd0) ; + + // rule RL_wmemiS_respF_decCtr + assign WILL_FIRE_RL_wmemiS_respF_decCtr = + wmemiS_respF_cntr_r != 2'd0 && !wmemiS_respF_enqueueing_whas ; + + // rule RL_wmemiS_respF_both + assign WILL_FIRE_RL_wmemiS_respF_both = + wmemiS_respF_x_wire_whas && wmemiS_respF_cntr_r != 2'd0 && + wmemiS_respF_enqueueing_whas ; + + // rule RL_advance_request + assign WILL_FIRE_RL_advance_request = + wmemiS_operateD && wmemiS_peerIsReady && wmemiS_reqF_EMPTY_N && + IF_wmemiS_reqF_first__37_BIT_43_38_THEN_IF_wme_ETC___d250 && + !axiActive ; + + // rule RL_wmemiM_reqF_incCtr + assign WILL_FIRE_RL_wmemiM_reqF_incCtr = + wmemiM_reqF_enqueueing_whas && wmemiM_reqF_enqueueing_whas && + !wmemiM_reqF_dequeueing_whas ; + + // rule RL_wmemiM_reqF_decCtr + assign WILL_FIRE_RL_wmemiM_reqF_decCtr = + wmemiM_reqF_dequeueing_whas && !wmemiM_reqF_enqueueing_whas ; + + // rule RL_wmemiM_reqF_both + assign WILL_FIRE_RL_wmemiM_reqF_both = + wmemiM_reqF_enqueueing_whas && wmemiM_reqF_dequeueing_whas && + wmemiM_reqF_enqueueing_whas ; + + // rule RL_wmemiM_dhF_incCtr + assign WILL_FIRE_RL_wmemiM_dhF_incCtr = + wmemiM_dhF_enqueueing_whas && wmemiM_dhF_enqueueing_whas && + !wmemiM_dhF_dequeueing_whas ; + + // rule RL_wmemiM_dhF_decCtr + assign WILL_FIRE_RL_wmemiM_dhF_decCtr = + wmemiM_dhF_dequeueing_whas && !wmemiM_dhF_enqueueing_whas ; + + // rule RL_wmemiM_dhF_both + assign WILL_FIRE_RL_wmemiM_dhF_both = + wmemiM_dhF_enqueueing_whas && wmemiM_dhF_dequeueing_whas && + wmemiM_dhF_enqueueing_whas ; + + // rule RL_a4l_a4wrAddr_fifof_incCtr + assign WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr = + a4l_a4wrAddr_fifof_enqueueing_whas && + a4l_a4wrAddr_fifof_enqueueing_whas && + !a4l_a4wrAddr_fifof_dequeueing_whas ; + + // rule RL_a4l_a4wrAddr_fifof_decCtr + assign WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr = + a4l_a4wrAddr_fifof_dequeueing_whas && + !a4l_a4wrAddr_fifof_enqueueing_whas ; + + // rule RL_a4l_a4wrAddr_fifof_both + assign WILL_FIRE_RL_a4l_a4wrAddr_fifof_both = + a4l_a4wrAddr_fifof_enqueueing_whas && + a4l_a4wrAddr_fifof_dequeueing_whas && + a4l_a4wrAddr_fifof_enqueueing_whas ; + + // rule RL_a4l_a4wrData_fifof_incCtr + assign WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr = + a4l_a4wrAddr_fifof_enqueueing_whas && + a4l_a4wrAddr_fifof_enqueueing_whas && + !a4l_a4wrData_fifof_dequeueing_whas ; + + // rule RL_a4l_a4wrData_fifof_decCtr + assign WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr = + a4l_a4wrData_fifof_dequeueing_whas && + !a4l_a4wrAddr_fifof_enqueueing_whas ; + + // rule RL_a4l_a4wrData_fifof_both + assign WILL_FIRE_RL_a4l_a4wrData_fifof_both = + a4l_a4wrAddr_fifof_enqueueing_whas && + a4l_a4wrData_fifof_dequeueing_whas && + a4l_a4wrAddr_fifof_enqueueing_whas ; + + // rule RL_a4l_a4rdAddr_fifof_incCtr + assign WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr = + a4l_a4rdAddr_fifof_enqueueing_whas && + a4l_a4rdAddr_fifof_enqueueing_whas && + !a4l_a4rdAddr_fifof_dequeueing_whas ; + + // rule RL_a4l_a4rdAddr_fifof_decCtr + assign WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr = + a4l_a4rdAddr_fifof_dequeueing_whas && + !a4l_a4rdAddr_fifof_enqueueing_whas ; + + // rule RL_a4l_a4rdAddr_fifof_both + assign WILL_FIRE_RL_a4l_a4rdAddr_fifof_both = + a4l_a4rdAddr_fifof_enqueueing_whas && + a4l_a4rdAddr_fifof_dequeueing_whas && + a4l_a4rdAddr_fifof_enqueueing_whas ; + + // inputs to muxes for submodule ports + assign MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr && + a4l_a4rdAddr_fifof_cntr_r == 2'd0 ; + assign MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_both && _dfoo23 ; + assign MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr && + a4l_a4rdAddr_fifof_cntr_r == 2'd1 ; + assign MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_both && _dfoo21 ; + assign MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr && + a4l_a4wrAddr_fifof_cntr_r == 2'd0 ; + assign MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_both && _dfoo15 ; + assign MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr && + a4l_a4wrAddr_fifof_cntr_r == 2'd1 ; + assign MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_both && _dfoo13 ; + assign MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr && + a4l_a4wrData_fifof_cntr_r == 2'd0 ; + assign MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4wrData_fifof_both && _dfoo19 ; + assign MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr && + a4l_a4wrData_fifof_cntr_r == 2'd1 ; + assign MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4wrData_fifof_both && _dfoo17 ; + assign MUX_axiActive_write_1__SEL_1 = + WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] ; + assign MUX_wmemiM_dhF_q_0_write_1__SEL_1 = + WILL_FIRE_RL_wmemiM_dhF_incCtr && wmemiM_dhF_cntr_r == 2'd0 ; + assign MUX_wmemiM_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_dhF_both && _dfoo11 ; + assign MUX_wmemiM_dhF_q_1_write_1__SEL_1 = + WILL_FIRE_RL_wmemiM_dhF_incCtr && wmemiM_dhF_cntr_r == 2'd1 ; + assign MUX_wmemiM_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_dhF_both && _dfoo9 ; + assign MUX_wmemiM_reqF_q_0_write_1__SEL_1 = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 ; + assign MUX_wmemiM_reqF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_reqF_both && _dfoo7 ; + assign MUX_wmemiM_reqF_q_1_write_1__SEL_1 = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 ; + assign MUX_wmemiM_reqF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_reqF_both && _dfoo5 ; + assign MUX_wmemiS_respF_q_0_write_1__SEL_1 = + WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd0 ; + assign MUX_wmemiS_respF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemiS_respF_both && _dfoo3 ; + assign MUX_wmemiS_respF_q_1_write_1__SEL_1 = + WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd1 ; + assign MUX_wmemiS_respF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemiS_respF_both && _dfoo1 ; + assign MUX_a4l_a4rdAddr_fifof_cntr_r_write_1__VAL_2 = + a4l_a4rdAddr_fifof_cntr_r + 2'd1 ; + assign MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 = + { 3'd0, wmemiS_reqF_D_OUT[43:12] } ; + assign MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_2 = + (a4l_a4rdAddr_fifof_cntr_r == 2'd1) ? + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 : + a4l_a4rdAddr_fifof_q_1 ; + assign MUX_a4l_a4rdAddr_fifof_q_1_write_1__VAL_2 = + (a4l_a4rdAddr_fifof_cntr_r == 2'd2) ? + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 : + 35'd0 ; + assign MUX_a4l_a4wrAddr_fifof_cntr_r_write_1__VAL_2 = + a4l_a4wrAddr_fifof_cntr_r + 2'd1 ; + assign MUX_a4l_a4wrAddr_fifof_q_0_write_1__VAL_2 = + (a4l_a4wrAddr_fifof_cntr_r == 2'd1) ? + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 : + a4l_a4wrAddr_fifof_q_1 ; + assign MUX_a4l_a4wrAddr_fifof_q_1_write_1__VAL_2 = + (a4l_a4wrAddr_fifof_cntr_r == 2'd2) ? + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 : + 35'd0 ; + assign MUX_a4l_a4wrData_fifof_cntr_r_write_1__VAL_2 = + a4l_a4wrData_fifof_cntr_r + 2'd1 ; + assign MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 = + { wmemiS_dhF_D_OUT[3:0], wmemiS_dhF_D_OUT[47:16] } ; + assign MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_2 = + (a4l_a4wrData_fifof_cntr_r == 2'd1) ? + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 : + a4l_a4wrData_fifof_q_1 ; + assign MUX_a4l_a4wrData_fifof_q_1_write_1__VAL_2 = + (a4l_a4wrData_fifof_cntr_r == 2'd2) ? + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 : + 36'd0 ; + assign MUX_wmemiM_dhF_cntr_r_write_1__VAL_2 = wmemiM_dhF_cntr_r + 2'd1 ; + assign MUX_wmemiM_dhF_q_0_write_1__VAL_1 = + { 1'd1, wmemiS_dhF_D_OUT[144:0] } ; + assign MUX_wmemiM_dhF_q_0_write_1__VAL_2 = + (wmemiM_dhF_cntr_r == 2'd1) ? + MUX_wmemiM_dhF_q_0_write_1__VAL_1 : + wmemiM_dhF_q_1 ; + assign MUX_wmemiM_dhF_q_1_write_1__VAL_2 = + (wmemiM_dhF_cntr_r == 2'd2) ? + MUX_wmemiM_dhF_q_0_write_1__VAL_1 : + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign MUX_wmemiM_reqF_cntr_r_write_1__VAL_2 = wmemiM_reqF_cntr_r + 2'd1 ; + assign MUX_wmemiM_reqF_q_0_write_1__VAL_1 = + { (wmemiS_reqF_D_OUT[51:49] == 3'd1) ? + wmemiS_reqF_D_OUT[51:49] : + 3'd2, + 1'd1, + wmemiS_reqF_D_OUT[47:0] } ; + assign MUX_wmemiM_reqF_q_0_write_1__VAL_2 = + (wmemiM_reqF_cntr_r == 2'd1) ? + MUX_wmemiM_reqF_q_0_write_1__VAL_1 : + wmemiM_reqF_q_1 ; + assign MUX_wmemiM_reqF_q_1_write_1__VAL_2 = + (wmemiM_reqF_cntr_r == 2'd2) ? + MUX_wmemiM_reqF_q_0_write_1__VAL_1 : + 52'h0AAAAAAAAAAAA ; + assign MUX_wmemiS_respF_cntr_r_write_1__VAL_2 = wmemiS_respF_cntr_r + 2'd1 ; + assign MUX_wmemiS_respF_q_0_write_1__VAL_1 = + WILL_FIRE_RL_wmemi_response ? + MUX_wmemiS_respF_x_wire_wset_1__VAL_1 : + MUX_wmemiS_respF_x_wire_wset_1__VAL_2 ; + assign MUX_wmemiS_respF_q_0_write_1__VAL_2 = + (wmemiS_respF_cntr_r == 2'd1) ? + MUX_wmemiS_respF_q_0_write_1__VAL_1 : + wmemiS_respF_q_1 ; + assign MUX_wmemiS_respF_q_1_write_1__VAL_2 = + (wmemiS_respF_cntr_r == 2'd2) ? + MUX_wmemiS_respF_q_0_write_1__VAL_1 : + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign MUX_wmemiS_respF_x_wire_wset_1__VAL_1 = + { 2'd1, wmemiM_respF_D_OUT[128:0] } ; + assign MUX_wmemiS_respF_x_wire_wset_1__VAL_2 = + { 99'h3000000000000000000000000, + a4l_a4rdResp_fifof_D_OUT[31:0] } ; + + // inlined wires + assign wmemiS_wmemiReq_wget = + { wmemiS0_MCmd, + wmemiS0_MReqLast, + wmemiS0_MAddr, + wmemiS0_MBurstLength } ; + assign wmemiS_wmemiReq_whas = 1'd1 ; + assign wmemiS_wmemiDh_wget = + { wmemiS0_MDataValid, + wmemiS0_MDataLast, + wmemiS0_MData, + wmemiS0_MDataByteEn } ; + assign wmemiS_wmemiDh_whas = 1'd1 ; + assign wmemiS_cmdAccept_w_wget = 1'd1 ; + assign wmemiS_cmdAccept_w_whas = + wmemiS_reqF_FULL_N && wmemiS_operateD && wmemiS_peerIsReady && + wmemiS_wmemiReq_wget[51:49] != 3'd0 && + wmemiS_reqF_FULL_N ; + assign wmemiS_dhAccept_w_wget = 1'd1 ; + assign wmemiS_dhAccept_w_whas = + wmemiS_dhF_FULL_N && wmemiS_operateD && wmemiS_peerIsReady && + wmemiS_wmemiDh_wget[145] && + wmemiS_dhF_FULL_N ; + assign wmemiS_respF_x_wire_wget = MUX_wmemiS_respF_q_0_write_1__VAL_1 ; + assign wmemiS_respF_x_wire_whas = + WILL_FIRE_RL_wmemi_response || WILL_FIRE_RL_axi_read_response ; + assign wmemiS_operateD_1_wget = 1'd1 ; + assign wmemiS_operateD_1_whas = 1'd1 ; + assign wmemiS_peerIsReady_1_wget = 1'd1 ; + assign wmemiS_peerIsReady_1_whas = wmemiS0_MReset_n ; + assign wmemiM_reqF_x_wire_wget = MUX_wmemiM_reqF_q_0_write_1__VAL_1 ; + assign wmemiM_reqF_x_wire_whas = wmemiM_reqF_enqueueing_whas ; + assign wmemiM_dhF_x_wire_wget = MUX_wmemiM_dhF_q_0_write_1__VAL_1 ; + assign wmemiM_dhF_x_wire_whas = wmemiM_dhF_enqueueing_whas ; + assign wmemiM_wmemiResponse_wget = + { wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ; + assign wmemiM_wmemiResponse_whas = 1'd1 ; + assign wmemiM_sCmdAccept_w_wget = 1'd1 ; + assign wmemiM_sCmdAccept_w_whas = wmemiM0_SCmdAccept ; + assign wmemiM_sDataAccept_w_wget = 1'd1 ; + assign wmemiM_sDataAccept_w_whas = wmemiM0_SDataAccept ; + assign wmemiM_operateD_1_wget = 1'd1 ; + assign wmemiM_operateD_1_whas = 1'd1 ; + assign wmemiM_peerIsReady_1_wget = 1'b0 ; + assign wmemiM_peerIsReady_1_whas = 1'b0 ; + assign a4l_a4wrAddr_fifof_x_wire_wget = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 ; + assign a4l_a4wrAddr_fifof_x_wire_whas = a4l_a4wrAddr_fifof_enqueueing_whas ; + assign a4l_a4wrData_fifof_x_wire_wget = + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 ; + assign a4l_a4wrData_fifof_x_wire_whas = a4l_a4wrAddr_fifof_enqueueing_whas ; + assign a4l_a4rdAddr_fifof_x_wire_wget = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 ; + assign a4l_a4rdAddr_fifof_x_wire_whas = a4l_a4rdAddr_fifof_enqueueing_whas ; + assign wmemi_Es_mCmd_w_wget = wmemiS0_MCmd ; + assign wmemi_Es_mCmd_w_whas = 1'd1 ; + assign wmemi_Es_mAddr_w_wget = wmemiS0_MAddr ; + assign wmemi_Es_mAddr_w_whas = 1'd1 ; + assign wmemi_Es_mBurstLength_w_wget = wmemiS0_MBurstLength ; + assign wmemi_Es_mBurstLength_w_whas = 1'd1 ; + assign wmemi_Es_mData_w_wget = wmemiS0_MData ; + assign wmemi_Es_mData_w_whas = 1'd1 ; + assign wmemi_Es_mDataByteEn_w_wget = wmemiS0_MDataByteEn ; + assign wmemi_Es_mDataByteEn_w_whas = 1'd1 ; + assign wmemi_Em_sResp_w_wget = wmemiM0_SResp ; + assign wmemi_Em_sResp_w_whas = 1'd1 ; + assign wmemi_Em_sData_w_wget = wmemiM0_SData ; + assign wmemi_Em_sData_w_whas = 1'd1 ; + assign wmemiS_respF_enqueueing_whas = + WILL_FIRE_RL_axi_read_response || WILL_FIRE_RL_wmemi_response ; + assign wmemiS_respF_dequeueing_whas = wmemiS_respF_cntr_r != 2'd0 ; + assign wmemiM_reqF_enqueueing_whas = + WILL_FIRE_RL_advance_request && !wmemiS_reqF_D_OUT[43] ; + assign wmemiM_reqF_dequeueing_whas = + wmemiM0_SCmdAccept && wmemiM_reqF_cntr_r != 2'd0 ; + assign wmemiM_dhF_enqueueing_whas = + WILL_FIRE_RL_advance_request && !wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] == 3'd1 ; + assign wmemiM_dhF_dequeueing_whas = + wmemiM0_SDataAccept && wmemiM_dhF_cntr_r != 2'd0 ; + assign a4l_a4wrAddr_fifof_enqueueing_whas = + WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] == 3'd1 ; + assign a4l_a4wrAddr_fifof_dequeueing_whas = + a4l_a4wrAddr_fifof_cntr_r != 2'd0 && axiM0_wrAddr_ready_value ; + assign a4l_a4wrAddr_deq_ready_whas = axiM0_wrAddr_ready_value ; + assign a4l_a4wrAddr_deq_deq_whas = 1'b0 ; + assign a4l_a4wrData_fifof_enqueueing_whas = + a4l_a4wrAddr_fifof_enqueueing_whas ; + assign a4l_a4wrData_fifof_dequeueing_whas = + a4l_a4wrData_fifof_cntr_r != 2'd0 && axiM0_wrData_ready_value ; + assign a4l_a4wrData_deq_ready_whas = axiM0_wrData_ready_value ; + assign a4l_a4wrData_deq_deq_whas = 1'b0 ; + assign a4l_a4wrResp_enq_valid_whas = axiM0_wrResp_valid_value ; + assign a4l_a4wrResp_enq_enq_whas = 1'b0 ; + assign a4l_a4rdAddr_fifof_enqueueing_whas = + WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] != 3'd1 ; + assign a4l_a4rdAddr_fifof_dequeueing_whas = + a4l_a4rdAddr_fifof_cntr_r != 2'd0 && axiM0_rdAddr_ready_value ; + assign a4l_a4rdAddr_deq_ready_whas = axiM0_rdAddr_ready_value ; + assign a4l_a4rdAddr_deq_deq_whas = 1'b0 ; + assign a4l_a4rdResp_enq_valid_whas = axiM0_rdResp_valid_value ; + assign a4l_a4rdResp_enq_enq_whas = 1'b0 ; + assign wmemi_Es_mReqLast_w_whas = wmemiS0_MReqLast ; + assign wmemi_Es_mDataValid_w_whas = wmemiS0_MDataValid ; + assign wmemi_Es_mDataLast_w_whas = wmemiS0_MDataLast ; + assign wmemi_Em_sRespLast_w_whas = wmemiM0_SRespLast ; + assign a4l_a4wrResp_data_wire_wget = axiM0_wrResp_data_value ; + assign a4l_a4rdResp_data_wire_wget = axiM0_rdResp_data_value ; + + // register a4l_a4rdAddr_fifof_cntr_r + assign a4l_a4rdAddr_fifof_cntr_r_D_IN = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr ? + a4l_a4rdAddr_fifof_cntr_r_09_MINUS_1___d217 : + MUX_a4l_a4rdAddr_fifof_cntr_r_write_1__VAL_2 ; + assign a4l_a4rdAddr_fifof_cntr_r_EN = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr || + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr ; + + // register a4l_a4rdAddr_fifof_q_0 + always@(MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_1 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_2 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr or a4l_a4rdAddr_fifof_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_1: + a4l_a4rdAddr_fifof_q_0_D_IN = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4rdAddr_fifof_q_0_write_1__SEL_2: + a4l_a4rdAddr_fifof_q_0_D_IN = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr: + a4l_a4rdAddr_fifof_q_0_D_IN = a4l_a4rdAddr_fifof_q_1; + default: a4l_a4rdAddr_fifof_q_0_D_IN = + 35'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4rdAddr_fifof_q_0_EN = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr && + a4l_a4rdAddr_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_a4l_a4rdAddr_fifof_both && _dfoo23 || + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr ; + + // register a4l_a4rdAddr_fifof_q_1 + always@(MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_1 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_2 or + MUX_a4l_a4rdAddr_fifof_q_1_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_1: + a4l_a4rdAddr_fifof_q_1_D_IN = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4rdAddr_fifof_q_1_write_1__SEL_2: + a4l_a4rdAddr_fifof_q_1_D_IN = + MUX_a4l_a4rdAddr_fifof_q_1_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr: + a4l_a4rdAddr_fifof_q_1_D_IN = 35'd0; + default: a4l_a4rdAddr_fifof_q_1_D_IN = + 35'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4rdAddr_fifof_q_1_EN = + WILL_FIRE_RL_a4l_a4rdAddr_fifof_incCtr && + a4l_a4rdAddr_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_a4l_a4rdAddr_fifof_both && _dfoo21 || + WILL_FIRE_RL_a4l_a4rdAddr_fifof_decCtr ; + + // register a4l_a4wrAddr_fifof_cntr_r + assign a4l_a4wrAddr_fifof_cntr_r_D_IN = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr ? + a4l_a4wrAddr_fifof_cntr_r_49_MINUS_1___d157 : + MUX_a4l_a4wrAddr_fifof_cntr_r_write_1__VAL_2 ; + assign a4l_a4wrAddr_fifof_cntr_r_EN = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr || + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr ; + + // register a4l_a4wrAddr_fifof_q_0 + always@(MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_1 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_2 or + MUX_a4l_a4wrAddr_fifof_q_0_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr or a4l_a4wrAddr_fifof_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_1: + a4l_a4wrAddr_fifof_q_0_D_IN = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4wrAddr_fifof_q_0_write_1__SEL_2: + a4l_a4wrAddr_fifof_q_0_D_IN = + MUX_a4l_a4wrAddr_fifof_q_0_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr: + a4l_a4wrAddr_fifof_q_0_D_IN = a4l_a4wrAddr_fifof_q_1; + default: a4l_a4wrAddr_fifof_q_0_D_IN = + 35'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4wrAddr_fifof_q_0_EN = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr && + a4l_a4wrAddr_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_a4l_a4wrAddr_fifof_both && _dfoo15 || + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr ; + + // register a4l_a4wrAddr_fifof_q_1 + always@(MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_1 or + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_2 or + MUX_a4l_a4wrAddr_fifof_q_1_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_1: + a4l_a4wrAddr_fifof_q_1_D_IN = + MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4wrAddr_fifof_q_1_write_1__SEL_2: + a4l_a4wrAddr_fifof_q_1_D_IN = + MUX_a4l_a4wrAddr_fifof_q_1_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr: + a4l_a4wrAddr_fifof_q_1_D_IN = 35'd0; + default: a4l_a4wrAddr_fifof_q_1_D_IN = + 35'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4wrAddr_fifof_q_1_EN = + WILL_FIRE_RL_a4l_a4wrAddr_fifof_incCtr && + a4l_a4wrAddr_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_a4l_a4wrAddr_fifof_both && _dfoo13 || + WILL_FIRE_RL_a4l_a4wrAddr_fifof_decCtr ; + + // register a4l_a4wrData_fifof_cntr_r + assign a4l_a4wrData_fifof_cntr_r_D_IN = + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr ? + a4l_a4wrData_fifof_cntr_r_76_MINUS_1___d184 : + MUX_a4l_a4wrData_fifof_cntr_r_write_1__VAL_2 ; + assign a4l_a4wrData_fifof_cntr_r_EN = + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr || + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr ; + + // register a4l_a4wrData_fifof_q_0 + always@(MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_1 or + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_2 or + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr or a4l_a4wrData_fifof_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_1: + a4l_a4wrData_fifof_q_0_D_IN = + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4wrData_fifof_q_0_write_1__SEL_2: + a4l_a4wrData_fifof_q_0_D_IN = + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr: + a4l_a4wrData_fifof_q_0_D_IN = a4l_a4wrData_fifof_q_1; + default: a4l_a4wrData_fifof_q_0_D_IN = + 36'hAAAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4wrData_fifof_q_0_EN = + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr && + a4l_a4wrData_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_a4l_a4wrData_fifof_both && _dfoo19 || + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr ; + + // register a4l_a4wrData_fifof_q_1 + always@(MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_1 or + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_2 or + MUX_a4l_a4wrData_fifof_q_1_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_1: + a4l_a4wrData_fifof_q_1_D_IN = + MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4wrData_fifof_q_1_write_1__SEL_2: + a4l_a4wrData_fifof_q_1_D_IN = + MUX_a4l_a4wrData_fifof_q_1_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr: + a4l_a4wrData_fifof_q_1_D_IN = 36'd0; + default: a4l_a4wrData_fifof_q_1_D_IN = + 36'hAAAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4wrData_fifof_q_1_EN = + WILL_FIRE_RL_a4l_a4wrData_fifof_incCtr && + a4l_a4wrData_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_a4l_a4wrData_fifof_both && _dfoo17 || + WILL_FIRE_RL_a4l_a4wrData_fifof_decCtr ; + + // register axiActive + assign axiActive_D_IN = MUX_axiActive_write_1__SEL_1 ; + assign axiActive_EN = + WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] || + WILL_FIRE_RL_axi_read_response || + WILL_FIRE_RL_axi_write_response ; + + // register wmemiM_busyWithMessage + assign wmemiM_busyWithMessage_D_IN = 1'b0 ; + assign wmemiM_busyWithMessage_EN = 1'b0 ; + + // register wmemiM_dhF_cntr_r + assign wmemiM_dhF_cntr_r_D_IN = + WILL_FIRE_RL_wmemiM_dhF_decCtr ? + wmemiM_dhF_cntr_r_1_MINUS_1___d100 : + MUX_wmemiM_dhF_cntr_r_write_1__VAL_2 ; + assign wmemiM_dhF_cntr_r_EN = + WILL_FIRE_RL_wmemiM_dhF_decCtr || + WILL_FIRE_RL_wmemiM_dhF_incCtr ; + + // register wmemiM_dhF_q_0 + always@(MUX_wmemiM_dhF_q_0_write_1__SEL_1 or + MUX_wmemiM_dhF_q_0_write_1__VAL_1 or + MUX_wmemiM_dhF_q_0_write_1__SEL_2 or + MUX_wmemiM_dhF_q_0_write_1__VAL_2 or + WILL_FIRE_RL_wmemiM_dhF_decCtr or wmemiM_dhF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiM_dhF_q_0_write_1__SEL_1: + wmemiM_dhF_q_0_D_IN = MUX_wmemiM_dhF_q_0_write_1__VAL_1; + MUX_wmemiM_dhF_q_0_write_1__SEL_2: + wmemiM_dhF_q_0_D_IN = MUX_wmemiM_dhF_q_0_write_1__VAL_2; + WILL_FIRE_RL_wmemiM_dhF_decCtr: wmemiM_dhF_q_0_D_IN = wmemiM_dhF_q_1; + default: wmemiM_dhF_q_0_D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiM_dhF_q_0_EN = + WILL_FIRE_RL_wmemiM_dhF_incCtr && wmemiM_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemiM_dhF_both && _dfoo11 || + WILL_FIRE_RL_wmemiM_dhF_decCtr ; + + // register wmemiM_dhF_q_1 + always@(MUX_wmemiM_dhF_q_1_write_1__SEL_1 or + MUX_wmemiM_dhF_q_0_write_1__VAL_1 or + MUX_wmemiM_dhF_q_1_write_1__SEL_2 or + MUX_wmemiM_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmemiM_dhF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiM_dhF_q_1_write_1__SEL_1: + wmemiM_dhF_q_1_D_IN = MUX_wmemiM_dhF_q_0_write_1__VAL_1; + MUX_wmemiM_dhF_q_1_write_1__SEL_2: + wmemiM_dhF_q_1_D_IN = MUX_wmemiM_dhF_q_1_write_1__VAL_2; + WILL_FIRE_RL_wmemiM_dhF_decCtr: + wmemiM_dhF_q_1_D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + default: wmemiM_dhF_q_1_D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiM_dhF_q_1_EN = + WILL_FIRE_RL_wmemiM_dhF_incCtr && wmemiM_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemiM_dhF_both && _dfoo9 || + WILL_FIRE_RL_wmemiM_dhF_decCtr ; + + // register wmemiM_errorSticky + assign wmemiM_errorSticky_D_IN = 1'b0 ; + assign wmemiM_errorSticky_EN = 1'b0 ; + + // register wmemiM_isReset_isInReset + assign wmemiM_isReset_isInReset_D_IN = 1'd0 ; + assign wmemiM_isReset_isInReset_EN = wmemiM_isReset_isInReset ; + + // register wmemiM_operateD + assign wmemiM_operateD_D_IN = 1'b1 ; + assign wmemiM_operateD_EN = 1'd1 ; + + // register wmemiM_peerIsReady + assign wmemiM_peerIsReady_D_IN = 1'b1 ; + assign wmemiM_peerIsReady_EN = 1'd1 ; + + // register wmemiM_reqF_cntr_r + assign wmemiM_reqF_cntr_r_D_IN = + WILL_FIRE_RL_wmemiM_reqF_decCtr ? + wmemiM_reqF_cntr_r_8_MINUS_1___d77 : + MUX_wmemiM_reqF_cntr_r_write_1__VAL_2 ; + assign wmemiM_reqF_cntr_r_EN = + WILL_FIRE_RL_wmemiM_reqF_decCtr || + WILL_FIRE_RL_wmemiM_reqF_incCtr ; + + // register wmemiM_reqF_q_0 + always@(MUX_wmemiM_reqF_q_0_write_1__SEL_1 or + MUX_wmemiM_reqF_q_0_write_1__VAL_1 or + MUX_wmemiM_reqF_q_0_write_1__SEL_2 or + MUX_wmemiM_reqF_q_0_write_1__VAL_2 or + WILL_FIRE_RL_wmemiM_reqF_decCtr or wmemiM_reqF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiM_reqF_q_0_write_1__SEL_1: + wmemiM_reqF_q_0_D_IN = MUX_wmemiM_reqF_q_0_write_1__VAL_1; + MUX_wmemiM_reqF_q_0_write_1__SEL_2: + wmemiM_reqF_q_0_D_IN = MUX_wmemiM_reqF_q_0_write_1__VAL_2; + WILL_FIRE_RL_wmemiM_reqF_decCtr: wmemiM_reqF_q_0_D_IN = wmemiM_reqF_q_1; + default: wmemiM_reqF_q_0_D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiM_reqF_q_0_EN = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemiM_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmemiM_reqF_decCtr ; + + // register wmemiM_reqF_q_1 + always@(MUX_wmemiM_reqF_q_1_write_1__SEL_1 or + MUX_wmemiM_reqF_q_0_write_1__VAL_1 or + MUX_wmemiM_reqF_q_1_write_1__SEL_2 or + MUX_wmemiM_reqF_q_1_write_1__VAL_2 or + WILL_FIRE_RL_wmemiM_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiM_reqF_q_1_write_1__SEL_1: + wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_0_write_1__VAL_1; + MUX_wmemiM_reqF_q_1_write_1__SEL_2: + wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_1_write_1__VAL_2; + WILL_FIRE_RL_wmemiM_reqF_decCtr: + wmemiM_reqF_q_1_D_IN = 52'h0AAAAAAAAAAAA; + default: wmemiM_reqF_q_1_D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiM_reqF_q_1_EN = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemiM_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmemiM_reqF_decCtr ; + + // register wmemiM_statusR + assign wmemiM_statusR_D_IN = + { wmemiM_isReset_isInReset, + !wmemiM_peerIsReady, + !wmemiM_operateD, + wmemiM_errorSticky, + 3'd0, + wmemiM_trafficSticky } ; + assign wmemiM_statusR_EN = 1'd1 ; + + // register wmemiM_trafficSticky + assign wmemiM_trafficSticky_D_IN = 1'd1 ; + assign wmemiM_trafficSticky_EN = wmemiM0_SCmdAccept ; + + // register wmemiS_errorSticky + assign wmemiS_errorSticky_D_IN = 1'b0 ; + assign wmemiS_errorSticky_EN = 1'b0 ; + + // register wmemiS_isReset_isInReset + assign wmemiS_isReset_isInReset_D_IN = 1'd0 ; + assign wmemiS_isReset_isInReset_EN = wmemiS_isReset_isInReset ; + + // register wmemiS_operateD + assign wmemiS_operateD_D_IN = 1'b1 ; + assign wmemiS_operateD_EN = 1'd1 ; + + // register wmemiS_peerIsReady + assign wmemiS_peerIsReady_D_IN = wmemiS0_MReset_n ; + assign wmemiS_peerIsReady_EN = 1'd1 ; + + // register wmemiS_respF_cntr_r + assign wmemiS_respF_cntr_r_D_IN = + WILL_FIRE_RL_wmemiS_respF_decCtr ? + wmemiS_respF_cntr_r_MINUS_1___d16 : + MUX_wmemiS_respF_cntr_r_write_1__VAL_2 ; + assign wmemiS_respF_cntr_r_EN = + WILL_FIRE_RL_wmemiS_respF_decCtr || + WILL_FIRE_RL_wmemiS_respF_incCtr ; + + // register wmemiS_respF_q_0 + always@(MUX_wmemiS_respF_q_0_write_1__SEL_1 or + MUX_wmemiS_respF_q_0_write_1__VAL_1 or + MUX_wmemiS_respF_q_0_write_1__SEL_2 or + MUX_wmemiS_respF_q_0_write_1__VAL_2 or + WILL_FIRE_RL_wmemiS_respF_decCtr or wmemiS_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiS_respF_q_0_write_1__SEL_1: + wmemiS_respF_q_0_D_IN = MUX_wmemiS_respF_q_0_write_1__VAL_1; + MUX_wmemiS_respF_q_0_write_1__SEL_2: + wmemiS_respF_q_0_D_IN = MUX_wmemiS_respF_q_0_write_1__VAL_2; + WILL_FIRE_RL_wmemiS_respF_decCtr: + wmemiS_respF_q_0_D_IN = wmemiS_respF_q_1; + default: wmemiS_respF_q_0_D_IN = + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiS_respF_q_0_EN = + WILL_FIRE_RL_wmemiS_respF_incCtr && + wmemiS_respF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemiS_respF_both && _dfoo3 || + WILL_FIRE_RL_wmemiS_respF_decCtr ; + + // register wmemiS_respF_q_1 + always@(MUX_wmemiS_respF_q_1_write_1__SEL_1 or + MUX_wmemiS_respF_q_0_write_1__VAL_1 or + MUX_wmemiS_respF_q_1_write_1__SEL_2 or + MUX_wmemiS_respF_q_1_write_1__VAL_2 or + WILL_FIRE_RL_wmemiS_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemiS_respF_q_1_write_1__SEL_1: + wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_0_write_1__VAL_1; + MUX_wmemiS_respF_q_1_write_1__SEL_2: + wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_1_write_1__VAL_2; + WILL_FIRE_RL_wmemiS_respF_decCtr: + wmemiS_respF_q_1_D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + default: wmemiS_respF_q_1_D_IN = + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemiS_respF_q_1_EN = + WILL_FIRE_RL_wmemiS_respF_incCtr && + wmemiS_respF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemiS_respF_both && _dfoo1 || + WILL_FIRE_RL_wmemiS_respF_decCtr ; + + // register wmemiS_statusR + assign wmemiS_statusR_D_IN = + { wmemiS_isReset_isInReset, + !wmemiS_peerIsReady, + !wmemiS_operateD, + wmemiS_errorSticky, + 3'd0, + wmemiS_trafficSticky } ; + assign wmemiS_statusR_EN = 1'd1 ; + + // register wmemiS_trafficSticky + assign wmemiS_trafficSticky_D_IN = 1'd1 ; + assign wmemiS_trafficSticky_EN = wmemiS_cmdAccept_w_whas ; + + // submodule a4l_a4rdResp_fifof + assign a4l_a4rdResp_fifof_D_IN = axiM0_rdResp_data_value ; + assign a4l_a4rdResp_fifof_ENQ = + a4l_a4rdResp_fifof_FULL_N && axiM0_rdResp_valid_value ; + assign a4l_a4rdResp_fifof_DEQ = WILL_FIRE_RL_axi_read_response ; + assign a4l_a4rdResp_fifof_CLR = 1'b0 ; + + // submodule a4l_a4wrResp_fifof + assign a4l_a4wrResp_fifof_D_IN = axiM0_wrResp_data_value ; + assign a4l_a4wrResp_fifof_ENQ = + a4l_a4wrResp_fifof_FULL_N && axiM0_wrResp_valid_value ; + assign a4l_a4wrResp_fifof_DEQ = WILL_FIRE_RL_axi_write_response ; + assign a4l_a4wrResp_fifof_CLR = 1'b0 ; + + // submodule wmemiM_respF + assign wmemiM_respF_D_IN = wmemiM_wmemiResponse_wget ; + assign wmemiM_respF_ENQ = + wmemiM_respF_FULL_N && wmemiM_operateD && wmemiM_peerIsReady && + wmemiM_wmemiResponse_wget[130:129] != 2'd0 ; + assign wmemiM_respF_DEQ = WILL_FIRE_RL_wmemi_response ; + assign wmemiM_respF_CLR = 1'b0 ; + + // submodule wmemiS_dhF + assign wmemiS_dhF_D_IN = wmemiS_wmemiDh_wget ; + assign wmemiS_dhF_ENQ = wmemiS_dhAccept_w_whas ; + assign wmemiS_dhF_DEQ = + WILL_FIRE_RL_advance_request && + wmemiS_reqF_D_OUT[51:49] == 3'd1 ; + assign wmemiS_dhF_CLR = 1'b0 ; + + // submodule wmemiS_reqF + assign wmemiS_reqF_D_IN = wmemiS_wmemiReq_wget ; + assign wmemiS_reqF_ENQ = wmemiS_cmdAccept_w_whas ; + assign wmemiS_reqF_DEQ = WILL_FIRE_RL_advance_request ; + assign wmemiS_reqF_CLR = 1'b0 ; + + // remaining internal signals + assign IF_wmemiS_reqF_first__37_BITS_51_TO_49_39_EQ_1_ETC___d244 = + (wmemiS_reqF_D_OUT[51:49] == 3'd1) ? + a4l_a4wrAddr_fifof_cntr_r != 2'd2 && + a4l_a4wrData_fifof_cntr_r != 2'd2 && + wmemiS_dhF_EMPTY_N : + a4l_a4rdAddr_fifof_cntr_r != 2'd2 ; + assign IF_wmemiS_reqF_first__37_BIT_43_38_THEN_IF_wme_ETC___d250 = + wmemiS_reqF_D_OUT[43] ? + IF_wmemiS_reqF_first__37_BITS_51_TO_49_39_EQ_1_ETC___d244 : + wmemiM_reqF_cntr_r != 2'd2 && + wmemiM_operateD_27_AND_wmemiM_peerIsReady_28_2_ETC___d248 ; + assign _dfoo1 = + wmemiS_respF_cntr_r != 2'd2 || + wmemiS_respF_cntr_r_MINUS_1___d16 == 2'd1 ; + assign _dfoo11 = + wmemiM_dhF_cntr_r != 2'd1 || + wmemiM_dhF_cntr_r_1_MINUS_1___d100 == 2'd0 ; + assign _dfoo13 = + a4l_a4wrAddr_fifof_cntr_r != 2'd2 || + a4l_a4wrAddr_fifof_cntr_r_49_MINUS_1___d157 == 2'd1 ; + assign _dfoo15 = + a4l_a4wrAddr_fifof_cntr_r != 2'd1 || + a4l_a4wrAddr_fifof_cntr_r_49_MINUS_1___d157 == 2'd0 ; + assign _dfoo17 = + a4l_a4wrData_fifof_cntr_r != 2'd2 || + a4l_a4wrData_fifof_cntr_r_76_MINUS_1___d184 == 2'd1 ; + assign _dfoo19 = + a4l_a4wrData_fifof_cntr_r != 2'd1 || + a4l_a4wrData_fifof_cntr_r_76_MINUS_1___d184 == 2'd0 ; + assign _dfoo21 = + a4l_a4rdAddr_fifof_cntr_r != 2'd2 || + a4l_a4rdAddr_fifof_cntr_r_09_MINUS_1___d217 == 2'd1 ; + assign _dfoo23 = + a4l_a4rdAddr_fifof_cntr_r != 2'd1 || + a4l_a4rdAddr_fifof_cntr_r_09_MINUS_1___d217 == 2'd0 ; + assign _dfoo3 = + wmemiS_respF_cntr_r != 2'd1 || + wmemiS_respF_cntr_r_MINUS_1___d16 == 2'd0 ; + assign _dfoo5 = + wmemiM_reqF_cntr_r != 2'd2 || + wmemiM_reqF_cntr_r_8_MINUS_1___d77 == 2'd1 ; + assign _dfoo7 = + wmemiM_reqF_cntr_r != 2'd1 || + wmemiM_reqF_cntr_r_8_MINUS_1___d77 == 2'd0 ; + assign _dfoo9 = + wmemiM_dhF_cntr_r != 2'd2 || + wmemiM_dhF_cntr_r_1_MINUS_1___d100 == 2'd1 ; + assign a4l_a4rdAddr_fifof_cntr_r_09_MINUS_1___d217 = + a4l_a4rdAddr_fifof_cntr_r - 2'd1 ; + assign a4l_a4wrAddr_fifof_cntr_r_49_MINUS_1___d157 = + a4l_a4wrAddr_fifof_cntr_r - 2'd1 ; + assign a4l_a4wrData_fifof_cntr_r_76_MINUS_1___d184 = + a4l_a4wrData_fifof_cntr_r - 2'd1 ; + assign wmemiM_dhF_cntr_r_1_MINUS_1___d100 = wmemiM_dhF_cntr_r - 2'd1 ; + assign wmemiM_operateD_27_AND_wmemiM_peerIsReady_28_2_ETC___d248 = + wmemiM_operateD && wmemiM_peerIsReady && + (wmemiS_reqF_D_OUT[51:49] != 3'd1 || + wmemiM_dhF_cntr_r != 2'd2 && wmemiS_dhF_EMPTY_N) ; + assign wmemiM_reqF_cntr_r_8_MINUS_1___d77 = wmemiM_reqF_cntr_r - 2'd1 ; + assign wmemiS_respF_cntr_r_MINUS_1___d16 = wmemiS_respF_cntr_r - 2'd1 ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + a4l_a4rdAddr_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4rdAddr_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 35'd0; + a4l_a4rdAddr_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 35'd0; + a4l_a4wrAddr_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4wrAddr_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 35'd0; + a4l_a4wrAddr_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 35'd0; + a4l_a4wrData_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4wrData_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 36'd0; + a4l_a4wrData_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 36'd0; + axiActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiM_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiM_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemiM_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiM_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd1; + wmemiM_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemiM_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA; + wmemiM_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA; + wmemiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemiS_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemiS_respF_q_0 <= `BSV_ASSIGNMENT_DELAY + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiS_respF_q_1 <= `BSV_ASSIGNMENT_DELAY + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (a4l_a4rdAddr_fifof_cntr_r_EN) + a4l_a4rdAddr_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdAddr_fifof_cntr_r_D_IN; + if (a4l_a4rdAddr_fifof_q_0_EN) + a4l_a4rdAddr_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdAddr_fifof_q_0_D_IN; + if (a4l_a4rdAddr_fifof_q_1_EN) + a4l_a4rdAddr_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdAddr_fifof_q_1_D_IN; + if (a4l_a4wrAddr_fifof_cntr_r_EN) + a4l_a4wrAddr_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrAddr_fifof_cntr_r_D_IN; + if (a4l_a4wrAddr_fifof_q_0_EN) + a4l_a4wrAddr_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrAddr_fifof_q_0_D_IN; + if (a4l_a4wrAddr_fifof_q_1_EN) + a4l_a4wrAddr_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrAddr_fifof_q_1_D_IN; + if (a4l_a4wrData_fifof_cntr_r_EN) + a4l_a4wrData_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrData_fifof_cntr_r_D_IN; + if (a4l_a4wrData_fifof_q_0_EN) + a4l_a4wrData_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrData_fifof_q_0_D_IN; + if (a4l_a4wrData_fifof_q_1_EN) + a4l_a4wrData_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrData_fifof_q_1_D_IN; + if (axiActive_EN) axiActive <= `BSV_ASSIGNMENT_DELAY axiActive_D_IN; + if (wmemiM_busyWithMessage_EN) + wmemiM_busyWithMessage <= `BSV_ASSIGNMENT_DELAY + wmemiM_busyWithMessage_D_IN; + if (wmemiM_dhF_cntr_r_EN) + wmemiM_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemiM_dhF_cntr_r_D_IN; + if (wmemiM_dhF_q_0_EN) + wmemiM_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemiM_dhF_q_0_D_IN; + if (wmemiM_dhF_q_1_EN) + wmemiM_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemiM_dhF_q_1_D_IN; + if (wmemiM_errorSticky_EN) + wmemiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemiM_errorSticky_D_IN; + if (wmemiM_operateD_EN) + wmemiM_operateD <= `BSV_ASSIGNMENT_DELAY wmemiM_operateD_D_IN; + if (wmemiM_peerIsReady_EN) + wmemiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemiM_peerIsReady_D_IN; + if (wmemiM_reqF_cntr_r_EN) + wmemiM_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemiM_reqF_cntr_r_D_IN; + if (wmemiM_reqF_q_0_EN) + wmemiM_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemiM_reqF_q_0_D_IN; + if (wmemiM_reqF_q_1_EN) + wmemiM_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemiM_reqF_q_1_D_IN; + if (wmemiM_trafficSticky_EN) + wmemiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wmemiM_trafficSticky_D_IN; + if (wmemiS_errorSticky_EN) + wmemiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemiS_errorSticky_D_IN; + if (wmemiS_operateD_EN) + wmemiS_operateD <= `BSV_ASSIGNMENT_DELAY wmemiS_operateD_D_IN; + if (wmemiS_peerIsReady_EN) + wmemiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemiS_peerIsReady_D_IN; + if (wmemiS_respF_cntr_r_EN) + wmemiS_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wmemiS_respF_cntr_r_D_IN; + if (wmemiS_respF_q_0_EN) + wmemiS_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemiS_respF_q_0_D_IN; + if (wmemiS_respF_q_1_EN) + wmemiS_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemiS_respF_q_1_D_IN; + if (wmemiS_trafficSticky_EN) + wmemiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wmemiS_trafficSticky_D_IN; + end + if (wmemiM_statusR_EN) + wmemiM_statusR <= `BSV_ASSIGNMENT_DELAY wmemiM_statusR_D_IN; + if (wmemiS_statusR_EN) + wmemiS_statusR <= `BSV_ASSIGNMENT_DELAY wmemiS_statusR_D_IN; + end + + always@(posedge CLK or `BSV_RESET_EDGE RST_N) + if (RST_N == `BSV_RESET_VALUE) + begin + wmemiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wmemiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wmemiM_isReset_isInReset_EN) + wmemiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wmemiM_isReset_isInReset_D_IN; + if (wmemiS_isReset_isInReset_EN) + wmemiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wmemiS_isReset_isInReset_D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + a4l_a4rdAddr_fifof_cntr_r = 2'h2; + a4l_a4rdAddr_fifof_q_0 = 35'h2AAAAAAAA; + a4l_a4rdAddr_fifof_q_1 = 35'h2AAAAAAAA; + a4l_a4wrAddr_fifof_cntr_r = 2'h2; + a4l_a4wrAddr_fifof_q_0 = 35'h2AAAAAAAA; + a4l_a4wrAddr_fifof_q_1 = 35'h2AAAAAAAA; + a4l_a4wrData_fifof_cntr_r = 2'h2; + a4l_a4wrData_fifof_q_0 = 36'hAAAAAAAAA; + a4l_a4wrData_fifof_q_1 = 36'hAAAAAAAAA; + axiActive = 1'h0; + wmemiM_busyWithMessage = 1'h0; + wmemiM_dhF_cntr_r = 2'h2; + wmemiM_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiM_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiM_errorSticky = 1'h0; + wmemiM_isReset_isInReset = 1'h0; + wmemiM_operateD = 1'h0; + wmemiM_peerIsReady = 1'h0; + wmemiM_reqF_cntr_r = 2'h2; + wmemiM_reqF_q_0 = 52'hAAAAAAAAAAAAA; + wmemiM_reqF_q_1 = 52'hAAAAAAAAAAAAA; + wmemiM_statusR = 8'hAA; + wmemiM_trafficSticky = 1'h0; + wmemiS_errorSticky = 1'h0; + wmemiS_isReset_isInReset = 1'h0; + wmemiS_operateD = 1'h0; + wmemiS_peerIsReady = 1'h0; + wmemiS_respF_cntr_r = 2'h2; + wmemiS_respF_q_0 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiS_respF_q_1 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemiS_statusR = 8'hAA; + wmemiS_trafficSticky = 1'h0; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_axi_write_response) + begin + v__h10592 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_axi_write_response) + $display("[%0d]: %m: AXI4-LITE WRITE RESPOSNE", v__h10592); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_axi_read_response) + begin + v__h10751 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_axi_read_response) + $display("[%0d]: %m: AXI4-LITE READ RESPOSNE Data:%0x", + v__h10751, + a4l_a4rdResp_fifof_D_OUT[31:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] == 3'd1) + begin + v__h10358 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] == 3'd1) + $display("[%0d]: %m: AXI4-LITE WRITE REQUEST Addr:%0x BE:%0x Data:%0x", + v__h10358, + wmemiS_reqF_D_OUT[47:12], + wmemiS_dhF_D_OUT[15:0], + wmemiS_dhF_D_OUT[143:16]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] != 3'd1) + begin + v__h10384 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_request && wmemiS_reqF_D_OUT[43] && + wmemiS_reqF_D_OUT[51:49] != 3'd1) + $display("[%0d]: %m: AXI4-LITE READ REQUEST Addr:%0x", + v__h10384, + wmemiS_reqF_D_OUT[47:12]); + end + // synopsys translate_on +endmodule // mkWmemiTap + diff --git a/rtl/mkWsiAdapter16B4B.v b/rtl/mkWsiAdapter16B4B.v index 3fa3eb0c..bd56eb6c 100644 --- a/rtl/mkWsiAdapter16B4B.v +++ b/rtl/mkWsiAdapter16B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:19 EST 2014 +// On Thu Jan 30 14:51:23 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter32B4B.v b/rtl/mkWsiAdapter32B4B.v index c8fbf9d4..3178cd24 100644 --- a/rtl/mkWsiAdapter32B4B.v +++ b/rtl/mkWsiAdapter32B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:20 EST 2014 +// On Thu Jan 30 14:51:24 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B16B.v b/rtl/mkWsiAdapter4B16B.v index 8aff7fbd..91524875 100644 --- a/rtl/mkWsiAdapter4B16B.v +++ b/rtl/mkWsiAdapter4B16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:19 EST 2014 +// On Thu Jan 30 14:51:23 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B32B.v b/rtl/mkWsiAdapter4B32B.v index e38f5d5f..f00abd91 100644 --- a/rtl/mkWsiAdapter4B32B.v +++ b/rtl/mkWsiAdapter4B32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:00:19 EST 2014 +// On Thu Jan 30 14:51:24 EST 2014 // // // Ports: From 9ea730adeb75bd0eb8e6a6e904e0f7801506dc22 Mon Sep 17 00:00:00 2001 From: Shepard Siegel Date: Mon, 3 Feb 2014 17:06:14 -0500 Subject: [PATCH 3/3] added AXBLUART at WMemiTap in ML605 --- bsv/axi/AXBLUART.bsv | 94 + bsv/top/FTop_ml605.bsv | 8 +- bsv/utl/CompileTime.bsv | 2 +- logs/ml605-20140203_1611/fpgaTop-ml605.srp | 14265 +++++++++++++++++++ logs/ml605-20140203_1611/fpgaTop.bld | 5926 ++++++++ logs/ml605-20140203_1611/fpgaTop.par | 1217 ++ logs/ml605-20140203_1611/fpgaTop.twr | 10753 ++++++++++++++ logs/ml605-20140203_1611/fpgaTop_map.mrp | 8532 +++++++++++ rtl/mkAXBLUART.v | 941 ++ rtl/mkBLUART.v | 2 +- rtl/mkBiasWorker16B.v | 57 +- rtl/mkBiasWorker32B.v | 57 +- rtl/mkBiasWorker4B.v | 57 +- rtl/mkBiasWorker8B.v | 57 +- rtl/mkCTop16B.v | 2 +- rtl/mkDramServer_v6.v | 119 +- rtl/mkFMC150.v | 2 +- rtl/mkFTop_ml605.v | 285 +- rtl/mkFlashController2416.v | 2 +- rtl/mkFlashWorker.v | 25 +- rtl/mkGMAC.v | 2 +- rtl/mkGbeWorker.v | 2 +- rtl/mkICAPWorker.v | 2 +- rtl/mkMemiTestWorker.v | 2 +- rtl/mkOCApp16B.v | 2 +- rtl/mkOCCP.v | 4 +- rtl/mkOCDP16B.v | 23 +- rtl/mkOCInf16B.v | 2 +- rtl/mkPktFork.v | 8 +- rtl/mkPktMerge.v | 8 +- rtl/mkQABSMF.v | 2 +- rtl/mkQABSMF3.v | 2 +- rtl/mkSMAdapter16B.v | 12 +- rtl/mkSMAdapter32B.v | 2 +- rtl/mkSMAdapter4B.v | 2 +- rtl/mkSMAdapter8B.v | 12 +- rtl/mkTLPCM.v | 2 +- rtl/mkTLPClientNode.v | 2 +- rtl/mkTLPSM.v | 2 +- rtl/mkTLPSerializer.v | 2 +- rtl/mkTLPServerNode.v | 2 +- rtl/mkTimeClient.v | 2 +- rtl/mkUUID.v | 2 +- rtl/mkWSICaptureWorker4B.v | 79 +- rtl/mkWciInitiator.v | 40 +- rtl/mkWciMonitor.v | 2 +- rtl/mkWciTarget.v | 36 +- rtl/mkWmemiTap.v | 74 +- rtl/mkWsiAdapter16B4B.v | 2 +- rtl/mkWsiAdapter32B4B.v | 2 +- rtl/mkWsiAdapter4B16B.v | 2 +- rtl/mkWsiAdapter4B32B.v | 2 +- scripts/buildhdl/fpgaTop-ml605.prj | 2 + 53 files changed, 42335 insertions(+), 410 deletions(-) create mode 100644 bsv/axi/AXBLUART.bsv create mode 100644 logs/ml605-20140203_1611/fpgaTop-ml605.srp create mode 100644 logs/ml605-20140203_1611/fpgaTop.bld create mode 100644 logs/ml605-20140203_1611/fpgaTop.par create mode 100644 logs/ml605-20140203_1611/fpgaTop.twr create mode 100644 logs/ml605-20140203_1611/fpgaTop_map.mrp create mode 100644 rtl/mkAXBLUART.v diff --git a/bsv/axi/AXBLUART.bsv b/bsv/axi/AXBLUART.bsv new file mode 100644 index 00000000..bebcf6c9 --- /dev/null +++ b/bsv/axi/AXBLUART.bsv @@ -0,0 +1,94 @@ +// AXBLUART - An AXI wrapper around a BSV UART +// Copyright (c) 2014 Atomic Rules LLC - ALL RIGHTS RESERVED + +import ARAXI4L ::*; +import BLUART ::*; + +import FIFO ::*; +import GetPut ::*; +import Vector ::*; + +interface AXBLUARTIfc; + interface A4L_Es s_axi; // Slave AXI Ifc + interface UART_pads upads; // UART pads +endinterface + +(* synthesize, default_clock_osc="s_axi_aclk", default_reset="s_axi_aresetn" *) +module mkAXBLUART (AXBLUARTIfc); + A4LSlaveIfc a4l <- mkA4LSlave; // The AXI4-Lite Slave Interface + Reg#(Bit#(32)) r0 <- mkReg(0); // Some regsiters for testing... + Reg#(Bit#(32)) r4 <- mkReg(0); + Reg#(Bit#(32)) r8 <- mkReg(0); + Reg#(Bit#(32)) rC <- mkReg(0); + BLUARTIfc bluart <- mkBLUART; // BLUART + Reg#(Bool) uartInited <- mkReg(False); + Reg#(UInt#(6)) uartTxtP <- mkReg(0); + + function Vector#(40,Bit#(8)) uartLine(String s); + Integer n = primStringToInteger(s); + Integer l = stringLength(s) - 1; + Vector#(40,Bit#(8)) text; + for (Integer i = 0; i < 40; i = i + 1) begin + Bit#(8) ch = fromInteger(n % 256); + n = n / 256; + if (ch == 0) text[i] = 8'h20; // blank space + else text[l-i] = ch; + end + return text; + endfunction + +rule init_uart_text (!uartInited); + Vector#(40,Bit#(8)) initText = uartLine("AXBLUART.bsv - Atomic Rules LLC (c) 2014"); + case (uartTxtP) + 0,42 : bluart.txChar.put(8'h0d); // CR + 1,43 : bluart.txChar.put(8'h0a); // LF + default: bluart.txChar.put(initText[uartTxtP-2]); + endcase + uartTxtP <= uartTxtP + 1; + if (uartTxtP==43) uartInited <= True; +endrule + +rule a4l_cfwr; // AXI4-Lite Configuration Property Writes... + let wa = a4l.f.wrAddr.first; a4l.f.wrAddr.deq; // Get the write address + let wd = a4l.f.wrData.first; a4l.f.wrData.deq; // Get the write data + case (wa.addr[7:0]) matches // Take some action with it... + 'h00 : r0 <= unpack(wd.data); + 'h04 : r4 <= unpack(wd.data); + 'h08 : r8 <= unpack(wd.data); + 'h0C : rC <= unpack(wd.data); + 'h20 : bluart.setClkDiv.put(truncate(unpack(wd.data))); + 'h2C : bluart.txChar.put (truncate(unpack(wd.data))); + endcase + a4l.f.wrResp.enq(A4LWrResp{resp:OKAY}); // Acknowledge the write + $display("[%0d]: %m: AXI4-LITE CONFIG WRITE Addr:%0x BE:%0x Data:%0x", $time, wa.addr, wd.strb, wd.data); +endrule + +rule a4l_cfrd; // AXI4-Lite Configuration Property Reads... + let ra = a4l.f.rdAddr.first; a4l.f.rdAddr.deq; // Get the read address + Bit#(32) rdat = ?; + case (ra.addr[7:0]) matches + 'h00 : rdat = pack(r0); // return r0 + 'h04 : rdat = pack(r4); // return r4 + 'h08 : rdat = pack(r8); // return r8 + 'h0C : rdat = pack(rC); // return rC + 'h10 : rdat = 32'hDEADBEEF; // return a constant + 'h14 : rdat = 32'hBABECAFE; // return a constant + 'h18 : rdat = 32'hF00DFACE; // return a constant + 'h1C : rdat = 32'hFEEDC0DE; // return a constant + 'h24 : rdat = extend(pack(bluart.txLevel)); + 'h28 : rdat = extend(pack(bluart.rxLevel)); + 'h30 : action + let d <- bluart.rxChar.get(); + rdat = extend(unpack(d)); + endaction + endcase + a4l.f.rdResp.enq(A4LRdResp{data:rdat,resp:OKAY}); // Return the read data + $display("[%0d]: %m: AXI4-LITE CONFIG READ Addr:%0x",$time, ra.addr); + $display("[%0d]: %m: AXI4-LITE CONFIG READ RESPOSNE Data:%0x",$time, rdat); +endrule + + A4L_Es a4ls <- mkA4StoEs(a4l.a4ls); // return the expanded interface... + //return(a4ls); + interface A4L_Es s_axi = a4ls; // prepend "s_axi" + interface UART_pads upads = bluart.pads; +endmodule diff --git a/bsv/top/FTop_ml605.bsv b/bsv/top/FTop_ml605.bsv index 0d0cfa37..9ff63506 100644 --- a/bsv/top/FTop_ml605.bsv +++ b/bsv/top/FTop_ml605.bsv @@ -2,6 +2,8 @@ // Copyright (c) 2009-2012 Atomic Rules LLC - ALL RIGHTS RESERVED // Application Imports... +import ARAXI4L ::*; +import AXBLUART ::*; import BLUART ::*; import Config ::*; import CPDefs ::*; @@ -86,6 +88,7 @@ module mkFTop_ml605#(Clock sys0_clkp, Clock sys0_clkn, // 200 MHz Board Reg#(UInt#(32)) freeCnt <- mkReg(0, clocked_by p125Clk, reset_by p125Rst); WmemiTapIfc wmemiTap <- mkWmemiTap( clocked_by p125Clk, reset_by p125Rst); + AXBLUARTIfc axbluart <- mkAXBLUART( clocked_by p125Clk, reset_by p125Rst); rule inc_freecnt; freeCnt <= freeCnt + 1; endrule @@ -144,6 +147,9 @@ module mkFTop_ml605#(Clock sys0_clkp, Clock sys0_clkn, // 200 MHz Board mkConnection(ctop.wmemiM0, wmemiTap.wmemiS0); mkConnection(wmemiTap.wmemiM0, dram0.wmemiS0); + A4L_Em a4lm <- mkA4MtoEm(wmemiTap.axiM0, clocked_by p125Clk, reset_by p125Rst); + mkConnection(a4lm, axbluart.s_axi); + rule init_lcd if (needs_init); // Paint the 16x2 LCD... Vector#(16,Bit#(8)) text1 = lcdLine(" Atomic Rules "); Vector#(16,Bit#(8)) text2 = lcdLine("OpenCPI : ml605 "); @@ -169,6 +175,6 @@ module mkFTop_ml605#(Clock sys0_clkp, Clock sys0_clkn, // 200 MHz Board interface MDIO_Pads mdio = gbe0.mdio; interface SPI32Pads flpCDC = fmc150.padsCDC; interface SPI5Pads flpDAC = fmc150.padsDAC; - interface UART_pads upads = ctop.upads; + interface UART_pads upads = axbluart.upads; endmodule: mkFTop_ml605 diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv index e5f56613..73fe0250 100644 --- a/bsv/utl/CompileTime.bsv +++ b/bsv/utl/CompileTime.bsv @@ -1 +1 @@ -Bit#(32) compileTime = 1391113942; // Verilog Thu Jan 30 15:32:22 EST 2014 +Bit#(32) compileTime = 1391459380; // Verilog Mon Feb 3 15:29:40 EST 2014 diff --git a/logs/ml605-20140203_1611/fpgaTop-ml605.srp b/logs/ml605-20140203_1611/fpgaTop-ml605.srp new file mode 100644 index 00000000..4f2b6406 --- /dev/null +++ b/logs/ml605-20140203_1611/fpgaTop-ml605.srp @@ -0,0 +1,14265 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter xsthdpini set to ocpihdp_v6.ini + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-ml605.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc6vlx240t-ff1156-1 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +LUT Combining : off +Reduce Control Sets : off +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Power Reduction : NO +Library Search Order : fpgaTop.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +---- Other Options +change_error_to_warning : "HDLCompiler:532 HDLCompiler:597" + +========================================================================= + +INFO:Xst - Changing 'HDLCompiler:532' to warning +INFO:Xst - Changing 'HDLCompiler:597' to warning + +========================================================================= +* HDL Parsing * +========================================================================= +The vhdl library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +The veri library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFO.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/Ethernet_v6_v1_5.v" into library work +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" Line 85. parameter declaration becomes local in pcie_upconfig_fix_3451_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" Line 76. parameter declaration becomes local in pcie_reset_delay_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" Line 120. parameter declaration becomes local in pcie_brams_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" Line 216. parameter declaration becomes local in pcie_gtx_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 325. parameter declaration becomes local in pcie_pipe_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" Line 103. parameter declaration becomes local in pcie_pipe_lane_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" Line 90. parameter declaration becomes local in pcie_pipe_misc_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 85. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 87. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 88. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 89. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 90. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 91. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 93. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 94. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 95. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 96. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 107. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 108. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 109. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 110. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 90. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 91. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 92. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 93. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 94. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 95. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 96. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 97. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 98. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 99. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 100. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTimeClient.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCRC32.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGMAC.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkICAPWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 200. parameter declaration becomes local in mc with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_buf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_dec_fix.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into library work +Parsing module . +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" into library work +Parsing module . +WARNING:HDLCompiler:751 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 271: Redeclaration of ansi port app_addr is not allowed +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPCM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktFork.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktMerge.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkUUID.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCCP.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWciMonitor.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFMC150.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkLCDController.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" into library work +Parsing module . + +========================================================================= +* HDL Elaboration * +========================================================================= +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Port flash_wp_n is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBLUART.v" Line 343: Assignment to rxCtsReg ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 541: Assignment to a4l_a4wrResp_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 542: Assignment to a4l_a4wrResp_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 543: Assignment to a4l_a4rdResp_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 545: Assignment to a4l_a4rdResp_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 546: Assignment to a4ls_wrAddrVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 547: Assignment to a4ls_wrAddrVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 548: Assignment to a4ls_wrDataVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 549: Assignment to a4ls_wrDataVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 550: Assignment to a4ls_wrRespRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 551: Assignment to a4ls_wrRespRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 552: Assignment to a4ls_rdAddrVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 553: Assignment to a4ls_rdAddrVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 554: Assignment to a4ls_rdRespRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 555: Assignment to a4ls_rdRespRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 556: Assignment to a4ls_wrAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 557: Assignment to a4ls_wrAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 558: Assignment to a4ls_wrProt_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 559: Assignment to a4ls_wrProt_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 560: Assignment to a4ls_wrData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 561: Assignment to a4ls_wrData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 562: Assignment to a4ls_wrStrb_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 563: Assignment to a4ls_wrStrb_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 564: Assignment to a4ls_rdAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 565: Assignment to a4ls_rdAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 566: Assignment to a4ls_rdProt_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 567: Assignment to a4ls_rdProt_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 568: Assignment to a4l_a4wrAddr_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 569: Assignment to a4l_a4wrAddr_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 570: Assignment to a4l_a4wrData_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 571: Assignment to a4l_a4wrData_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 572: Assignment to a4l_a4wrResp_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 575: Assignment to a4l_a4wrResp_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 576: Assignment to a4l_a4wrResp_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 577: Assignment to a4l_a4rdAddr_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 578: Assignment to a4l_a4rdAddr_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 579: Assignment to a4l_a4rdResp_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 582: Assignment to a4l_a4rdResp_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 583: Assignment to a4l_a4rdResp_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 604: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 630: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 664: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1434: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1466: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1467: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1474: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1475: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1476: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1477: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1478: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1482: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1483: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1484: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1485: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1486: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1487: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1488: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1489: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1490: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1491: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1500: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1501: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1502: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1503: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1504: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1508: Assignment to wtiS_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1509: Assignment to wtiS_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1510: Assignment to wtiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1511: Assignment to wtiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1513: Assignment to nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1514: Assignment to statusReg_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1515: Assignment to statusReg_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1516: Assignment to dataBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1523: Assignment to dataBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1527: Assignment to dataBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1531: Assignment to dataBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1532: Assignment to dataBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1533: Assignment to dataBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1534: Assignment to dataBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1535: Assignment to dataBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1536: Assignment to dataBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1537: Assignment to dataBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1538: Assignment to dataBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1540: Assignment to dataBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1541: Assignment to dataBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1542: Assignment to dataBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1549: Assignment to dataBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1554: Assignment to dataBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1555: Assignment to dataBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1557: Assignment to dataBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1558: Assignment to dataBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1560: Assignment to dataBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1561: Assignment to dataBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1562: Assignment to dataBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1563: Assignment to dataBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1565: Assignment to dataBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1566: Assignment to dataBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1568: Assignment to metaBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1575: Assignment to metaBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1579: Assignment to metaBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1583: Assignment to metaBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1584: Assignment to metaBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1585: Assignment to metaBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1586: Assignment to metaBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1587: Assignment to metaBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1588: Assignment to metaBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1589: Assignment to metaBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1590: Assignment to metaBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1592: Assignment to metaBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1593: Assignment to metaBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1594: Assignment to metaBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1601: Assignment to metaBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1606: Assignment to metaBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1607: Assignment to metaBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1609: Assignment to metaBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1610: Assignment to metaBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1612: Assignment to metaBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1613: Assignment to metaBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1614: Assignment to metaBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1615: Assignment to metaBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1617: Assignment to metaBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1618: Assignment to metaBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1620: Assignment to metaBram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1627: Assignment to metaBram_1_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1631: Assignment to metaBram_1_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1635: Assignment to metaBram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1636: Assignment to metaBram_1_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1637: Assignment to metaBram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1638: Assignment to metaBram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1639: Assignment to metaBram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1640: Assignment to metaBram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1641: Assignment to metaBram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1642: Assignment to metaBram_1_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1644: Assignment to metaBram_1_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1645: Assignment to metaBram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1646: Assignment to metaBram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1653: Assignment to metaBram_1_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1658: Assignment to metaBram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1659: Assignment to metaBram_1_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1661: Assignment to metaBram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1662: Assignment to metaBram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1664: Assignment to metaBram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1665: Assignment to metaBram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1666: Assignment to metaBram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1667: Assignment to metaBram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1669: Assignment to metaBram_1_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1670: Assignment to metaBram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1672: Assignment to metaBram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1679: Assignment to metaBram_2_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1683: Assignment to metaBram_2_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1687: Assignment to metaBram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1688: Assignment to metaBram_2_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1689: Assignment to metaBram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1690: Assignment to metaBram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1691: Assignment to metaBram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1692: Assignment to metaBram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1693: Assignment to metaBram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1694: Assignment to metaBram_2_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1696: Assignment to metaBram_2_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1697: Assignment to metaBram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1698: Assignment to metaBram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1705: Assignment to metaBram_2_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1710: Assignment to metaBram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1711: Assignment to metaBram_2_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1713: Assignment to metaBram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1714: Assignment to metaBram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1716: Assignment to metaBram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1717: Assignment to metaBram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1718: Assignment to metaBram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1719: Assignment to metaBram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1721: Assignment to metaBram_2_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1722: Assignment to metaBram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1724: Assignment to metaBram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1731: Assignment to metaBram_3_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1735: Assignment to metaBram_3_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1739: Assignment to metaBram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1740: Assignment to metaBram_3_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1741: Assignment to metaBram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1742: Assignment to metaBram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1743: Assignment to metaBram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1744: Assignment to metaBram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1745: Assignment to metaBram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1746: Assignment to metaBram_3_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1748: Assignment to metaBram_3_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1749: Assignment to metaBram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1750: Assignment to metaBram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1757: Assignment to metaBram_3_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1762: Assignment to metaBram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1763: Assignment to metaBram_3_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1765: Assignment to metaBram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1766: Assignment to metaBram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1768: Assignment to metaBram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1769: Assignment to metaBram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1770: Assignment to metaBram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1771: Assignment to metaBram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1773: Assignment to metaBram_3_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1774: Assignment to metaBram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1776: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1777: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1778: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1779: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1780: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1781: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1782: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1783: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1784: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1785: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1786: Assignment to wti_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1787: Assignment to wti_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1788: Assignment to wti_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1789: Assignment to wti_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1790: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1794: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1801: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1802: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1812: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1813: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1815: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1816: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1817: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1819: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1820: Assignment to dataBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1824: Assignment to metaBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1829: Assignment to metaBram_1_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1834: Assignment to metaBram_2_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1839: Assignment to metaBram_3_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1844: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1845: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1846: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2103: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2689: Assignment to isFirst ignored, since the identifier is never used +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Port EN_uuid is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 834: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 888: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 889: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 893: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 894: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 895: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 896: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 897: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 901: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 902: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 903: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 904: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 905: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 906: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 907: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 908: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 909: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 910: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 911: Assignment to wmemi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 914: Assignment to wmemi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 915: Assignment to wmemi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 918: Assignment to wmemi_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 919: Assignment to wmemi_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 920: Assignment to wmemi_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 921: Assignment to wmemi_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 922: Assignment to wmemi_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 923: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 924: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 925: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 926: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 927: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 928: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 929: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 930: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 931: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 935: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 939: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 940: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 954: Assignment to wmemi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 957: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1125: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1149: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1213: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1234: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1282: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1303: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1422: Assignment to respCnt ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 787: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 830: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 831: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 835: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 836: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 837: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 838: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 839: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 843: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 844: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 845: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 846: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 847: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 848: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 849: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 850: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 851: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 852: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 861: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 862: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 863: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 864: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 865: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 869: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 870: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 872: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 873: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 874: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 875: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 876: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 877: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 878: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 879: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 880: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 881: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 882: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 883: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 884: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 885: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 886: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 890: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 894: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 895: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 905: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 906: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 908: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 909: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 910: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 912: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 913: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 915: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 916: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 917: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 918: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 919: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1019: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1043: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1128: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1152: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1349: Assignment to wci_wslv_cEdge ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1743: Assignment to tieOff0_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1744: Assignment to tieOff0_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1745: Assignment to tieOff0_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1746: Assignment to tieOff0_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1747: Assignment to tieOff0_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1748: Assignment to tieOff0_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1749: Assignment to tieOff0_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1750: Assignment to tieOff0_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1751: Assignment to tieOff0_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1752: Assignment to tieOff0_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1753: Assignment to tieOff5_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1754: Assignment to tieOff5_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1755: Assignment to tieOff5_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1756: Assignment to tieOff5_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1757: Assignment to tieOff5_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1758: Assignment to tieOff5_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1759: Assignment to tieOff5_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1760: Assignment to tieOff5_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1761: Assignment to tieOff5_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1762: Assignment to tieOff5_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1763: Assignment to tieOff6_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1764: Assignment to tieOff6_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1765: Assignment to tieOff6_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1766: Assignment to tieOff6_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1767: Assignment to tieOff6_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1768: Assignment to tieOff6_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1769: Assignment to tieOff6_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1770: Assignment to tieOff6_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1771: Assignment to tieOff6_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1772: Assignment to tieOff6_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1773: Assignment to tieOff7_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1774: Assignment to tieOff7_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1775: Assignment to tieOff7_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1776: Assignment to tieOff7_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1777: Assignment to tieOff7_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1778: Assignment to tieOff7_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1779: Assignment to tieOff7_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1780: Assignment to tieOff7_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1781: Assignment to tieOff7_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1782: Assignment to tieOff7_wci_Es_mData_w_whas ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9392: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9471: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9548: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9625: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9702: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9855: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9931: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10007: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10083: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10159: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10235: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10311: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10387: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10463: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10511: Assignment to warmResetP_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10512: Assignment to warmResetP_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10513: Assignment to timeServ_jamFrac_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10516: Assignment to timeServ_jamFracVal_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10517: Assignment to timeServ_jamFracVal_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10518: Assignment to deviceDNA_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10519: Assignment to deviceDNA_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10522: Assignment to devDNAV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10523: Assignment to rom_serverAdapter_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10537: Assignment to rom_serverAdapter_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10538: Assignment to rom_serverAdapter_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10540: Assignment to rom_serverAdapter_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10541: Assignment to rom_serverAdapter_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10543: Assignment to rom_serverAdapter_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10544: Assignment to rom_serverAdapter_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10545: Assignment to rom_serverAdapter_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10546: Assignment to rom_serverAdapter_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10548: Assignment to rom_serverAdapter_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10549: Assignment to rom_serverAdapter_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10551: Assignment to dna_rdReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10553: Assignment to dna_shftReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10555: Assignment to uuidV_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10556: Assignment to uuidV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10557: Assignment to wci_0_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10563: Assignment to wci_0_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10564: Assignment to wci_0_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10565: Assignment to wci_0_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10566: Assignment to wci_0_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10570: Assignment to wci_1_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10576: Assignment to wci_1_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10577: Assignment to wci_1_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10578: Assignment to wci_1_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10579: Assignment to wci_1_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10583: Assignment to wci_2_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10589: Assignment to wci_2_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10590: Assignment to wci_2_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10591: Assignment to wci_2_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10592: Assignment to wci_2_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10596: Assignment to wci_3_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10602: Assignment to wci_3_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10603: Assignment to wci_3_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10604: Assignment to wci_3_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10605: Assignment to wci_3_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10609: Assignment to wci_4_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10615: Assignment to wci_4_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10616: Assignment to wci_4_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10617: Assignment to wci_4_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10618: Assignment to wci_4_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10622: Assignment to wci_5_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10628: Assignment to wci_5_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10629: Assignment to wci_5_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10630: Assignment to wci_5_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10631: Assignment to wci_5_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10635: Assignment to wci_6_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10641: Assignment to wci_6_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10642: Assignment to wci_6_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10643: Assignment to wci_6_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10644: Assignment to wci_6_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10648: Assignment to wci_7_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10654: Assignment to wci_7_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10655: Assignment to wci_7_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10656: Assignment to wci_7_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10657: Assignment to wci_7_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10661: Assignment to wci_8_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10667: Assignment to wci_8_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10668: Assignment to wci_8_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10669: Assignment to wci_8_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10670: Assignment to wci_8_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10674: Assignment to wci_9_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10680: Assignment to wci_9_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10681: Assignment to wci_9_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10682: Assignment to wci_9_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10683: Assignment to wci_9_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10687: Assignment to wci_10_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10693: Assignment to wci_10_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10694: Assignment to wci_10_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10695: Assignment to wci_10_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10696: Assignment to wci_10_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10700: Assignment to wci_11_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10706: Assignment to wci_11_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10707: Assignment to wci_11_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10708: Assignment to wci_11_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10709: Assignment to wci_11_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10713: Assignment to wci_12_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10719: Assignment to wci_12_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10720: Assignment to wci_12_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10721: Assignment to wci_12_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10722: Assignment to wci_12_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10726: Assignment to wci_13_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10732: Assignment to wci_13_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10733: Assignment to wci_13_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10734: Assignment to wci_13_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10735: Assignment to wci_13_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10739: Assignment to wci_14_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10745: Assignment to wci_14_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10746: Assignment to wci_14_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10747: Assignment to wci_14_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10748: Assignment to wci_14_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10752: Assignment to wci_Emv_0_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10753: Assignment to wci_Emv_0_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10754: Assignment to wci_Emv_0_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10755: Assignment to wci_Emv_0_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10756: Assignment to wci_Emv_1_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10757: Assignment to wci_Emv_1_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10758: Assignment to wci_Emv_1_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10759: Assignment to wci_Emv_1_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10760: Assignment to wci_Emv_2_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10761: Assignment to wci_Emv_2_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10762: Assignment to wci_Emv_2_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10763: Assignment to wci_Emv_2_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10764: Assignment to wci_Emv_3_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10765: Assignment to wci_Emv_3_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10766: Assignment to wci_Emv_3_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10767: Assignment to wci_Emv_3_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10768: Assignment to wci_Emv_4_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10769: Assignment to wci_Emv_4_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10770: Assignment to wci_Emv_4_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10771: Assignment to wci_Emv_4_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10772: Assignment to wci_Emv_5_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10773: Assignment to wci_Emv_5_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10774: Assignment to wci_Emv_5_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10775: Assignment to wci_Emv_5_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10776: Assignment to wci_Emv_6_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10777: Assignment to wci_Emv_6_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10778: Assignment to wci_Emv_6_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10779: Assignment to wci_Emv_6_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10780: Assignment to wci_Emv_7_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10781: Assignment to wci_Emv_7_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10782: Assignment to wci_Emv_7_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10783: Assignment to wci_Emv_7_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10784: Assignment to wci_Emv_8_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10785: Assignment to wci_Emv_8_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10786: Assignment to wci_Emv_8_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10787: Assignment to wci_Emv_8_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10788: Assignment to wci_Emv_9_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10789: Assignment to wci_Emv_9_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10790: Assignment to wci_Emv_9_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10791: Assignment to wci_Emv_9_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10792: Assignment to wci_Emv_10_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10793: Assignment to wci_Emv_10_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10794: Assignment to wci_Emv_10_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10795: Assignment to wci_Emv_10_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10796: Assignment to wci_Emv_11_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10797: Assignment to wci_Emv_11_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10798: Assignment to wci_Emv_11_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10799: Assignment to wci_Emv_11_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10800: Assignment to wci_Emv_12_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10801: Assignment to wci_Emv_12_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10802: Assignment to wci_Emv_12_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10803: Assignment to wci_Emv_12_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10804: Assignment to wci_Emv_13_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10805: Assignment to wci_Emv_13_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10806: Assignment to wci_Emv_13_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10807: Assignment to wci_Emv_13_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10808: Assignment to wci_Emv_14_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10809: Assignment to wci_Emv_14_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10810: Assignment to wci_Emv_14_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10811: Assignment to wci_Emv_14_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10817: Assignment to wci_0_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10821: Assignment to wci_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10822: Assignment to wci_1_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10826: Assignment to wci_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10827: Assignment to wci_2_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10831: Assignment to wci_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10832: Assignment to wci_3_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10836: Assignment to wci_3_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10837: Assignment to wci_4_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10841: Assignment to wci_4_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10842: Assignment to wci_5_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10846: Assignment to wci_5_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10847: Assignment to wci_6_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10851: Assignment to wci_6_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10852: Assignment to wci_7_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10856: Assignment to wci_7_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10857: Assignment to wci_8_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10861: Assignment to wci_8_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10862: Assignment to wci_9_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10866: Assignment to wci_9_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10867: Assignment to wci_10_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10872: Assignment to wci_10_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10873: Assignment to wci_11_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10878: Assignment to wci_11_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10879: Assignment to wci_12_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10884: Assignment to wci_12_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10885: Assignment to wci_13_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10890: Assignment to wci_13_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10891: Assignment to wci_14_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10896: Assignment to wci_14_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12161: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12183: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12348: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12370: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12558: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12724: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12746: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12912: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12934: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13122: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13287: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13309: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13473: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13495: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13659: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13681: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13845: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13867: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14031: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14053: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14239: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14403: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14425: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14589: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14611: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14775: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14797: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14885: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15195: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15363: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15420: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15478: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15594: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15652: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15710: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15767: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15824: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15881: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15938: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15995: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16052: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16109: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16166: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 24475: Assignment to warmResetP ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 25618: Assignment to timeServ_ppsExtCapture ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 118: Assignment to wti_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 119: Assignment to wti_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 120: Assignment to wti_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 140: Assignment to wti_peerIsReady ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 198: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 240: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1691: Assignment to wtiM_0_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1692: Assignment to wtiM_0_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1693: Assignment to wtiM_1_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1694: Assignment to wtiM_1_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1695: Assignment to wtiM_2_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1696: Assignment to wtiM_2_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1697: Assignment to wtiM_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1698: Assignment to wtiM_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1699: Assignment to wtiM_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1918: Assignment to wtiM_0_peerIsReady ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Input port EN_uuid is not connected on this instance +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1243: Port sda is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 353: Port pd_PSEN is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 347: Assignment to ocb_mon_PSDONE ignored, since the identifier is never used +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 369: Module memc_ui_top does not have a parameter named OCB_MONITOR +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 379: Module memc_ui_top does not have a parameter named SIM_CAL_OPTION +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 380: Module memc_ui_top does not have a parameter named SIM_INIT_OPTION + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 386: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 432: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" Line 146: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" Line 153: Net does not have a driver. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 443: Result of 64-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 444: Result of 64-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 168: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 169: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 201: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" Line 426: Result of 32-bit expression is truncated to fit in 6-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 140: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 198: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 204: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:532 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 323: Index <13> is out of range [12:0] for signal . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 151: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 506: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 764: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 854: Result of 8-bit expression is truncated to fit in 7-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 879: Result of 11-bit expression is truncated to fit in 10-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 888: Result of 10-bit expression is truncated to fit in 9-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 935: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 950: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 966: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 987: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1038: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1051: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1179: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1208: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1083: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1561: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1573: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1657: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1735: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1745: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" Line 232: Assignment to rst_r ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 152: Assignment to dqs_ibuf_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 288: Assignment to dqs_n_tfb ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" Line 147: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" Line 239: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" Line 199: Assignment to dqs_oe_r ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 269: Assignment to wrdata_en_r7 ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1549: Assignment to wrlvl_done_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1634: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1758: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1761: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1764: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1767: Result of 32-bit expression is truncated to fit in 8-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 284: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 298: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 523: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 540: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 453: Assignment to wl_state_r1 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 310: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 324: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 331: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 339: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 301: Found full_case directive in module phy_rdclk_gen. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 173: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 180: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" Line 163: Result of 10-bit expression is truncated to fit in 9-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 566: Result of 8-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 647: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 707: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 878: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 918: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 946: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1025: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1046: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1048: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1167: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1179: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1283: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1292: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1296: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1317: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1343: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1356: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1357: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1372: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1395: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1405: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1413: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1479: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1481: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1483: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1497: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1525: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1073: Assignment to found_two_edge_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1541: Result of 31-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1650: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1784: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1809: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1880: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1974: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1984: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1995: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2037: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2091: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" Line 275: Result of 32-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 199: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 229: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 416: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 417: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 593: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 977: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 568: Assignment to ecc_single ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 570: Assignment to ecc_err_addr ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" Line 232: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" Line 199: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 620: Assignment to hi_priority ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 377: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 378: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 396: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 412: Assignment to ddr3_parity ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 419: Assignment to bank_mach_next ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 423: Assignment to app_ecc_multiple_err_i ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 267: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 268: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 298: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 306: Net does not have a driver. +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 399: Input port pd_PSDONE is not connected on this instance +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1246: Size mismatch in connection of port . Formal port size is 27-bit while actual signal size is 33-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1295: Size mismatch in connection of port . Formal port size is 256-bit while actual signal size is 32-bit. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1651: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1697: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1698: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1704: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1705: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1706: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1707: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1708: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1712: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1713: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1714: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1715: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1716: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1717: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1718: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1719: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1720: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1721: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1722: Assignment to memc_wdfWren_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1726: Assignment to memc_wdfEnd_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1727: Assignment to memc_wdfEnd_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1733: Assignment to wmemi_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1739: Assignment to wmemi_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1740: Assignment to wmemi_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1744: Assignment to wmemi_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1749: Assignment to wmemi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1750: Assignment to wmemi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1751: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1752: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1753: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1754: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1755: Assignment to memInReset_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1756: Assignment to memInReset_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1757: Assignment to wmemiReadInFlight_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1761: Assignment to wmemiReadInFlight_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1762: Assignment to wmemiReadInFlight_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1763: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1764: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1765: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1766: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1767: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1768: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1769: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1770: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1771: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1772: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1773: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1777: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1783: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1784: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1798: Assignment to wmemi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1799: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1800: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1801: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1991: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2015: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2121: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2143: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2291: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2753: Assignment to pioReadInFlight ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2876: Assignment to dbgCtrl ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 918: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 951: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 952: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 958: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 959: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 960: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 961: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 962: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 966: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 967: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 968: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 969: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 970: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 971: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 972: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 973: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 974: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 975: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 976: Assignment to flashC_rseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 980: Assignment to flashC_rseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 981: Assignment to flashC_rseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 982: Assignment to flashC_rseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 983: Assignment to flashC_rseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 984: Assignment to flashC_rseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 985: Assignment to flashC_rseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 987: Assignment to flashC_wseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 991: Assignment to flashC_wseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 992: Assignment to flashC_wseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 993: Assignment to flashC_wseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 994: Assignment to flashC_wseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 995: Assignment to flashC_wseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 996: Assignment to flashC_wseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 998: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1002: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1008: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1009: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1028: Assignment to flashC_rseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1055: Assignment to flashC_wseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1130: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1271: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1449: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1473: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1589: Assignment to flashC_wdReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1227: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1264: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1265: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1273: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1274: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1275: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1276: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1277: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1281: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1282: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1283: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1284: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1285: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1286: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1287: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1288: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1289: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1290: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1297: Assignment to spiCDC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1298: Assignment to spiCDC_doResp_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1302: Assignment to spiDAC_cGate_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1305: Assignment to spiDAC_csbR_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1306: Assignment to spiDAC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1314: Assignment to fcCdc_pulseAction_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1315: Assignment to fcCdc_pulseAction_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1316: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1320: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1328: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1329: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1342: Assignment to spiCDC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1343: Assignment to spiCDC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1344: Assignment to spiCDC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1345: Assignment to spiCDC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1346: Assignment to spiCDC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1347: Assignment to spiCDC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1348: Assignment to spiCDC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1349: Assignment to spiCDC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1350: Assignment to spiCDC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1354: Assignment to spiDAC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1355: Assignment to spiDAC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1356: Assignment to spiDAC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1357: Assignment to spiDAC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1358: Assignment to spiDAC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1359: Assignment to spiDAC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1360: Assignment to spiDAC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1361: Assignment to spiDAC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1362: Assignment to spiDAC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1363: Assignment to fcCdc_grayCounter_pwIncrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1364: Assignment to fcCdc_grayCounter_pwDecrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1365: Assignment to oneKHz_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1366: Assignment to oneKHz_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1367: Assignment to spiCDC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1368: Assignment to spiDAC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1369: Assignment to fcCdc_grayCounter_wdCounterCrossing_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1719: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1743: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 2023: Assignment to splitReadInFlight ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 614: Assignment to gmii_rx_clk_O ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 624: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 626: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 627: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 628: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1023: Assignment to rxRS_rxOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1024: Assignment to rxRS_rxOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1025: Assignment to txRS_txOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1026: Assignment to txRS_txOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1035: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1051: Assignment to txRS_txDV_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1056: Assignment to txRS_txER_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1057: Assignment to txRS_txER_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1058: Assignment to txRS_underflow_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1059: Assignment to txRS_underflow_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1062: Assignment to rxRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1065: Assignment to rxRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1066: Assignment to txRS_preambleCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1067: Assignment to txRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1068: Assignment to txRS_ifgCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1078: Assignment to txRS_lenCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1085: Assignment to txRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1437: Assignment to txRS_underflow ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1485: Assignment to rxRS_isSOF ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1768: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1802: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1803: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1809: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1810: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1811: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1812: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1813: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1817: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1818: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1819: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1820: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1821: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1822: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1823: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1824: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1825: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1826: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1827: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1828: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1829: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1830: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1831: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1832: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1833: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1836: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1837: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1846: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1847: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1848: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1849: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1850: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1854: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1855: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1856: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1857: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1858: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1859: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1860: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1861: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1862: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1863: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1864: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1868: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1874: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1875: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1885: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1886: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1887: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1888: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1889: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1891: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1892: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1893: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1895: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1896: Assignment to mdi_pwTick_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1897: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1898: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1899: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2341: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2365: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3497: Assignment to txDBGPos ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3755: Assignment to wti_nowReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1806: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1877: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1923: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2064: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2278: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2746: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2822: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 719: Assignment to block_clk ignored, since the identifier is never used + +Elaborating module +. + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1273: Assignment to TRNRDLLPSRCRDYN ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 180: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 229: Result of 9-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1886: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 69-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1894: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 68-bit. + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 986: Assignment to rx_func_level_reset_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1065: Assignment to wmemiS_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1071: Assignment to wmemiS_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1072: Assignment to wmemiS_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1077: Assignment to wmemiS_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1082: Assignment to wmemiS_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1085: Assignment to wmemiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1086: Assignment to wmemiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1087: Assignment to wmemiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1088: Assignment to wmemiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1089: Assignment to wmemiM_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1090: Assignment to wmemiM_reqF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1091: Assignment to wmemiM_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1092: Assignment to wmemiM_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1095: Assignment to wmemiM_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1096: Assignment to wmemiM_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1097: Assignment to wmemiM_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1098: Assignment to wmemiM_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1099: Assignment to wmemiM_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1100: Assignment to wmemiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1101: Assignment to wmemiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1102: Assignment to wmemiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1103: Assignment to wmemiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1104: Assignment to a4l_a4wrAddr_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1106: Assignment to a4l_a4wrAddr_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1107: Assignment to a4l_a4wrData_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1109: Assignment to a4l_a4wrData_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1110: Assignment to a4l_a4rdAddr_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1112: Assignment to a4l_a4rdAddr_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1113: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1114: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1115: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1116: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1117: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1118: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1119: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1120: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1121: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1122: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1123: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1124: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1125: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1126: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1129: Assignment to wmemiS_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1144: Assignment to a4l_a4wrAddr_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1145: Assignment to a4l_a4wrAddr_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1146: Assignment to a4l_a4wrData_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1150: Assignment to a4l_a4wrData_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1151: Assignment to a4l_a4wrData_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1152: Assignment to a4l_a4wrResp_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1153: Assignment to a4l_a4wrResp_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1159: Assignment to a4l_a4rdAddr_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1160: Assignment to a4l_a4rdAddr_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1161: Assignment to a4l_a4rdResp_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1162: Assignment to a4l_a4rdResp_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1163: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1164: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1165: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1166: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1167: Assignment to a4l_a4wrResp_data_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1168: Assignment to a4l_a4rdResp_data_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1186: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1212: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1247: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1273: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1308: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1334: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1380: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1401: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1449: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1471: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1533: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1557: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1688: Assignment to wmemiM_busyWithMessage ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2062: Assignment to pciw_pci0_wTrnTxSof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2063: Assignment to pciw_pci0_wTrnTxSof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2064: Assignment to pciw_pci0_wTrnTxEof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2065: Assignment to pciw_pci0_wTrnTxEof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2066: Assignment to pciw_pci0_wTrnTxDsc_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2067: Assignment to pciw_pci0_wTrnTxDsc_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2068: Assignment to pciw_pci0_wTrnTxRem_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2069: Assignment to pciw_pci0_wTrnTxRem_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2070: Assignment to pciw_pci0_wTrnTxDat_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2071: Assignment to pciw_pci0_wTrnTxDat_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2072: Assignment to pciw_pci0_wTrnRxNpOk_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2073: Assignment to pciw_pci0_wTrnRxNpOk_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2074: Assignment to pciw_pci0_wTrnRxCplS_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2075: Assignment to pciw_pci0_wTrnRxCplS_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2076: Assignment to pciw_pcie_irq_wInterruptRdyN_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2078: Assignment to pciw_pcie_irq_wInterruptRdyN_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2079: Assignment to pciw_pcie_irq_wInterruptDo_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2081: Assignment to pciw_pcie_irq_wInterruptDo_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2082: Assignment to a4lm_wrAddrRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2083: Assignment to a4lm_wrAddrRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2084: Assignment to a4lm_wrDataRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2085: Assignment to a4lm_wrDataRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2086: Assignment to a4lm_wrRespVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2087: Assignment to a4lm_wrRespVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2088: Assignment to a4lm_rdAddrRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2089: Assignment to a4lm_rdAddrRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2090: Assignment to a4lm_rdRespVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2091: Assignment to a4lm_rdRespVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2092: Assignment to a4lm_wrResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2093: Assignment to a4lm_wrResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2094: Assignment to a4lm_rdData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2095: Assignment to a4lm_rdData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2096: Assignment to a4lm_rdResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2097: Assignment to a4lm_rdResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2110: Assignment to pciw_p2iAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2111: Assignment to pciw_p2iAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2112: Assignment to pciw_p2iAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2117: Assignment to pciw_i2pAF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2119: Assignment to pciw_i2pAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2120: Assignment to pciw_i2pAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2121: Assignment to pciw_i2pAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2122: Assignment to infLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2123: Assignment to blinkLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2545: Assignment to pciw_pcie_irq_rMMEnabled ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Input port gmii_col_i is not connected on this instance +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v". +WARNING:Xst:2898 - Port 'gmii_col_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_crs_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_intr_i', unconnected in block instance 'ftop', is tied to GND. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1343: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1343: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1875: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 82-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 82-bit register for signal . + Found 32-bit adder for signal created at line 2126. + Found 1-bit comparator equal for signal created at line 2012 + Found 1-bit comparator equal for signal created at line 2306 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 538 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkAXBLUART.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 766. + Found 2-bit subtractor for signal created at line 768. + Found 6-bit subtractor for signal created at line 772. + Found 2-bit adder for signal created at line 515. + Found 2-bit adder for signal created at line 526. + Found 6-bit adder for signal created at line 714. + Found 64x8-bit Read Only RAM for signal + Summary: + inferred 1 RAM(s). + inferred 6 Adder/Subtractor(s). + inferred 211 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 72 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 36-bit register for signal . + Found 36-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 74 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBLUART.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit adder for signal created at line 264. + Found 16-bit adder for signal created at line 285. + Found 4-bit adder for signal created at line 294. + Found 16-bit adder for signal created at line 327. + Found 1-bit 10-to-1 multiplexer for signal created at line 302. + Found 16-bit comparator equal for signal created at line 244 + Found 16-bit comparator greater for signal created at line 285 + Found 16-bit comparator equal for signal created at line 328 + Found 16-bit comparator greater for signal created at line 329 + Found 16-bit comparator equal for signal created at line 338 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 68 D-type flip-flop(s). + inferred 5 Comparator(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x8-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 15 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1201: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 3-bit register for signal . + Found 2-bit subtractor for signal created at line 2082. + Found 2-bit subtractor for signal created at line 2200. + Found 2-bit subtractor for signal created at line 2534. + Found 32-bit adder for signal created at line 1415. + Found 32-bit adder for signal created at line 1416. + Found 2-bit adder for signal created at line 1422. + Found 2-bit adder for signal created at line 2081. + Found 32-bit adder for signal created at line 2168. + Found 32-bit adder for signal created at line 2187. + Found 2-bit adder for signal created at line 2199. + Found 32-bit adder for signal created at line 2225. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2496. + Found 3-bit adder for signal created at line 2496. + Found 3-bit adder for signal created at line 2504. + Found 3-bit adder for signal created at line 2504. + Found 14-bit adder for signal created at line 2512. + Found 3-bit adder for signal created at line 2515. + Found 3-bit adder for signal created at line 2535. + Found 3-bit adder for signal created at line 2536. + Found 4x3-bit Read Only RAM for signal <_n1537> + Found 1-bit 4-to-1 multiplexer for signal created at line 2566. + Found 32-bit 4-to-1 multiplexer for signal created at line 2621. + Found 1-bit 4-to-1 multiplexer for signal created at line 2646. + Found 1-bit 4-to-1 multiplexer for signal created at line 2671. + Found 34-bit 8-to-1 multiplexer for signal <_n1601> created at line 866. + Found 2-bit comparator greater for signal created at line 943 + Found 2-bit comparator greater for signal created at line 1505 + Found 1-bit comparator not equal for signal created at line 2084 + Found 1-bit comparator not equal for signal created at line 2202 + Found 3-bit comparator greater for signal created at line 2452 + Found 3-bit comparator greater for signal created at line 2454 + Found 3-bit comparator greater for signal created at line 2455 + Found 3-bit comparator greater for signal created at line 2456 + Found 3-bit comparator greater for signal created at line 2457 + Found 32-bit comparator greater for signal created at line 2476 + Found 32-bit comparator greater for signal created at line 2511 + Found 3-bit comparator greater for signal created at line 2569 + Found 3-bit comparator greater for signal created at line 2572 + Found 3-bit comparator greater for signal created at line 2575 + Found 3-bit comparator greater for signal created at line 2578 + Found 3-bit comparator greater for signal created at line 2610 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 347 D-type flip-flop(s). + inferred 16 Comparator(s). + inferred 22 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 1024x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 77 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCTop16B.v". +WARNING:Xst:2898 - Port 'EN_uuid', unconnected in block instance 'inf', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCApp16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit subtractor for signal created at line 818. + Found 32-bit subtractor for signal created at line 1002. + Found 2-bit subtractor for signal created at line 1104. + Found 32-bit subtractor for signal created at line 1337. + Found 2-bit subtractor for signal created at line 1391. + Found 2-bit subtractor for signal created at line 1392. + Found 2-bit subtractor for signal created at line 1393. + Found 2-bit adder for signal created at line 824. + Found 2-bit adder for signal created at line 854. + Found 2-bit adder for signal created at line 865. + Found 32-bit adder for signal created at line 960. + Found 32-bit adder for signal created at line 966. + Found 32-bit adder for signal created at line 970. + Found 32-bit adder for signal > created at line 1011. + Found 32-bit adder for signal > created at line 1012. + Found 32-bit adder for signal > created at line 1013. + Found 32-bit adder for signal > created at line 1014. + Found 32-bit adder for signal created at line 1024. + Found 2-bit adder for signal created at line 1103. + Found 32-bit adder for signal > created at line 1176. + Found 32-bit adder for signal > created at line 1177. + Found 32-bit adder for signal > created at line 1178. + Found 32-bit adder for signal > created at line 1179. + Found 32-bit adder for signal created at line 1183. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1191. + Found 4x3-bit Read Only RAM for signal <_n1569> + Found 34-bit 13-to-1 multiplexer for signal <_n1657> created at line 525. + Found 2-bit comparator greater for signal created at line 573 + Found 1-bit comparator not equal for signal created at line 1106 + Found 128-bit comparator not equal for signal created at line 1368 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 25 Adder/Subtractor(s). + inferred 1201 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 264 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2038> + Found 34-bit 24-to-1 multiplexer for signal <_n2111> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x169-bit dual-port RAM for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 338 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x169-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 174 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit subtractor for signal created at line 808. + Found 2-bit subtractor for signal created at line 998. + Found 2-bit subtractor for signal created at line 1245. + Found 2-bit subtractor for signal created at line 1318. + Found 2-bit adder for signal created at line 777. + Found 2-bit adder for signal created at line 809. + Found 2-bit adder for signal created at line 997. + Found 32-bit adder for signal created at line 1085. + Found 32-bit adder for signal created at line 1101. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1213. + Found 32-bit adder for signal created at line 1232. + Found 2-bit adder for signal created at line 1244. + Found 32-bit adder for signal created at line 1271. + Found 32-bit adder for signal > created at line 1321. + Found 32-bit adder for signal > created at line 1322. + Found 32-bit adder for signal > created at line 1323. + Found 32-bit adder for signal > created at line 1324. + Found 4x3-bit Read Only RAM for signal <_n0683> + Found 34-bit 15-to-1 multiplexer for signal <_n0763> created at line 537. + Found 2-bit comparator greater for signal created at line 579 + Found 2-bit comparator greater for signal created at line 866 + Found 1-bit comparator not equal for signal created at line 1000 + Found 1-bit comparator not equal for signal created at line 1247 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 16 Adder/Subtractor(s). + inferred 710 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2042> + Found 34-bit 24-to-1 multiplexer for signal <_n2108> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkUUID.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit comparator not equal for signal created at line 68 + Found 1-bit comparator equal for signal created at line 69 + Summary: + inferred 6 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCInf16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2041: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2484: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2484: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCCP.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5398: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5417: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5436: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5455: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5474: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5493: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5512: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5531: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5550: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5569: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5588: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5607: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5626: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5645: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5664: Output port of the instance is unconnected or connected to loadless signal. + Found 65-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 57-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 64-bit subtractor for signal created at line 10957. + Found 50-bit subtractor for signal created at line 11922. + Found 28-bit subtractor for signal created at line 12027. + Found 50-bit subtractor for signal <_281474976710656_MINUS_timeServ_delSecond__q1> created at line 17283. + Found 4-bit subtractor for signal created at line 17480. + Found 4-bit subtractor for signal created at line 17481. + Found 32-bit adder for signal created at line 9361. + Found 1-bit adder for signal created at line 9383. + Found 1-bit adder for signal created at line 9462. + Found 1-bit adder for signal created at line 9539. + Found 1-bit adder for signal created at line 9616. + Found 1-bit adder for signal created at line 9693. + Found 1-bit adder for signal created at line 9770. + Found 1-bit adder for signal created at line 9846. + Found 1-bit adder for signal created at line 9922. + Found 1-bit adder for signal created at line 9998. + Found 1-bit adder for signal created at line 10074. + Found 1-bit adder for signal created at line 10150. + Found 1-bit adder for signal created at line 10226. + Found 1-bit adder for signal created at line 10302. + Found 1-bit adder for signal created at line 10378. + Found 1-bit adder for signal created at line 10454. + Found 7-bit adder for signal created at line 11846. + Found 50-bit adder for signal created at line 11929. + Found 8-bit adder for signal created at line 11968. + Found 28-bit adder for signal created at line 12015. + Found 28-bit adder for signal created at line 12037. + Found 28-bit adder for signal created at line 12044. + Found 3-bit adder for signal created at line 17325. + Found 3-bit adder for signal created at line 17325. + Found 32-bit adder for signal created at line 17514. + Found 32-bit adder for signal created at line 17515. + Found 32-bit adder for signal created at line 17516. + Found 32-bit adder for signal created at line 17517. + Found 32-bit adder for signal created at line 17518. + Found 32-bit adder for signal created at line 17519. + Found 32-bit adder for signal created at line 17521. + Found 32-bit adder for signal created at line 17522. + Found 50-bit adder for signal created at line 17526. + Found 32-bit adder for signal created at line 17527. + Found 32-bit adder for signal created at line 17528. + Found 32-bit adder for signal created at line 17529. + Found 32-bit adder for signal created at line 17530. + Found 32-bit adder for signal created at line 17531. + Found 32-bit adder for signal created at line 17532. + Found 32-bit adder for signal created at line 17533. + Found 32-bit adder for signal created at line 17534. + Found 32-bit shifter logical left for signal created at line 4556 + Found 32-bit shifter logical left for signal created at line 4557 + Found 32-bit shifter logical left for signal created at line 4558 + Found 32-bit shifter logical left for signal created at line 4559 + Found 32-bit shifter logical left for signal created at line 4560 + Found 32-bit shifter logical left for signal created at line 4561 + Found 32-bit shifter logical left for signal created at line 4562 + Found 32-bit shifter logical left for signal created at line 4563 + Found 32-bit shifter logical left for signal created at line 4564 + Found 32-bit shifter logical left for signal created at line 4565 + Found 32-bit shifter logical left for signal created at line 4566 + Found 32-bit shifter logical left for signal created at line 4567 + Found 32-bit shifter logical left for signal created at line 4568 + Found 32-bit shifter logical left for signal created at line 4569 + Found 32-bit shifter logical left for signal created at line 4570 + Found 32-bit 16-to-1 multiplexer for signal created at line 17629. + Found 1-bit 16-to-1 multiplexer for signal created at line 17666. + Found 1-bit 16-to-1 multiplexer for signal created at line 17735. + Found 1-bit 16-to-1 multiplexer for signal created at line 17815. + Found 1-bit 16-to-1 multiplexer for signal created at line 17883. + Found 1-bit 16-to-1 multiplexer for signal created at line 17952. + Found 1-bit 16-to-1 multiplexer for signal created at line 18020. + Found 1-bit 16-to-1 multiplexer for signal created at line 18089. + Found 1-bit 16-to-1 multiplexer for signal created at line 18157. + Found 1-bit 16-to-1 multiplexer for signal created at line 18226. + Found 1-bit 16-to-1 multiplexer for signal created at line 18294. + Found 1-bit 16-to-1 multiplexer for signal created at line 18363. + Found 1-bit 16-to-1 multiplexer for signal created at line 18431. + Found 1-bit 16-to-1 multiplexer for signal created at line 18500. + Found 1-bit 16-to-1 multiplexer for signal created at line 18568. + Found 1-bit 16-to-1 multiplexer for signal created at line 18637. + Found 1-bit 16-to-1 multiplexer for signal created at line 18705. + Found 1-bit 16-to-1 multiplexer for signal created at line 18774. + Found 1-bit 16-to-1 multiplexer for signal created at line 18843. + Found 1-bit 16-to-1 multiplexer for signal created at line 18911. + Found 1-bit 16-to-1 multiplexer for signal created at line 18979. + Found 1-bit 16-to-1 multiplexer for signal created at line 19048. + Found 1-bit 16-to-1 multiplexer for signal created at line 19116. + Found 1-bit 16-to-1 multiplexer for signal created at line 19185. + Found 1-bit 16-to-1 multiplexer for signal created at line 19253. + Found 1-bit 16-to-1 multiplexer for signal created at line 19322. + Found 1-bit 16-to-1 multiplexer for signal created at line 19390. + Found 1-bit 16-to-1 multiplexer for signal created at line 19459. + Found 1-bit 16-to-1 multiplexer for signal created at line 19527. + Found 1-bit 16-to-1 multiplexer for signal created at line 19596. + Found 1-bit 16-to-1 multiplexer for signal created at line 19663. + Found 1-bit 16-to-1 multiplexer for signal created at line 19730. + Found 1-bit 16-to-1 multiplexer for signal created at line 19843. + Found 1-bit 16-to-1 multiplexer for signal created at line 20093. + Found 1-bit 16-to-1 multiplexer for signal created at line 20162. + Found 1-bit 16-to-1 multiplexer for signal created at line 20242. + Found 1-bit 16-to-1 multiplexer for signal created at line 20447. + Found 1-bit 16-to-1 multiplexer for signal created at line 20516. + Found 1-bit 16-to-1 multiplexer for signal created at line 20721. + Found 1-bit 16-to-1 multiplexer for signal created at line 20790. + Found 1-bit 16-to-1 multiplexer for signal created at line 20995. + Found 1-bit 16-to-1 multiplexer for signal created at line 21064. + Found 1-bit 16-to-1 multiplexer for signal created at line 21269. + Found 1-bit 16-to-1 multiplexer for signal created at line 21338. + Found 1-bit 16-to-1 multiplexer for signal created at line 21543. + Found 1-bit 16-to-1 multiplexer for signal created at line 21612. + Found 1-bit 16-to-1 multiplexer for signal created at line 21817. + Found 1-bit 16-to-1 multiplexer for signal created at line 21886. + Found 1-bit 16-to-1 multiplexer for signal created at line 22091. + Found 1-bit 16-to-1 multiplexer for signal created at line 22160. + Found 1-bit 16-to-1 multiplexer for signal created at line 22365. + Found 1-bit 16-to-1 multiplexer for signal created at line 22434. + Found 1-bit 16-to-1 multiplexer for signal created at line 22639. + Found 1-bit 16-to-1 multiplexer for signal created at line 22708. + Found 1-bit 16-to-1 multiplexer for signal created at line 22913. + Found 1-bit 16-to-1 multiplexer for signal created at line 22982. + Found 1-bit 16-to-1 multiplexer for signal created at line 23187. + Found 1-bit 16-to-1 multiplexer for signal created at line 23256. + Found 1-bit 16-to-1 multiplexer for signal created at line 23461. + Found 1-bit 16-to-1 multiplexer for signal created at line 23530. + Found 1-bit 16-to-1 multiplexer for signal created at line 23735. + Found 1-bit 16-to-1 multiplexer for signal created at line 23804. + Found 1-bit 16-to-1 multiplexer for signal created at line 24005. + Found 1-bit 16-to-1 multiplexer for signal created at line 24072. + Found 1-bit 16-to-1 multiplexer for signal created at line 24169. + Found 1-bit 16-to-1 multiplexer for signal created at line 24265. + Found 32-bit 16-to-1 multiplexer for signal created at line 24421. + Found 3-bit comparator greater for signal created at line 5814 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 28-bit comparator greater for signal created at line 11964 + Found 2-bit comparator not equal for signal created at line 16408 + Found 8-bit comparator greater for signal created at line 17299 + Found 8-bit comparator greater for signal created at line 17300 + Found 24-bit comparator greater for signal created at line 17302 + Found 24-bit comparator greater for signal created at line 17304 + Found 28-bit comparator greater for signal created at line 17334 + Found 28-bit comparator greater for signal created at line 17342 + Found 28-bit comparator greater for signal created at line 17344 + Found 32-bit comparator greater for signal created at line 17376 + Found 32-bit comparator greater for signal created at line 17383 + Found 32-bit comparator greater for signal created at line 17390 + Found 32-bit comparator greater for signal created at line 17397 + Found 32-bit comparator greater for signal created at line 17404 + Found 32-bit comparator greater for signal created at line 17411 + Found 32-bit comparator greater for signal created at line 17418 + Found 32-bit comparator greater for signal created at line 17425 + Found 32-bit comparator greater for signal created at line 17432 + Found 32-bit comparator greater for signal created at line 17439 + Found 32-bit comparator greater for signal created at line 17446 + Found 32-bit comparator greater for signal created at line 17453 + Found 32-bit comparator greater for signal created at line 17460 + Found 32-bit comparator greater for signal created at line 17467 + Found 32-bit comparator greater for signal created at line 17474 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 47 Adder/Subtractor(s). + inferred 4100 D-type flip-flop(s). + inferred 27 Comparator(s). + inferred 299 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM1Load.v". + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x64-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 86 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 30-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 10-bit subtractor for signal created at line 313. + Found 10-bit subtractor for signal created at line 314. + Found 2-bit subtractor for signal created at line 322. + Found 10-bit subtractor for signal created at line 323. + Found 12-bit subtractor for signal created at line 490. + Found 12-bit subtractor for signal created at line 522. + Found 2-bit adder for signal created at line 319. + Found 30-bit adder for signal created at line 321. + Found 2-bit subtractor for signal > created at line 203. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n0624> + Found 4x2-bit Read Only RAM for signal <_n0642> + Found 4x2-bit Read Only RAM for signal <_n0661> + Found 32-bit 4-to-1 multiplexer for signal created at line 548. + Summary: + inferred 4 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 283 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 56-bit register for signal . + Found 56-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 114 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 308 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 10-bit subtractor for signal created at line 3265. + Found 10-bit subtractor for signal created at line 3268. + Found 10-bit subtractor for signal created at line 3269. + Found 10-bit subtractor for signal created at line 3271. + Found 10-bit subtractor for signal created at line 3275. + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3306. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 17-bit adder for signal created at line 3296. + Found 17-bit adder for signal created at line 3298. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 5-bit adder for signal created at line 4548. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6690. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1969. + Found 2-bit subtractor for signal created at line 1973. + Found 4x16-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal <_n4159> + Found 4x2-bit Read Only RAM for signal <_n4179> + Found 4x2-bit Read Only RAM for signal <_n4371> + Found 4x2-bit Read Only RAM for signal <_n4390> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4473> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 8-bit comparator equal for signal created at line 6489 + Found 17-bit comparator lessequal for signal created at line 6519 + Found 13-bit comparator lessequal for signal created at line 6673 + Found 10-bit comparator greater for signal created at line 6677 + Found 10-bit comparator greater for signal created at line 6679 + Found 8-bit comparator equal for signal created at line 6681 + Found 5-bit comparator equal for signal created at line 6682 + Found 3-bit comparator equal for signal created at line 6683 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6818 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 91 Adder/Subtractor(s). + inferred 2516 D-type flip-flop(s). + inferred 34 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 153-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2448-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 153-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2608 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x146-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 151 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3314. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 32-bit adder for signal created at line 3389. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6692. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1969. + Found 2-bit subtractor for signal created at line 1973. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4127> + Found 4x2-bit Read Only RAM for signal <_n4145> + Found 4x2-bit Read Only RAM for signal <_n4171> + Found 4x3-bit Read Only RAM for signal <_n4188> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4427> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 17-bit comparator equal for signal created at line 6658 + Found 13-bit comparator lessequal for signal created at line 6669 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6808 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + Summary: + inferred 5 RAM(s). + inferred 87 Adder/Subtractor(s). + inferred 2502 D-type flip-flop(s). + inferred 28 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTimeClient.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSM.v". + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktFork.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit shifter logical left for signal created at line 107 + Found 7-bit shifter logical left for signal created at line 107 + Found 1-bit 4-to-1 multiplexer for signal created at line 247. + Found 3-bit comparator equal for signal created at line 225 + Found 7-bit comparator equal for signal created at line 226 + Found 1-bit comparator equal for signal created at line 226 + Found 4-bit comparator equal for signal created at line 230 + Found 8-bit comparator equal for signal created at line 237 + Found 7-bit comparator equal for signal created at line 250 + Summary: + inferred 2 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 4 Multiplexer(s). + inferred 2 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktMerge.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1243: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1400: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit subtractor for signal created at line 1970. + Found 2-bit subtractor for signal created at line 2547. + Found 2-bit subtractor for signal created at line 2554. + Found 2-bit adder for signal created at line 1639. + Found 8-bit adder for signal created at line 1676. + Found 8-bit adder for signal created at line 1676. + Found 2-bit adder for signal created at line 1679. + Found 16-bit adder for signal created at line 1835. + Found 16-bit adder for signal created at line 1840. + Found 8-bit adder for signal created at line 1900. + Found 32-bit adder for signal created at line 1910. + Found 2-bit adder for signal created at line 1969. + Found 32-bit adder for signal created at line 2065. + Found 32-bit adder for signal created at line 2071. + Found 32-bit adder for signal created at line 2085. + Found 4x3-bit Read Only RAM for signal <_n1796> + Found 32-bit 39-to-1 multiplexer for signal <_n1787> created at line 886. + Found 34-bit 4-to-1 multiplexer for signal created at line 855. + Found 2-bit comparator greater for signal created at line 959 + Found 1-bit comparator not equal for signal created at line 1972 + Found 8-bit comparator greater for signal created at line 2317 + Found 8-bit comparator greater for signal created at line 2549 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 849 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 161 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 5-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 10 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 24-bit register for signal . + Found 24-bit register for signal . + Summary: + inferred 48 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x177-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 199 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x128-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 150 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v". +WARNING:Xst:2898 - Port 'dbg_wr_dqs_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_dq_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'pd_PSDONE', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_tap_set_en', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_inc_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_dec_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 334: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "syn_maxfan = 10" for signal . + Found 31-bit register for signal . + Summary: + inferred 31 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v". + Set property "syn_maxfan = 10" for signal . + Set property "syn_maxfan = 10" for signal . + Found 33-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 612: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'dfi_dram_clk_disable', unconnected in block 'mc', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'dfi_reset_n', unconnected in block 'mc', is tied to its initial value (1). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v". +WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 206. + Found 3-bit subtractor for signal created at line 267. + Found 4-bit subtractor for signal created at line 326. + Found 3-bit subtractor for signal created at line 385. + Found 3-bit adder for signal created at line 205. + Found 4-bit adder for signal created at line 329. + Found 3-bit comparator lessequal for signal created at line 271 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 17 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 6 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 236: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 321: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit subtractor for signal created at line 122. + Found 6-bit subtractor for signal created at line 147. + Found 20-bit subtractor for signal created at line 175. + Found 1-bit adder for signal created at line 267. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 43 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_col_r<10>', unconnected in block 'bank_compare', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 280 + Found 3-bit comparator equal for signal created at line 221 + Found 13-bit comparator equal for signal created at line 230 + Summary: + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 7 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 8 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'bank_common', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 2-bit subtractor for signal created at line 393. + Found 6-bit subtractor for signal created at line 430. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 18 Adder/Subtractor(s). + inferred 21 D-type flip-flop(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 159: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 185: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 235: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'arb_row_col', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'arb_row_col', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'row_mux.row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:2935 - Signal 'col_mux.col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 349 + Found 1-bit shifter logical left for signal > created at line 351 + Found 1-bit shifter logical left for signal created at line 390 + Summary: + inferred 13 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 3 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 11-bit register for signal >. + Found 1-bit register for signal >. + Found 11-bit register for signal . + Found 3-bit subtractor for signal created at line 260. + Found 2-bit subtractor for signal created at line 280. + Found 5-bit adder for signal created at line 377. + Found 5-bit adder for signal created at line 386. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 45 D-type flip-flop(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1131: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v". +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst - Value "0" of property "syn_replicate" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 256-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:1799 - State 011110 is never reached in FSM . +INFO:Xst:1799 - State 100101 is never reached in FSM . +INFO:Xst:1799 - State 100100 is never reached in FSM . +INFO:Xst:1799 - State 100111 is never reached in FSM . +INFO:Xst:1799 - State 011101 is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 86 | + | Inputs | 31 | + | Outputs | 43 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit subtractor for signal created at line 1560. + Found 7-bit adder for signal created at line 854. + Found 10-bit adder for signal created at line 879. + Found 9-bit adder for signal created at line 888. + Found 8-bit adder for signal created at line 935. + Found 8-bit adder for signal created at line 966. + Found 2-bit adder for signal created at line 987. + Found 2-bit adder for signal created at line 1038. + Found 3-bit adder for signal created at line 1051. + Found 2-bit adder for signal created at line 1561. + Found 2-bit adder for signal created at line 1573. + Found 2-bit adder for signal created at line 1657. + Found 4-bit adder for signal created at line 1735. + Found 5-bit subtractor for signal > created at line 764. + Found 16x256-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal + Found 2-bit comparator greater for signal created at line 1208 + Found 32-bit comparator not equal for signal created at line 1560 + Found 2-bit comparator greater for signal created at line 1597 + WARNING:Xst:2404 - FFs/Latches <7:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:2>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <2:10>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 468 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 21 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v". + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_keep = 1" for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 D-type flip-flop(s). + inferred 17 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v". + Set property "syn_maxfan = 1" for signal . + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 6-bit register for signal . + Found 6-bit register for signal . + Summary: + inferred 12 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal created at line 109. + Found 4-bit 4-to-1 multiplexer for signal created at line 133. + Summary: + inferred 17 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Summary: + inferred 14 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Summary: + inferred 26 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 108 D-type flip-flop(s). + inferred 124 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 2-bit adder for signal created at line 1634. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 137 D-type flip-flop(s). + inferred 146 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 40-bit register for signal >. + Found 16-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal >. + Found 40-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <9>>. + Found 1-bit register for signal <8>>. + Found 1-bit register for signal <7>>. + Found 1-bit register for signal <6>>. + Found 1-bit register for signal <5>>. + Found 1-bit register for signal <14>>. + Found 1-bit register for signal <13>>. + Found 1-bit register for signal <12>>. + Found 1-bit register for signal <11>>. + Found 1-bit register for signal <10>>. + Found 1-bit register for signal <19>>. + Found 1-bit register for signal <18>>. + Found 1-bit register for signal <17>>. + Found 1-bit register for signal <16>>. + Found 1-bit register for signal <15>>. + Found 1-bit register for signal <24>>. + Found 1-bit register for signal <23>>. + Found 1-bit register for signal <22>>. + Found 1-bit register for signal <21>>. + Found 1-bit register for signal <20>>. + Found 1-bit register for signal <29>>. + Found 1-bit register for signal <28>>. + Found 1-bit register for signal <27>>. + Found 1-bit register for signal <26>>. + Found 1-bit register for signal <25>>. + Found 1-bit register for signal <34>>. + Found 1-bit register for signal <33>>. + Found 1-bit register for signal <32>>. + Found 1-bit register for signal <31>>. + Found 1-bit register for signal <30>>. + Found 1-bit register for signal <39>>. + Found 1-bit register for signal <38>>. + Found 1-bit register for signal <37>>. + Found 1-bit register for signal <36>>. + Found 1-bit register for signal <35>>. + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal >. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 23 | + | Inputs | 10 | + | Outputs | 11 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 541. + Found 4-bit subtractor for signal created at line 581. + Found 2-bit adder for signal created at line 284. + Found 2-bit adder for signal created at line 298. + Found 5-bit adder for signal created at line 492. + Found 4-bit adder for signal created at line 566. + Found 4-bit adder for signal created at line 567. + Found 4-bit adder for signal created at line 568. + Found 2-bit adder for signal created at line 586. + Found 5-bit adder for signal created at line 641. + Found 3x4-bit multiplier for signal created at line 408. + Found 1-bit 8-to-1 multiplexer for signal created at line 264. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 299. + Found 5-bit 8-to-1 multiplexer for signal created at line 341. + Found 1-bit 8-to-1 multiplexer for signal created at line 512. + Found 1-bit 8-to-1 multiplexer for signal created at line 529. + Found 1-bit 16-to-1 multiplexer for signal created at line 640. + Found 1-bit 16-to-1 multiplexer for signal created at line 641. + Found 1-bit 8-to-1 multiplexer for signal created at line 665. + Found 1-bit 8-to-1 multiplexer for signal created at line 668. + Found 2-bit comparator lessequal for signal created at line 230 + Found 5-bit comparator greater for signal created at line 280 + Found 1-bit comparator equal for signal created at line 282 + Found 2-bit comparator greater for signal created at line 283 + Found 1-bit comparator equal for signal created at line 295 + Found 2-bit comparator greater for signal created at line 297 + Found 4-bit comparator lessequal for signal created at line 341 + Found 2-bit comparator lessequal for signal created at line 341 + Found 5-bit comparator greater for signal created at line 530 + Found 5-bit comparator greater for signal created at line 543 + Found 4-bit comparator lessequal for signal created at line 549 + Found 32-bit comparator equal for signal created at line 581 + Found 5-bit comparator lessequal for signal created at line 673 + Summary: + inferred 1 Multiplier(s). + inferred 10 Adder/Subtractor(s). + inferred 351 D-type flip-flop(s). + inferred 13 Comparator(s). + inferred 163 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 11 | + | Inputs | 4 | + | Outputs | 27 | + | Clock | clk (rising_edge) | + | Reset | rst_oserdes (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit adder for signal created at line 310. + Found 4-bit adder for signal created at line 324. + Found 4-bit adder for signal created at line 331. + Found 4-bit adder for signal created at line 339. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 81 D-type flip-flop(s). + inferred 8 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 256-bit register for signal . + Summary: + inferred 288 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v". + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 5-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 3-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 42 | + | Inputs | 18 | + | Outputs | 18 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 10 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 6 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 15 | + | Inputs | 9 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 1284. + Found 6-bit subtractor for signal created at line 1297. + Found 6-bit subtractor for signal created at line 1395. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 4-bit adder for signal created at line 647. + Found 4-bit adder for signal created at line 707. + Found 12-bit adder for signal created at line 918. + Found 12-bit adder for signal created at line 946. + Found 3-bit adder for signal created at line 1025. + Found 5-bit adder for signal created at line 1046. + Found 31-bit adder for signal created at line 1284. + Found 6-bit adder for signal created at line 1290. + Found 32-bit adder for signal created at line 1297. + Found 3-bit adder for signal created at line 1343. + Found 5-bit adder for signal created at line 1413. + Found 7-bit adder for signal created at line 1480. + Found 32-bit adder for signal created at line 1541. + Found 6-bit adder for signal created at line 1543. + Found 3-bit adder for signal created at line 1650. + Found 5-bit adder for signal created at line 1784. + Found 3-bit adder for signal created at line 1880. + Found 5-bit adder for signal created at line 1974. + Found 2-bit adder for signal created at line 1984. + Found 3-bit adder for signal created at line 1996. + Found 3-bit adder for signal created at line 2037. + Found 5-bit subtractor for signal > created at line 1048. + Found 6-bit subtractor for signal > created at line 1293. + Found 6-bit subtractor for signal > created at line 1372. + Found 5-bit subtractor for signal > created at line 1479. + Found 5-bit subtractor for signal > created at line 1483. + Found 5-bit subtractor for signal > created at line 1497. + Found 5-bit subtractor for signal > created at line 1525. + Found 5-bit subtractor for signal > created at line 1809. + Found 5-bit subtractor for signal > created at line 2091. + Found 3x3-bit multiplier for signal created at line 599. + Found 30-bit shifter logical right for signal created at line 1996 + Found 3x3-bit multiplier for signal created at line 2021. + Found 3-bit 3-to-1 multiplexer for signal created at line 490. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 5-bit comparator lessequal for signal created at line 1289 + Found 6-bit comparator greater for signal created at line 1290 + Found 3-bit comparator greater for signal created at line 1336 + Found 6-bit comparator greater for signal created at line 1383 + Found 6-bit comparator lessequal for signal created at line 1478 + Found 7-bit comparator lessequal for signal created at line 1480 + Found 5-bit comparator lessequal for signal created at line 1756 + Found 3-bit comparator greater for signal created at line 1872 + Found 5-bit comparator lessequal for signal created at line 2013 + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 Multiplier(s). + inferred 44 Adder/Subtractor(s). + inferred 870 D-type flip-flop(s). + inferred 73 Comparator(s). + inferred 232 Multiplexer(s). + inferred 1 Combinational logic shifter(s). + inferred 3 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 9 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 416. + Found 6-bit adder for signal created at line 502. + Found 16-bit adder for signal created at line 536. + Found 16-bit adder for signal created at line 546. + Found 4-bit adder for signal created at line 593. + Found 4-bit subtractor for signal created at line 184. + Found 5-bit subtractor for signal > created at line 417. + Found 1-bit 16-to-1 multiplexer for signal created at line 203. + Found 1-bit 16-to-1 multiplexer for signal created at line 205. + Found 1-bit 16-to-1 multiplexer for signal created at line 232. + Found 1-bit 16-to-1 multiplexer for signal created at line 233. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 67 D-type flip-flop(s). + inferred 12 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 11 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v". + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 256-bit register for signal . + Found 5-bit subtractor for signal created at line 376. + Found 4-bit adder for signal created at line 232. + Found 4-bit adder for signal created at line 252. + Found 4-bit adder for signal created at line 283. + Found 5-bit adder for signal created at line 377. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 339 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal created at line 224. + Found 6-bit adder for signal created at line 183. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 11 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 2-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 41 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 177-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 356 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2048-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 128-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2183 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 294 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 106 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFlashWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" line 586: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 84 | + | Inputs | 8 | + | Outputs | 8 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_186_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 25 | + | Transitions | 299 | + | Inputs | 11 | + | Outputs | 25 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_186_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1428. + Found 2-bit subtractor for signal created at line 1565. + Found 2-bit adder for signal created at line 906. + Found 2-bit adder for signal created at line 1427. + Found 4x3-bit Read Only RAM for signal <_n0852> + Found 32-bit 7-to-1 multiplexer for signal <_n0844> created at line 508. + Found 2-bit comparator greater for signal created at line 528 + Found 1-bit comparator not equal for signal created at line 1430 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 3 Adder/Subtractor(s). + inferred 315 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 41-bit register for signal . + Found 41-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFMC150.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 820: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 891: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 956: Output port of the instance is unconnected or connected to loadless signal. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 33-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 5-bit subtractor for signal created at line 1185. + Found 6-bit subtractor for signal created at line 1188. + Found 3-bit subtractor for signal created at line 1194. + Found 3-bit subtractor for signal created at line 1196. + Found 18-bit subtractor for signal created at line 1400. + Found 2-bit subtractor for signal created at line 1698. + Found 5-bit subtractor for signal <_31_MINUS_spiCDC_dPos_29___d230> created at line 1855. + Found 2-bit subtractor for signal created at line 1920. + Found 5-bit subtractor for signal created at line 1922. + Found 18-bit adder for signal created at line 1183. + Found 2-bit adder for signal created at line 1213. + Found 2-bit adder for signal created at line 1697. + Found 18-bit shifter logical left for signal created at line 708 + Found 4x3-bit Read Only RAM for signal <_n1004> + Found 1-bit 18-to-1 multiplexer for signal created at line 1179. + Found 1-bit 8-to-1 multiplexer for signal created at line 1207. + Found 1-bit 28-to-1 multiplexer for signal created at line 1921. + Found 1-bit 4-to-1 multiplexer for signal <_n0986> created at line 701. + Found 1-bit 4-to-1 multiplexer for signal <_n0996> created at line 700. + Found 2-bit comparator greater for signal created at line 782 + Found 1-bit comparator equal for signal created at line 969 + Found 1-bit comparator equal for signal created at line 976 + Found 1-bit comparator equal for signal created at line 1056 + Found 1-bit comparator not equal for signal created at line 1700 + Found 1-bit comparator equal for signal created at line 1848 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 11 Adder/Subtractor(s). + inferred 367 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 39 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 106. + Found 3-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetEither.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncReset0.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 106. + Found 4-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGbeWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1447: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1459: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1503: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1517: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 22-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 16 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_221_o_equal_658_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1793. + Found 22-bit subtractor for signal created at line 2096. + Found 2-bit subtractor for signal created at line 2320. + Found 2-bit subtractor for signal created at line 2964. + Found 5-bit subtractor for signal created at line 2966. + Found 5-bit subtractor for signal created at line 2967. + Found 5-bit subtractor for signal created at line 2968. + Found 5-bit adder for signal created at line 1745. + Found 4-bit adder for signal created at line 1746. + Found 4-bit adder for signal created at line 1748. + Found 2-bit adder for signal created at line 1756. + Found 32-bit adder for signal created at line 2101. + Found 32-bit adder for signal created at line 2108. + Found 32-bit adder for signal created at line 2141. + Found 32-bit adder for signal created at line 2146. + Found 32-bit adder for signal created at line 2211. + Found 32-bit adder for signal created at line 2225. + Found 32-bit adder for signal created at line 2229. + Found 32-bit adder for signal created at line 2262. + Found 2-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2407. + Found 32-bit adder for signal created at line 2423. + Found 5-bit adder for signal created at line 2957. + Found 32-bit adder for signal created at line 2965. + Found 4x3-bit Read Only RAM for signal <_n2228> + Found 4x10-bit Read Only RAM for signal <_n2473> + Found 256x2-bit Read Only RAM for signal <_n2867> + Found 8-bit 15-to-1 multiplexer for signal created at line 3010. + Found 8-bit 15-to-1 multiplexer for signal created at line 3059. + Found 8-bit 15-to-1 multiplexer for signal <_n2358> created at line 1132. + Found 8-bit 15-to-1 multiplexer for signal <_n2387> created at line 3108. + Found 8-bit 15-to-1 multiplexer for signal <_n2420> created at line 1131. + Found 34-bit 32-to-1 multiplexer for signal <_n2484> created at line 1093. + Found 2-bit comparator greater for signal created at line 1245 + Found 4-bit comparator greater for signal created at line 1748 + Found 22-bit comparator greater for signal created at line 2098 + Found 32-bit comparator greater for signal created at line 2200 + Found 1-bit comparator not equal for signal created at line 2322 + Found 8-bit comparator greater for signal created at line 2782 + Found 8-bit comparator equal for signal created at line 2810 + Found 8-bit comparator equal for signal created at line 2875 + Found 8-bit comparator equal for signal created at line 2877 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 3 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 1539 D-type flip-flop(s). + inferred 9 Comparator(s). + inferred 100 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGMAC.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 5-bit subtractor for signal created at line 995. + Found 3-bit subtractor for signal created at line 1397. + Found 4-bit adder for signal created at line 971. + Found 12-bit adder for signal created at line 999. + Found 5-bit adder for signal created at line 1003. + Found 8-bit 4-to-1 multiplexer for signal <_n0420> created at line 518. + Found 32-bit comparator not equal for signal created at line 975 + Found 4-bit comparator greater for signal created at line 1136 + Found 12-bit comparator greater for signal created at line 1394 + Found 5-bit comparator greater for signal created at line 1396 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 Adder/Subtractor(s). + inferred 113 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCRC32.v". + Found 32-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator not equal for signal created at line 127 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 48 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 16x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 5-bit comparator not equal for signal created at line 126 + Found 5-bit comparator not equal for signal created at line 127 + Found 5-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 56 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal created at line 50 + Summary: + inferred 1 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 112-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 226 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkLCDController.v". + Found 2-bit register for signal . + Found 24-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 15 | + | Inputs | 12 | + | Outputs | 2 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 61 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 140 | + | Transitions | 4472 | + | Inputs | 18 | + | Outputs | 139 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 24-bit subtractor for signal created at line 1550. + Found 8-bit adder for signal created at line 1551. + Found 5-bit adder for signal created at line 1594. + Found 4-bit adder for signal created at line 1595. + Found 8-bit 16-to-1 multiplexer for signal <_n1469> created at line 443. + Found 8-bit 16-to-1 multiplexer for signal <_n1503> created at line 443. + Found 5-bit comparator greater for signal created at line 2925 + Found 4-bit comparator greater for signal created at line 2938 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 330 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 11 Multiplexer(s). + inferred 5 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x81-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 81-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 88 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v". + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 709: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 99. + Found 8-bit adder for signal created at line 100. + Found 8-bit adder for signal created at line 101. + Summary: + inferred 3 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 8 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" line 254: Output port of the instance is unconnected or connected to loadless signal. + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 4-bit subtractor for signal created at line 484. + Found 5-bit adder for signal created at line 464. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 20 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | drp_clk (rising_edge) | + | Reset | Reset_n (negative) | + | Reset type | synchronous | + | Reset State | 0011 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 180. + Found 16x32-bit Read Only RAM for signal <_n0098> + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 10 D-type flip-flop(s). + inferred 7 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v". + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 26 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 00001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 14 | + | Inputs | 7 | + | Outputs | 4 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 308. + Found 4-bit adder for signal created at line 328. + Found 4-bit adder for signal created at line 360. + Found 5-bit comparator greater for signal created at line 283 + Found 4-bit comparator lessequal for signal created at line 356 + Summary: + inferred 3 Adder/Subtractor(s). + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 7 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 21 | + | Transitions | 40 | + | Inputs | 10 | + | Outputs | 21 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0000000000000100000000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 179. + Found 8-bit adder for signal created at line 180. + Found 1-bit comparator equal for signal created at line 534 + Summary: + inferred 2 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 19 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x8-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 41 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWmemiTap.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" line 760: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 2-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 2-bit register for signal . + Found 36-bit register for signal . + Found 36-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 1673. + Found 2-bit subtractor for signal created at line 1675. + Found 2-bit subtractor for signal created at line 1677. + Found 2-bit subtractor for signal created at line 1678. + Found 2-bit subtractor for signal created at line 1683. + Found 2-bit subtractor for signal created at line 1684. + Found 2-bit adder for signal created at line 981. + Found 2-bit adder for signal created at line 993. + Found 2-bit adder for signal created at line 1003. + Found 2-bit adder for signal created at line 1014. + Found 2-bit adder for signal created at line 1025. + Found 2-bit adder for signal created at line 1040. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 886 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port RAM : 5 + 1024x32-bit single-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 16x256-bit single-port Read Only RAM : 1 + 16x32-bit single-port Read Only RAM : 4 + 2048x169-bit dual-port RAM : 2 + 2048x32-bit dual-port RAM : 8 + 256x2-bit single-port Read Only RAM : 1 + 2x128-bit dual-port RAM : 1 + 2x146-bit dual-port RAM : 2 + 2x169-bit dual-port RAM : 3 + 2x177-bit dual-port RAM : 1 + 2x32-bit dual-port RAM : 26 + 2x61-bit dual-port RAM : 2 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 11 + 3x8-bit dual-port RAM : 1 + 3x81-bit dual-port RAM : 2 + 4x10-bit single-port Read Only RAM : 1 + 4x16-bit single-port Read Only RAM : 3 + 4x2-bit single-port Read Only RAM : 9 + 4x3-bit single-port Read Only RAM : 12 + 64x8-bit single-port Read Only RAM : 1 + 8x10-bit dual-port RAM : 1 + 8x8-bit dual-port RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 834 + 1-bit adder : 120 + 10-bit adder : 1 + 10-bit subtractor : 16 + 11-bit adder : 2 + 12-bit adder : 15 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 7 + 14-bit subtractor : 6 + 16-bit adder : 36 + 16-bit addsub : 8 + 16-bit subtractor : 6 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit adder : 1 + 18-bit subtractor : 1 + 2-bit adder : 45 + 2-bit addsub : 52 + 2-bit subtractor : 80 + 20-bit subtractor : 1 + 22-bit subtractor : 1 + 24-bit adder : 2 + 24-bit subtractor : 1 + 28-bit adder : 3 + 28-bit subtractor : 1 + 3-bit adder : 64 + 3-bit subtractor : 11 + 30-bit adder : 1 + 31-bit adder : 1 + 32-bit adder : 100 + 32-bit subtractor : 3 + 4-bit adder : 31 + 4-bit addsub : 26 + 4-bit subtractor : 35 + 5-bit adder : 46 + 5-bit addsub : 4 + 5-bit subtractor : 21 + 50-bit adder : 2 + 50-bit subtractor : 2 + 6-bit adder : 12 + 6-bit subtractor : 10 + 64-bit subtractor : 1 + 7-bit adder : 3 + 8-bit adder : 23 + 9-bit adder : 1 +# Registers : 5261 + 1-bit register : 3190 + 10-bit register : 17 + 11-bit register : 2 + 112-bit register : 3 + 113-bit register : 2 + 12-bit register : 26 + 128-bit register : 12 + 129-bit register : 4 + 13-bit register : 13 + 130-bit register : 12 + 131-bit register : 8 + 139-bit register : 4 + 14-bit register : 16 + 146-bit register : 14 + 15-bit register : 5 + 153-bit register : 28 + 16-bit register : 106 + 169-bit register : 13 + 17-bit register : 20 + 177-bit register : 3 + 18-bit register : 7 + 182-bit register : 2 + 2-bit register : 309 + 20-bit register : 2 + 2048-bit register : 1 + 22-bit register : 1 + 24-bit register : 4 + 2448-bit register : 22 + 256-bit register : 3 + 27-bit register : 4 + 28-bit register : 24 + 3-bit register : 162 + 30-bit register : 1 + 31-bit register : 1 + 32-bit register : 249 + 33-bit register : 22 + 34-bit register : 41 + 35-bit register : 8 + 36-bit register : 4 + 4-bit register : 393 + 40-bit register : 34 + 41-bit register : 2 + 45-bit register : 5 + 48-bit register : 2 + 5-bit register : 105 + 50-bit register : 5 + 52-bit register : 8 + 56-bit register : 2 + 57-bit register : 1 + 59-bit register : 12 + 6-bit register : 160 + 61-bit register : 8 + 64-bit register : 19 + 65-bit register : 1 + 67-bit register : 6 + 7-bit register : 5 + 72-bit register : 26 + 79-bit register : 2 + 8-bit register : 91 + 81-bit register : 2 + 82-bit register : 2 + 9-bit register : 5 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 3385 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 71 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 1389 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 24 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 43 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 16 + 128-bit 16-to-1 multiplexer : 1 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 16 + 15-bit 2-to-1 multiplexer : 1 + 153-bit 16-to-1 multiplexer : 22 + 16-bit 2-to-1 multiplexer : 56 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 16-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 104 + 20-bit 2-to-1 multiplexer : 13 + 22-bit 2-to-1 multiplexer : 1 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 132 + 3-bit 3-to-1 multiplexer : 1 + 30-bit 2-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 320 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 50 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 32-to-1 multiplexer : 1 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 35-bit 2-to-1 multiplexer : 4 + 36-bit 2-to-1 multiplexer : 2 + 4-bit 2-to-1 multiplexer : 76 + 4-bit 4-to-1 multiplexer : 144 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 146 + 5-bit 8-to-1 multiplexer : 1 + 50-bit 2-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 5 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 86 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 5 + 8-bit 16-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 131 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 7 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 32-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 8-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 169-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 169-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 146-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 146-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 81-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 81-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 177-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 177-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 128-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 128-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 8-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 64-word x 8-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 10-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 256-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port block RAM : 5 + 1024x32-bit single-port block RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 16x256-bit single-port distributed Read Only RAM : 1 + 16x32-bit single-port distributed Read Only RAM : 4 + 2048x169-bit dual-port block RAM : 2 + 2048x32-bit dual-port block RAM : 8 + 256x2-bit single-port distributed Read Only RAM : 1 + 2x128-bit dual-port distributed RAM : 1 + 2x146-bit dual-port distributed RAM : 2 + 2x169-bit dual-port distributed RAM : 3 + 2x177-bit dual-port distributed RAM : 1 + 2x32-bit dual-port distributed RAM : 26 + 2x61-bit dual-port distributed RAM : 2 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 11 + 3x8-bit dual-port distributed RAM : 1 + 3x81-bit dual-port distributed RAM : 2 + 4x10-bit single-port distributed Read Only RAM : 1 + 4x16-bit single-port distributed Read Only RAM : 3 + 4x2-bit single-port distributed Read Only RAM : 9 + 4x3-bit single-port distributed Read Only RAM : 12 + 64x8-bit single-port distributed Read Only RAM : 1 + 8x10-bit dual-port distributed RAM : 1 + 8x8-bit dual-port distributed RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 424 + 1-bit adder : 101 + 10-bit subtractor : 15 + 11-bit adder : 2 + 12-bit adder : 4 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 5 + 14-bit subtractor : 4 + 16-bit adder : 13 + 16-bit subtractor : 4 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit subtractor : 1 + 2-bit adder : 22 + 2-bit adder carry in : 1 + 2-bit subtractor : 72 + 24-bit subtractor : 1 + 28-bit subtractor : 1 + 3-bit adder : 3 + 3-bit adder carry in : 1 + 3-bit subtractor : 8 + 32-bit adder : 40 + 32-bit subtractor : 3 + 4-bit adder : 5 + 4-bit subtractor : 30 + 5-bit adder : 4 + 5-bit addsub : 1 + 5-bit subtractor : 17 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 6 + 64-bit subtractor : 1 + 7-bit adder : 2 + 8-bit adder : 12 +# Adder Trees : 3 + 2-bit / 5-inputs adder tree : 1 + 5-bit / 9-inputs adder tree : 2 +# Counters : 402 + 1-bit up counter : 107 + 10-bit down counter : 1 + 10-bit up counter : 1 + 12-bit up counter : 9 + 16-bit down counter : 2 + 16-bit up counter : 23 + 16-bit updown counter : 8 + 18-bit up counter : 1 + 2-bit down counter : 8 + 2-bit up counter : 16 + 2-bit updown counter : 52 + 20-bit down counter : 1 + 22-bit down counter : 1 + 28-bit up counter : 3 + 3-bit down counter : 3 + 3-bit up counter : 15 + 30-bit up counter : 1 + 32-bit up counter : 57 + 4-bit down counter : 5 + 4-bit up counter : 26 + 4-bit updown counter : 26 + 5-bit down counter : 4 + 5-bit up counter : 12 + 5-bit updown counter : 3 + 6-bit down counter : 4 + 6-bit up counter : 2 + 7-bit up counter : 2 + 8-bit up counter : 8 + 9-bit up counter : 1 +# Accumulators : 40 + 12-bit up accumulator cin : 2 + 14-bit down loadable accumulator : 2 + 14-bit up accumulator : 5 + 16-bit up accumulator : 2 + 3-bit up accumulator cin : 22 + 32-bit up loadable accumulator : 1 + 4-bit up loadable accumulator : 1 + 50-bit up accumulator : 1 + 50-bit up loadable accumulator : 1 + 6-bit up accumulator : 1 + 8-bit up accumulator cin : 1 + 8-bit up loadable accumulator : 1 +# Registers : 40752 + Flip-Flops : 40752 +# Shift Registers : 3498 + 16-bit dynamic shift register : 3498 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 4776 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 15-to-1 multiplexer : 24 + 1-bit 16-to-1 multiplexer : 87 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 2761 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 32-to-1 multiplexer : 34 + 1-bit 4-to-1 multiplexer : 312 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 38 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 15 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 14 + 15-bit 2-to-1 multiplexer : 1 + 16-bit 2-to-1 multiplexer : 40 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 92 + 20-bit 2-to-1 multiplexer : 13 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 123 + 3-bit 3-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 287 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 38 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 35-bit 2-to-1 multiplexer : 4 + 36-bit 2-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 56 + 4-bit 4-to-1 multiplexer : 72 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 31 + 5-bit 8-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 3 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 84 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 125 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 6 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 00001 | 000 + 00010 | 001 + 00100 | 010 + 01000 | 011 + 10000 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0001 | 00 + 0010 | 01 + 0100 | 11 + 1000 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0011 | 000 + 0110 | 001 + 0111 | 011 + 0001 | 010 + 1000 | 110 + 1001 | 111 + 0010 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------- + State | Encoding +---------------------------------------------------- + 0000000000000100000000000 | 000000000000000000001 + 0010000000000000000000000 | 000000000000000000010 + 0000100000000000000000000 | 000000000000000000100 + 0100000000000000000000000 | 000000000000000001000 + 1000000000000000000000000 | 000000000000000010000 + 0000000010000000000000000 | 000000000000000100000 + 0000000100000000000000000 | 000000000000001000000 + 0000000000000000000000010 | 000000000000010000000 + 0000001000000000000000000 | 000000000000100000000 + 0000000000000000000000001 | 000000000001000000000 + 0000000000010000000000000 | 000000000010000000000 + 0000000000000000010000000 | 000000000100000000000 + 0000010000000000000000000 | 000000001000000000000 + 0000000000000000000000100 | 000000010000000000000 + 0000000000000000000001000 | 000000100000000000000 + 0000000000000000001000000 | 000001000000000000000 + 0000000000100000000000000 | 000010000000000000000 + 0001000000000000000000000 | 000100000000000000000 + 0000000000000000100000000 | 001000000000000000000 + 0000000000000001000000000 | 010000000000000000000 + 0000000000000010000000000 | 100000000000000000000 +---------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 10 | 01 + 01 | 11 +------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------ + State | Encoding +------------------------------------ + 00000 | 0000000000000000000000001 + 11000 | 0000000000000000000000010 + 00001 | 0000000000000000000000100 + 00010 | 0000000000000000000001000 + 00011 | 0000000000000000000010000 + 00100 | 0000000000000000000100000 + 00111 | 0000000000000000001000000 + 01000 | 0000000000000000010000000 + 01001 | 0000000000000000100000000 + 01010 | 0000000000000001000000000 + 01011 | 0000000000000010000000000 + 01100 | 0000000000000100000000000 + 01111 | 0000000000001000000000000 + 10000 | 0000000000010000000000000 + 10001 | 0000000000100000000000000 + 10010 | 0000000001000000000000000 + 10011 | 0000000010000000000000000 + 10100 | 0000000100000000000000000 + 10111 | 0000001000000000000000000 + 00101 | 0000010000000000000000000 + 00110 | 0000100000000000000000000 + 01101 | 0001000000000000000000000 + 01110 | 0010000000000000000000000 + 10101 | 0100000000000000000000000 + 10110 | 1000000000000000000000000 +------------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------- + State | Encoding +-------------------- + 0000 | 000000001 + 0111 | 000000010 + 0001 | 000000100 + 0010 | 000001000 + 0101 | 000010000 + 0110 | 000100000 + 0011 | 001000000 + 0100 | 010000000 + 1010 | 100000000 +-------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 0000001 + 001 | 0000010 + 010 | 0000100 + 011 | 0001000 + 100 | 0010000 + 101 | 0100000 + 110 | 1000000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------------- + State | Encoding +------------------------------------------------- + 000000 | 0000000000000000000000000000000000001 + 000001 | 0000000000000000000000000000000000010 + 000010 | 0000000000000000000000000000000000100 + 000011 | 0000000000000000000000000000000001000 + 000100 | 0000000000000000000000000000000010000 + 010110 | 0000000000000000000000000000000100000 + 000101 | 0000000000000000000000000000001000000 + 000110 | 0000000000000000000000000000010000000 + 000111 | 0000000000000000000000000000100000000 + 001000 | 0000000000000000000000000001000000000 + 001001 | 0000000000000000000000000010000000000 + 001010 | 0000000000000000000000000100000000000 + 001011 | 0000000000000000000000001000000000000 + 001100 | 0000000000000000000000010000000000000 + 001101 | 0000000000000000000000100000000000000 + 010101 | 0000000000000000000001000000000000000 + 011010 | 0000000000000000000010000000000000000 + 011001 | 0000000000000000000100000000000000000 + 001111 | 0000000000000000001000000000000000000 + 010010 | 0000000000000000010000000000000000000 + 010100 | 0000000000000000100000000000000000000 + 010011 | 0000000000000001000000000000000000000 + 010111 | 0000000000000010000000000000000000000 + 011111 | 0000000000000100000000000000000000000 + 011000 | 0000000000001000000000000000000000000 + 011011 | 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0011 + 1000 | 1000 + 0111 | 0111 + 0110 | 0110 + 0101 | 0101 + 0010 | 0010 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 110 | 011 + 100 | 100 + 101 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00000 | 00000 + 00001 | 00001 + 00010 | 00010 + 00011 | 00011 + 01100 | 01100 + 01011 | 01011 + 00100 | 00100 + 00111 | 00111 + 00101 | 00101 + 01101 | 01101 + 00110 | 00110 + 01000 | 01000 + 10010 | 10010 + 01010 | 01010 + 01111 | 01111 + 01110 | 01110 + 10000 | 10000 + 01001 | 01001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0010 | 0010 + 0011 | 0011 + 0100 | 0100 + 0110 | 0110 + 0101 | 0101 + 0111 | 0111 + 1000 | 1000 + 1001 | 1001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 011 | 011 + 100 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1010 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0100 | 00000100000 + 0101 | 00001000000 + 0110 | 00010000000 + 0111 | 00100000000 + 1000 | 01000000000 + 1001 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. 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00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00111101 | 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 01000001 | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 10101010 | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------------------------------------------------------------------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +INFO:Xst:1901 - Instance use_ramb36.ramb36 in unit use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 +INFO:Xst:1901 - Instance GEN2_LINK.pipe_clk_bufgmux in unit pcie_clocking_v6 of type BUFGMUX has been replaced by BUFGCTRL +INFO:Xst:1901 - Instance gmii_rxc_dly in unit mkGMAC of type IODELAY has been replaced by IODELAYE1 +INFO:Xst:1901 - Instance gmii_rx_clk in unit mkGMAC of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 3. +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 16-bit shift register was found for signal and currently occupies 16 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 33-bit shift register was found for signal and currently occupies 33 logic cells (16 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 31-bit shift register was found for signal and currently occupies 31 logic cells (15 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 3-bit shift register for signal . +Unit processed. + +Processing Unit : + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 3-bit shift register for signal . + Found 16-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 4-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 35587 + Flip-Flops : 35587 +# Shift Registers : 44 + 10-bit shift register : 2 + 16-bit shift register : 5 + 2-bit shift register : 34 + 3-bit shift register : 2 + 4-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : fpgaTop.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 48442 +# BUF : 102 +# GND : 222 +# INV : 1326 +# LUT1 : 2527 +# LUT2 : 3412 +# LUT3 : 4470 +# LUT4 : 4172 +# LUT5 : 7356 +# LUT6 : 14694 +# MULT_AND : 90 +# MUXCY : 4697 +# MUXF7 : 716 +# MUXF8 : 100 +# VCC : 188 +# XORCY : 4370 +# FlipFlops/Latches : 35647 +# FD : 7550 +# FD_1 : 432 +# FDC : 480 +# FDCE : 1342 +# FDE : 11189 +# FDP : 146 +# FDPE : 59 +# FDR : 2139 +# FDRE : 9876 +# FDS : 112 +# FDSE : 2310 +# ODDR : 12 +# RAMS : 829 +# RAM32M : 432 +# RAM32X1D : 68 +# RAM64X1D : 288 +# RAMB18E1 : 3 +# RAMB36E1 : 38 +# Shift Registers : 2977 +# SRL16E : 5 +# SRLC16E : 2970 +# SRLC32E : 2 +# Clock Buffers : 12 +# BUFG : 11 +# BUFGCTRL : 1 +# IO Buffers : 232 +# IBUF : 29 +# IBUFDS : 2 +# IBUFDS_GTXE1 : 2 +# IOBUF : 81 +# IOBUFDS_DIFF_OUT : 8 +# OBUF : 109 +# OBUFDS : 1 +# GigabitIOs : 4 +# GTXE1 : 4 +# Others : 302 +# BUFIODQS : 9 +# BUFR : 3 +# DNA_PORT : 1 +# IDELAYCTRL : 1 +# IODELAYE1 : 91 +# ISERDESE1 : 72 +# MMCM_ADV : 2 +# OSERDESE1 : 122 +# PCIE_2_0 : 1 + +Device utilization summary: +--------------------------- + +Selected Device : 6vlx240tff1156-1 + + +Slice Logic Utilization: + Number of Slice Registers: 35647 out of 301440 11% + Number of Slice LUTs: 43374 out of 150720 28% + Number used as Logic: 37957 out of 150720 25% + Number used as Memory: 5417 out of 58400 9% + Number used as RAM: 2440 + Number used as SRL: 2977 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 58766 + Number with an unused Flip Flop: 23119 out of 58766 39% + Number with an unused LUT: 15392 out of 58766 26% + Number of fully used LUT-FF pairs: 20255 out of 58766 34% + Number of unique control sets: 2323 + +IO Utilization: + Number of IOs: 242 + Number of bonded IOBs: 237 out of 600 39% + +Specific Feature Utilization: + Number of Block RAM/FIFO: 40 out of 416 9% + Number using Block RAM only: 40 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT0 | 550 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT1 | 29434 | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | BUFGCTRL | 418 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDWE | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i)| 1 | +sys1_clkp | IBUF+IBUFDS_GTXE1+BUFG | 119 | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | BUFR | 134 | +sys0_clkp | MMCM_ADV:CLKOUT1 | 6206 | +flp_cdc_clk_p | IBUFDS+BUFG | 20 | +ftop/fmc150/spiCDC_cd/cntr_2 | BUFG | 76 | +ftop/fmc150/spiDAC_cd/cntr_3 | BUFG | 31 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| BUFR | 928 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| BUFR | 1542 | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/ctop/app/appW2/wmiM0_MDataValid(ftop/ctop/app/appW2/XST_GND:G) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 4 | +ftop/ctop/app/appW4/wmiM0_MAddrSpace(ftop/ctop/app/appW4/XST_GND:G) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 4 | +ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4622_o(ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4622_o1_INV_0:O) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i) | 3 | +ftop/ctop/app/appW2/respF_pwEnqueue_whas(ftop/ctop/app/appW2/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/app/appW4/respF_pwEnqueue_whas(ftop/ctop/app/appW4/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/inf/cp/rom_memory/DO<16>(ftop/ctop/inf/cp/rom_memory/XST_GND:G) | NONE(ftop/ctop/inf/cp/rom_memory/Mram_RAM1) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/N0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/XST_VCC:P) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0:Q) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/gbe0/gmac/CLK_GATE_rxclkBnd(ftop/gbe0/gmac/XST_VCC:P) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +ftop/gbe0/gmac/txRS_txER(ftop/gbe0/gmac/XST_GND:G) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -1 + + Minimum period: 4.758ns (Maximum Frequency: 210.172MHz) + Minimum input arrival time before clock: 1.793ns + Maximum output required time after clock: 1.923ns + Maximum combinational path delay: 0.538ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Clock period: 4.101ns (frequency: 243.823MHz) + Total number of paths / destination ports: 10609175 / 82074 +------------------------------------------------------------------------- +Delay: 8.203ns (Levels of Logic = 12) + Source: ftop/ctop/inf/cp/cpReq_26 (FF) + Destination: ftop/ctop/inf/cp/cpReq_0 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/ctop/inf/cp/cpReq_26 to ftop/ctop/inf/cp/cpReq_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 28 0.375 0.733 cpReq_26 (cpReq_26) + LUT3:I0->O 66 0.068 0.577 Msub_wn___1__h76499_xor<2>11 (wn___1__h76499<2>) + LUT6:I5->O 62 0.068 0.558 Mmux__theResult_____1__h7573931 (_theResult_____1__h75739<2>) + MUXF7:S->O 1 0.267 0.000 Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 (Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7) + MUXF8:I0->O 2 0.175 0.423 Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 (CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793) + LUT6:I5->O 109 0.068 0.586 _n13575<34>21 (_n13575<34>2) + LUT5:I4->O 20 0.068 0.763 WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T) + LUT6:I2->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead5 (WILL_FIRE_RL_completeWorkerRead5) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead11 (WILL_FIRE_RL_completeWorkerRead11) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead17 (WILL_FIRE_RL_completeWorkerRead17) + LUT6:I5->O 19 0.068 0.536 WILL_FIRE_RL_completeWorkerRead31 (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 7 0.068 0.457 cpRespF_ENQ1 (cpRespF_ENQ) + LUT6:I5->O 64 0.068 0.559 cpReq_EN (cpReq_EN) + FDRE:CE 0.263 cpReq_0 + ---------------------------------------- + Total 8.203ns (1.760ns logic, 6.443ns route) + (21.5% logic, 78.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125' + Clock period: 3.724ns (frequency: 268.528MHz) + Total number of paths / destination ports: 4781 / 823 +------------------------------------------------------------------------- +Delay: 3.724ns (Levels of Logic = 5) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + + Data Path: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 4 0.375 0.798 state_FSM_FFd5 (state_FSM_FFd5) + LUT6:I0->O 1 0.068 0.491 nextwaitcounter2<7>112 (nextwaitcounter2<7>112) + LUT6:I4->O 2 0.068 0.423 nextwaitcounter2<7>113 (nextwaitcounter2<7>11) + LUT4:I3->O 2 0.068 0.423 nextwaitcounter2<1>31 (nextwaitcounter2<1>3) + LUT6:I5->O 14 0.068 0.863 nextwaitcounter2<0>11 (nextwaitcounter2<0>1) + LUT6:I0->O 1 0.068 0.000 nextwaitcounter<4>1 (nextwaitcounter<4>) + FDR:D 0.011 waitcounter_4 + ---------------------------------------- + Total 3.724ns (0.726ns logic, 2.998ns route) + (19.5% logic, 80.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys1_clkp' + Clock period: 3.831ns (frequency: 261.028MHz) + Total number of paths / destination ports: 6108 / 281 +------------------------------------------------------------------------- +Delay: 3.831ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Source Clock: sys1_clkp rising + Destination Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.375 0.795 txRS_ifgCnt_value_2 (txRS_ifgCnt_value_2) + LUT6:I1->O 12 0.068 0.563 WILL_FIRE_RL_txRS_egress_SOF31 (Mmux_txRS_txData_D_IN122) + LUT6:I4->O 8 0.068 0.463 Mmux_txRS_crc_add_data11 (Mmux_txRS_crc_add_data11) + LUT2:I1->O 15 0.068 0.867 Mmux_txRS_crc_add_data21 (txRS_crc_add_data<1>) + begin scope: 'ftop/gbe0/gmac/txRS_crc:add_data<1>' + LUT6:I1->O 1 0.068 0.417 rRemainder$D_IN<5>1 (rRemainder$D_IN<5>1) + LUT5:I4->O 1 0.068 0.000 rRemainder$D_IN<5>3 (rRemainder$D_IN<5>) + FDSE:D 0.011 rRemainder_5 + ---------------------------------------- + Total 3.831ns (0.726ns logic, 3.105ns route) + (19.0% logic, 81.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Clock period: 3.576ns (frequency: 279.622MHz) + Total number of paths / destination ports: 2172 / 314 +------------------------------------------------------------------------- +Delay: 3.576ns (Levels of Logic = 4) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Source Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 18 0.375 0.603 dSyncReg2 (dSyncReg2) + end scope: 'ftop/gbe0/gmac/rxRS_rxOperateS:dD_OUT' + LUT3:I1->O 49 0.068 0.931 _n0454_inv211 (WILL_FIRE_RL_rxRS_ingress_advance) + LUT6:I1->O 2 0.068 0.781 _n0454_inv2 (_n0454_inv2) + LUT5:I0->O 4 0.068 0.419 _n0454_inv1 (_n0454_inv) + FDRE:CE 0.263 rxRS_preambleCnt_value_0 + ---------------------------------------- + Total 3.576ns (0.842ns logic, 2.734ns route) + (23.5% logic, 76.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 4.758ns (frequency: 210.172MHz) + Total number of paths / destination ports: 166444 / 12719 +------------------------------------------------------------------------- +Delay: 4.758ns (Levels of Logic = 13) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl (FF) + Source Clock: sys0_clkp rising + Destination Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.375 0.784 io_config_r_1 (io_config_r_1) + LUT6:I0->O 1 0.068 0.417 Mmux_io_config_ns41 (Mmux_io_config_ns4) + LUT6:I5->O 1 0.068 0.417 Mmux_io_config_ns42 (Mmux_io_config_ns41) + LUT5:I4->O 20 0.068 0.542 Mmux_io_config_ns43 (dfi_odt_nom1<0>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:io_config<1>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:io_config<1>' + LUT4:I3->O 4 0.068 0.511 inhbt_wr_config11 (inhbt_wr_config) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:inhbt_wr_config' + LUT6:I4->O 6 0.068 0.808 rtc (rtc) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:rtc' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:rtc' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:rtc<2>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0:rtc<2>' + LUT6:I1->O 1 0.068 0.417 io_config_valid_ns_norst2 (io_config_valid_ns_norst2) + LUT2:I1->O 1 0.068 0.000 io_config_valid_ns_norst3 (io_config_valid_ns_norst) + FDR:D 0.011 io_config_valid_r_lcl + ---------------------------------------- + Total 4.758ns (0.862ns logic, 3.896ns route) + (18.1% logic, 81.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'flp_cdc_clk_p' + Clock period: 4.676ns (frequency: 213.858MHz) + Total number of paths / destination ports: 12407 / 37 +------------------------------------------------------------------------- +Delay: 4.676ns (Levels of Logic = 7) + Source: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 (FF) + Destination: ftop/fmc150/fcCdc_grayCounter_rsCounter_0 (FF) + Source Clock: flp_cdc_clk_p rising + Destination Clock: flp_cdc_clk_p rising + + Data Path: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 to ftop/fmc150/fcCdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 5 0.375 0.802 fcCdc_grayCounter_rsCounter_16 (fcCdc_grayCounter_rsCounter_16) + LUT6:I1->O 3 0.068 0.595 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>2 (Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>1) + LUT3:I0->O 14 0.068 0.502 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>4 (fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454) + LUT6:I5->O 13 0.068 0.571 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d49014 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490<0>) + LUT6:I4->O 1 0.068 0.638 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_91 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_91) + LUT6:I2->O 1 0.068 0.000 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_4 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_4) + MUXF7:I0->O 18 0.245 0.529 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_2_f7 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o) + LUT6:I5->O 1 0.068 0.000 Mmux_MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_181 (MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_1<16>) + FDC:D 0.011 fcCdc_grayCounter_rsCounter_16 + ---------------------------------------- + Total 4.676ns (1.039ns logic, 3.637ns route) + (22.2% logic, 77.8% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Clock period: 3.708ns (frequency: 269.687MHz) + Total number of paths / destination ports: 745 / 184 +------------------------------------------------------------------------- +Delay: 3.708ns (Levels of Logic = 7) + Source: ftop/fmc150/spiCDC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiCDC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_slowReset/reset_hold_1 to ftop/fmc150/spiCDC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 9 0.375 0.470 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiCDC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiCDC_reqF_dInReset:RST' + INV:I->O 8 0.086 0.824 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiCDC_reqF_dInReset:VAL' + LUT6:I0->O 4 0.068 0.511 MUX_spiCDC_rcv_d_write_1__SEL_21 (MUX_spiCDC_rcv_d_write_1__SEL_2) + LUT4:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable91 (Reset_OR_DriverANDClockEnable9) + FDRE:R 0.434 spiCDC_reqF_head_wrapped + ---------------------------------------- + Total 3.708ns (1.099ns logic, 2.609ns route) + (29.6% logic, 70.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Clock period: 3.785ns (frequency: 264.201MHz) + Total number of paths / destination ports: 336 / 69 +------------------------------------------------------------------------- +Delay: 3.785ns (Levels of Logic = 8) + Source: ftop/fmc150/spiDAC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiDAC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_slowReset/reset_hold_1 to ftop/fmc150/spiDAC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 6 0.375 0.450 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiDAC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiDAC_reqF_dInReset:RST' + INV:I->O 5 0.086 0.444 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiDAC_reqF_dInReset:VAL' + LUT6:I5->O 13 0.068 0.497 WILL_FIRE_RL_spiDAC_doxcv_d1 (WILL_FIRE_RL_spiDAC_doxcv_d) + LUT5:I4->O 2 0.068 0.423 spiDAC_reqF_head_wrapped_EN1 (spiDAC_reqF_head_wrapped_EN) + LUT3:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable101 (Reset_OR_DriverANDClockEnable10) + FDRE:R 0.434 spiDAC_reqF_head_wrapped + ---------------------------------------- + Total 3.785ns (1.167ns logic, 2.618ns route) + (30.8% logic, 69.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 2069 / 1093 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 3439 / 1815 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 25 / 25 +------------------------------------------------------------------------- +Offset: 1.457ns (Levels of Logic = 4) + Source: pci0_reset_n (PAD) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 (FF) + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising + + Data Path: pci0_reset_n to ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 pci0_reset_n_IBUF (pci0_reset_n_IBUF) + begin scope: 'ftop:pci0_rstn' + begin scope: 'ftop/pciw_pci0_pcie_ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i:sys_reset_n' + INV:I->O 22 0.086 0.535 sys_reset_n_inv1_INV_0 (sys_reset_n_inv) + FDCE:CLR 0.434 reg_count_23_16_0 + ---------------------------------------- + Total 1.457ns (0.523ns logic, 0.934ns route) + (35.9% logic, 64.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0/gmac:gmii_rx_rxd_i<0>' + FD:D 0.011 rxRS_rxData_0 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 75 / 75 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: ppsExtIn (PAD) + Destination: ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 (FF) + Destination Clock: sys0_clkp rising + + Data Path: ppsExtIn to ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 ppsExtIn_IBUF (ppsExtIn_IBUF) + begin scope: 'ftop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf/cp:gps_ppsSyncIn_x' + FDR:D 0.011 timeServ_ppsExtSync_d1 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_cdc_sdi (PAD) + Destination: ftop/fmc150/spiCDC_sdiP (FF) + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 falling + + Data Path: flp_cdc_sdi to ftop/fmc150/spiCDC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_cdc_sdi_IBUF (flp_cdc_sdi_IBUF) + begin scope: 'ftop:flpCDC_sdi_arg' + begin scope: 'ftop/fmc150:padsCDC_sdi_arg' + FD:D 0.011 spiCDC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_dac_sdi (PAD) + Destination: ftop/fmc150/spiDAC_sdiP (FF) + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 falling + + Data Path: flp_dac_sdi to ftop/fmc150/spiDAC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_dac_sdi_IBUF (flp_dac_sdi_IBUF) + begin scope: 'ftop:flpDAC_sdi_arg' + begin scope: 'ftop/fmc150:padsDAC_sdi_arg' + FD:D 0.011 spiDAC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 1665 / 675 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 999 / 405 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 79 / 62 +------------------------------------------------------------------------- +Offset: 1.360ns (Levels of Logic = 4) + Source: ftop/flash0/flashC_tsOE (FF) + Destination: flash_io_dq<15> (PAD) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/flash0/flashC_tsOE to flash_io_dq<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.399 flashC_tsOE (flashC_tsOE) + begin scope: 'ftop/flash0/flashC_tsd:OE' + INV:I->O 16 0.086 0.497 OE_inv1_INV_0 (OE_inv) + IOBUF:T->IO 0.003 IO_15_IOBUF (IO<15>) + end scope: 'ftop/flash0/flashC_tsd:IO<15>' + end scope: 'ftop/flash0:flash_io_dq<15>' + end scope: 'ftop:flash_io_dq<15>' + ---------------------------------------- + Total 1.360ns (0.464ns logic, 0.896ns route) + (34.1% logic, 65.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys1_clkp' + Total number of paths / destination ports: 12 / 12 +------------------------------------------------------------------------- +Offset: 1.009ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Destination: gmii_txd<7> (PAD) + Source Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_iobTxData_7 to gmii_txd<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ODDR:C->Q 1 0.607 0.399 txRS_iobTxData_7 (gmii_tx_txd<7>) + end scope: 'ftop/gbe0/gmac:gmii_tx_txd<7>' + end scope: 'ftop/gbe0:gmii_tx_txd<7>' + end scope: 'ftop:gmii_tx_txd<7>' + OBUF:I->O 0.003 gmii_txd_7_OBUF (gmii_txd<7>) + ---------------------------------------- + Total 1.009ns (0.610ns logic, 0.399ns route) + (60.5% logic, 39.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 1228 / 1056 +------------------------------------------------------------------------- +Offset: 1.870ns (Levels of Logic = 5) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST (PAD) + Source Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDP:C->Q 3 0.375 0.413 rstdiv0_sync_r_32 (rstdiv0_sync_r_32) + end scope: 'ftop/dram0/memc_memc/u_infrastructure:rstdiv0' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top:rst' + BUF:I->O 10 0.086 0.458 rst_1 (rst_1) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0:rst' + BUF:I->O 9 0.086 0.452 rst_8 (rst_8) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob:rst' + OSERDESE1:RST 0.000 u_oserdes_ck_p + ---------------------------------------- + Total 1.870ns (0.547ns logic, 1.323ns route) + (29.3% logic, 70.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 5 / 4 +------------------------------------------------------------------------- +Offset: 1.923ns (Levels of Logic = 4) + Source: ftop/fmc150/spiCDC_csbR (FF) + Destination: flp_com_sclk (PAD) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_csbR to flp_com_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 2 0.375 0.405 spiCDC_csbR (spiCDC_csbR) + INV:I->O 2 0.086 0.587 spiCDC_csbR_inv1_INV_0 (padsCDC_sclkgate) + end scope: 'ftop/fmc150:padsCDC_sclkgate' + end scope: 'ftop:flpCDC_sclkgate' + LUT4:I1->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.923ns (0.532ns logic, 1.391ns route) + (27.7% logic, 72.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 1.336ns (Levels of Logic = 3) + Source: ftop/fmc150/spiDAC_sdoR (FF) + Destination: flp_com_sdc2m (PAD) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_sdoR to flp_com_sdc2m + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.491 spiDAC_sdoR (spiDAC_sdoR) + end scope: 'ftop/fmc150:padsDAC_sdo' + end scope: 'ftop:flpDAC_sdo' + LUT4:I2->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.336ns (0.446ns logic, 0.890ns route) + (33.4% logic, 66.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 250 / 250 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_39 (dlyval_dq_39) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 150 / 150 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_14 (dlyval_dq_14) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 596 / 532 +------------------------------------------------------------------------- +Delay: 0.538ns (Levels of Logic = 3) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB (PAD) + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BUFIODQS:O 9 0.000 0.000 gen_ck_cpt[7].u_bufio_cpt (clk_cpt<7>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen:clk_cpt<7>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob:clk_cpt' + INV:I->O 0 0.086 0.000 iserdes_clkb1_INV_0 (iserdes_clkb) + ISERDESE1:CLKB 0.000 u_iserdes_dqs_p + ---------------------------------------- + Total 0.538ns (0.538ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock flp_cdc_clk_p +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 4.676| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.824| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiCDC_cd/cntr_2 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiCDC_cd/cntr_2 | 3.708| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.854| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiDAC_cd/cntr_3 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiDAC_cd/cntr_3 | 3.785| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.951| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 3.576| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.860| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 0.857| | | | +ftop/fmc150/spiCDC_cd/cntr_2 | 5.230| | | | +ftop/fmc150/spiDAC_cd/cntr_3 | 5.350| | | | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 2.078| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 8.203| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | 2.324| | | | +sys0_clkp | 2.712| | | | +sys1_clkp | 1.727| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 +-------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +-------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125| 3.724| | | | +-------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 1.675| | | | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 1.675| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | 2.230| | | | +sys0_clkp | 4.758| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 2.078| | | | +sys1_clkp | 3.831| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 351.00 secs +Total CPU time to Xst completion: 349.12 secs + +--> + + +Total memory usage is 1451872 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2594 ( 0 filtered) +Number of infos : 410 ( 0 filtered) + diff --git a/logs/ml605-20140203_1611/fpgaTop.bld b/logs/ml605-20140203_1611/fpgaTop.bld new file mode 100644 index 00000000..61dce2ec --- /dev/null +++ b/logs/ml605-20140203_1611/fpgaTop.bld @@ -0,0 +1,5926 @@ +Release 14.7 ngdbuild P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: /home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_trn_v6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc ml605.ucf -p xc6vlx240t-ff1156-1 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-ml605/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "ml605.ucf" ... +WARNING:NgdBuild - The value of SIM_DEVICE on instance + 'ftop/gbe0/gmac/rxClk_BUFR' of type BUFR has been changed from 'VIRTEX4' to + 'VIRTEX6' to correct post-ngdbuild and timing simulation for this primitive. + In order for functional simulation to be correct, the value of SIM_DEVICE + should be changed in this same manner in the source netlist or constraint + file. +Resolving constraint associations... +Checking Constraint Associations... +WARNING:ConstraintSystem - Constraint + [ml605.ucf(46)] was not distributed to the output pin TXOUTCLK of block + GTXD[0].GTX because the signal path to this output pin depends upon block + attribute settings. Constraint distribution does not support attribute + dependent distribution. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(113)]: NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(113)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(113)]: + NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(125)]: NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(125)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(125)]: + NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(126)]: NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(126)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(126)]: + NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(127)]: NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(127)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(127)]: + NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(281)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(286)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(287)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(294)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:58 - Constraint [ml605.ucf(761)]: INST + "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon" does not match any + design objects. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(761)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(768)]: INST "ftop/dram0/memc/u_infrastructure/u_mmcm_adv" not + found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(768)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(769)]: INST + "ftop/dram0/memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_ge + n/u_mmcm_clk_base" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(769)]' could not be + found and so the Locate constraint will be removed. + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT1: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT2: + +Done... + +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N100' has no driver +WARNING:NgdBuild:452 - logical net 'N101' has no driver +WARNING:NgdBuild:452 - logical net 'N102' has no driver +WARNING:NgdBuild:452 - logical net 'N103' has no driver +WARNING:NgdBuild:452 - logical net 'N104' has no driver +WARNING:NgdBuild:452 - logical net 'N105' has no driver +WARNING:NgdBuild:452 - logical net 'N106' has no driver +WARNING:NgdBuild:452 - logical net 'N107' has no driver +WARNING:NgdBuild:452 - logical net 'N108' has no driver +WARNING:NgdBuild:452 - logical net 'N109' has no driver +WARNING:NgdBuild:452 - logical net 'N110' has no driver +WARNING:NgdBuild:452 - logical net 'N111' has no driver +WARNING:NgdBuild:452 - logical net 'N112' has no driver +WARNING:NgdBuild:452 - logical net 'N113' has no driver +WARNING:NgdBuild:452 - logical net 'N114' has no driver +WARNING:NgdBuild:452 - logical net 'N115' has no driver +WARNING:NgdBuild:452 - logical net 'N116' has no driver +WARNING:NgdBuild:452 - logical net 'N117' has no driver +WARNING:NgdBuild:452 - logical net 'N118' has no driver +WARNING:NgdBuild:452 - logical net 'N119' has no driver +WARNING:NgdBuild:452 - logical net 'N120' has no driver +WARNING:NgdBuild:452 - logical net 'N121' has no driver +WARNING:NgdBuild:452 - logical net 'N122' has no driver +WARNING:NgdBuild:452 - logical net 'N123' has no driver +WARNING:NgdBuild:452 - logical net 'N124' has no driver +WARNING:NgdBuild:452 - logical net 'N125' has no driver +WARNING:NgdBuild:452 - logical net 'N126' has no driver +WARNING:NgdBuild:452 - logical net 'N127' has no driver +WARNING:NgdBuild:452 - logical net 'N128' has no driver +WARNING:NgdBuild:452 - logical net 'N129' has no driver +WARNING:NgdBuild:452 - logical net 'N130' has no driver +WARNING:NgdBuild:452 - logical net 'N131' has no driver +WARNING:NgdBuild:452 - logical net 'N132' has no driver +WARNING:NgdBuild:452 - logical net 'N133' has no driver +WARNING:NgdBuild:452 - logical net 'N134' has no driver +WARNING:NgdBuild:452 - logical net 'N135' has no driver +WARNING:NgdBuild:452 - logical net 'N136' has no driver +WARNING:NgdBuild:452 - logical net 'N137' has no driver +WARNING:NgdBuild:452 - logical net 'N138' has no driver +WARNING:NgdBuild:452 - logical net 'N139' has no driver +WARNING:NgdBuild:452 - logical net 'N140' has no driver +WARNING:NgdBuild:452 - logical net 'N141' has no driver +WARNING:NgdBuild:452 - logical net 'N142' has no driver +WARNING:NgdBuild:452 - logical net 'N143' has no driver +WARNING:NgdBuild:452 - logical net 'N144' has no driver +WARNING:NgdBuild:452 - logical net 'N145' has no driver +WARNING:NgdBuild:452 - logical net 'N146' has no driver +WARNING:NgdBuild:452 - logical net 'N147' has no driver +WARNING:NgdBuild:452 - logical net 'N148' has no driver +WARNING:NgdBuild:452 - logical net 'N149' has no driver +WARNING:NgdBuild:452 - logical net 'N150' has no driver +WARNING:NgdBuild:452 - logical net 'N151' has no driver +WARNING:NgdBuild:452 - logical net 'N152' has no driver +WARNING:NgdBuild:452 - logical net 'N153' has no driver +WARNING:NgdBuild:452 - logical net 'N154' has no driver +WARNING:NgdBuild:452 - logical net 'N155' has no driver +WARNING:NgdBuild:452 - logical net 'N156' has no driver +WARNING:NgdBuild:452 - logical net 'N157' has no driver +WARNING:NgdBuild:452 - logical net 'N158' has no driver +WARNING:NgdBuild:452 - logical net 'N159' has no driver +WARNING:NgdBuild:452 - logical net 'N160' has no driver +WARNING:NgdBuild:452 - logical net 'N161' has no driver +WARNING:NgdBuild:452 - logical net 'N162' has no driver +WARNING:NgdBuild:452 - logical net 'N163' has no driver +WARNING:NgdBuild:452 - logical net 'N164' has no driver +WARNING:NgdBuild:452 - logical net 'N165' has no driver +WARNING:NgdBuild:452 - logical net 'N166' has no driver +WARNING:NgdBuild:452 - logical net 'N167' has no driver +WARNING:NgdBuild:452 - logical net 'N168' has no driver +WARNING:NgdBuild:452 - logical net 'N169' has no driver +WARNING:NgdBuild:452 - logical net 'N170' has no driver +WARNING:NgdBuild:452 - logical net 'N171' has no driver +WARNING:NgdBuild:452 - logical net 'N172' has no driver +WARNING:NgdBuild:452 - logical net 'N173' has no driver +WARNING:NgdBuild:452 - logical net 'N174' has no driver +WARNING:NgdBuild:452 - logical net 'N175' has no driver +WARNING:NgdBuild:452 - logical net 'N176' has no driver +WARNING:NgdBuild:452 - logical net 'N177' has no driver +WARNING:NgdBuild:452 - logical net 'N178' has no driver +WARNING:NgdBuild:452 - logical net 'N179' has no driver +WARNING:NgdBuild:452 - logical net 'N180' has no driver +WARNING:NgdBuild:452 - logical net 'N181' has no driver +WARNING:NgdBuild:452 - logical net 'N182' has no driver +WARNING:NgdBuild:452 - logical net 'N183' has no driver +WARNING:NgdBuild:452 - logical net 'N184' has no driver +WARNING:NgdBuild:452 - logical net 'N185' has no driver +WARNING:NgdBuild:452 - logical net 'N186' has no driver +WARNING:NgdBuild:452 - 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logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<15>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<14>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<13>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<12>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<11>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<10>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_to_turnoff_n' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/pipe_tx_swing_o' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<42>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/gbe0/dcp_dcpRespF_D_OUT<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<143>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<142>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<141>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<140>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<139>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<138>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<137>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<136>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<135>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<134>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<133>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<132>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<131>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<130>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<129>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_request_put<128>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<150>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<149>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<148>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<147>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<146>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<145>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/server_response_get<144>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MCmd<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MCmd<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MCmd<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MByteEn<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MByteEn<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MByteEn<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop/inf_wci_m_0_MByteEn<0>' has no + driver +WARNING:NgdBuild:452 - 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logical net 'ftop/dram0/memc_memc/u_memc_ui_top/cmd<2>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0/memc_memc/u_memc_ui_top/cmd<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/app_ecc_multiple_err<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/app_ecc_multiple_err<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/app_ecc_multiple_err<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/app_ecc_multiple_err<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0/memc_memc/u_memc_ui_top/size' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/correct_en' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/rd_data_offset' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/rd_data_addr<3>' has no driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_address1<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_dram_clk_disable' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_reset_n' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_cas_n1' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<209>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<21>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<20>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<19>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<18>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<9>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<8>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<248>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<122>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_ra' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_a<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/io_config_ns<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/m + aintenance_request.maint_grant_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<0> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<1> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<2> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<3> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/low_idle_cnt_r + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/was_priority' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd0_col' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd1_row' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<15>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<14>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<13>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<12>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<11>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<10>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<9>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<23>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<22>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<21>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<20>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<19>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<18>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<17>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<31>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<30>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<29>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<28>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<27>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<26>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<25>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<0>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<39>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<38>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<37>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<36>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<35>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<34>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<33>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<32>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<31>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<30>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<29>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<28>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<27>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<26>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<25>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<24>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<23>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<22>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<21>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<20>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<19>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<18>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<17>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<16>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<15>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<14>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<13>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<12>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<11>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<10>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<9>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<8>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/pd_prech_req' has no + driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 2574 + +Total memory usage is 840188 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 48 sec +Total CPU time to NGDBUILD completion: 48 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/ml605-20140203_1611/fpgaTop.par b/logs/ml605-20140203_1611/fpgaTop.par new file mode 100644 index 00000000..0862b3d0 --- /dev/null +++ b/logs/ml605-20140203_1611/fpgaTop.par @@ -0,0 +1,1217 @@ +Release 14.7 par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +ar-cms520:: Mon Feb 03 16:01:42 2014 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '6vlx240t.nph' in environment /home/shep/ISE/14.7/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) + + +Device speed data version: "PRODUCTION 1.17 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 35,513 out of 301,440 11% + Number used as Flip Flops: 35,506 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 43,543 out of 150,720 28% + Number used as logic: 37,698 out of 150,720 25% + Number using O6 output only: 34,100 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,188 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 762 + Number with same-slice register load: 630 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 17,310 out of 37,680 45% + Number of LUT Flip Flop pairs used: 51,912 + Number with an unused Flip Flop: 17,424 out of 51,912 33% + Number with an unused LUT: 8,369 out of 51,912 16% + Number of fully used LUT-FF pairs: 26,119 out of 51,912 50% + Number of slice register sites lost + to control set restrictions: 0 out of 301,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + + +Overall effort level (-ol): Standard +Router effort level (-rl): High + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +Starting initial Timing Analysis. REAL time: 40 secs +Finished initial Timing Analysis. REAL time: 42 secs + +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal upads_cts_arg_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMB_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<7> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/axbluart/bluart/rxF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<29> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<31> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<17> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<19> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<173> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<145> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMB_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem27_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/txRS_txF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +Starting Router + + +Phase 1 : 264315 unrouted; REAL time: 48 secs + +Phase 2 : 227135 unrouted; REAL time: 1 mins 4 secs + +Phase 3 : 73806 unrouted; REAL time: 2 mins + +Phase 4 : 75511 unrouted; (Setup:214051, Hold:28025, Component Switching Limit:0) REAL time: 2 mins 24 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:354765, Hold:25553, Component Switching Limit:0) REAL time: 5 mins 21 secs + +Phase 6 : 0 unrouted; (Setup:354765, Hold:25553, Component Switching Limit:0) REAL time: 5 mins 29 secs + +Phase 7 : 0 unrouted; (Setup:354765, Hold:25553, Component Switching Limit:0) REAL time: 6 mins 1 secs + +Phase 8 : 0 unrouted; (Setup:354765, Hold:25553, Component Switching Limit:0) REAL time: 6 mins 1 secs + +Phase 9 : 0 unrouted; (Setup:354765, Hold:25553, Component Switching Limit:0) REAL time: 6 mins 1 secs + +Phase 10 : 0 unrouted; (Setup:354765, Hold:35, Component Switching Limit:0) REAL time: 6 mins 7 secs + +Phase 11 : 0 unrouted; (Setup:346535, Hold:35, Component Switching Limit:0) REAL time: 6 mins 19 secs +Total REAL time to Router completion: 6 mins 19 secs +Total CPU time to Router completion: 6 mins 43 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/p125clk |BUFGCTRL_X0Y29| No | 8333 | 0.464 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| _tb_clk |BUFGCTRL_X0Y25| No | 2156 | 0.365 | 1.952 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/pipe_clk |BUFGCTRL_X0Y30| No | 182 | 0.418 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<0> | Regional Clk|Yes | 272 | 0.179 | 1.017 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<1> | Regional Clk|Yes | 457 | 0.280 | 1.123 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/sys0_clk_O_BUFG | | | | | | +| | BUFGCTRL_X0Y1| No | 233 | 0.213 | 1.801 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/rxclkBnd | Regional Clk| No | 40 | 0.240 | 1.134 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1_clk_O |BUFGCTRL_X0Y24| No | 58 | 0.154 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep_trn_clk |BUFGCTRL_X0Y28| No | 235 | 0.157 | 1.782 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpCDC_sclk | BUFGCTRL_X0Y2| No | 29 | 0.051 | 1.658 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpDAC_sclk | BUFGCTRL_X0Y3| No | 15 | 0.020 | 1.650 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flp_clk_O_BUFG | BUFGCTRL_X0Y0| No | 9 | 0.029 | 1.651 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/TxOutClk_bufg |BUFGCTRL_X0Y31| No | 6 | 0.005 | 1.640 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_mem |BUFGCTRL_X0Y26| No | 186 | 0.164 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/ctop/inf/cp/dna | | | | | | +| _cnt<0> | Local| | 11 | 0.000 | 2.453 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_301_ML_NE | | | | | | +| W_CLK | Local| | 2 | 0.000 | 0.247 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_I1 | Local| | 3 | 0.000 | 1.794 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_309_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.142 | 0.506 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| I1 | Local| | 3 | 0.000 | 2.093 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| OUT | Local| | 2 | 0.000 | 0.541 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_OUT | Local| | 2 | 0.000 | 0.535 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<7> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_wr_i | Local| | 10 | 0.402 | 1.403 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<6> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<2> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<3> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<4> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<5> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<0> | Local| | 18 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_clk_O | | | | | | +| | Local| | 8 | 0.000 | 2.396 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<1> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 346570 (Setup: 346535, Hold: 35, Component Switching Limit: 0) + +WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. + + Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options + are set in the tools for timing closure. + + Increase the PAR Effort Level setting to "high" + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + + Visit the Xilinx technical support web at http://support.xilinx.com and go to + either "Troubleshoot->Tech Tips->Timing & Constraints" or " + TechXclusives->Timing Closure" for tips and suggestions for meeting timing + in your design. + +Number of Timing Constraints that were not applied: 13 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- +* TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | -2.427ns| 10.427ns| 300| 320412 + PCICLK / 2 HIGH 50% PRIORITY 100 | HOLD | -0.035ns| | 1| 35 +---------------------------------------------------------------------------------------------------------- +* TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | SETUP | -0.410ns| 4.410ns| 111| 26123 + PCICLK HIGH 50% PRIORITY 1 | HOLD | 0.001ns| | 0| 0 + | MINPERIOD | 0.000ns| 4.000ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | SETUP | 0.013ns| 4.987ns| 0| 0 + clk_pll = PERIOD TIMEGRP "ftop_dr | HOLD | 0.044ns| | 0| 0 + am0_memc_memc_u_infrastructure_clk_pll" T | | | | | + S_SYS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + Pin to Pin Skew Constraint | MAXDELAY | 0.108ns| 0.450ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 | SETUP | 0.985ns| 4.015ns| 0| 0 + MHz HIGH 50% | HOLD | 0.078ns| | 0| 0 + | MINPERIOD | 0.239ns| 4.761ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VAL | SETUP | 0.535ns| -0.035ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.734ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VAL | SETUP | 0.545ns| -0.045ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.686ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VAL | SETUP | 0.550ns| -0.050ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.665ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VAL | SETUP | 0.551ns| -0.051ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.674ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VAL | SETUP | 0.604ns| -0.104ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.630ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VAL | SETUP | 0.607ns| -0.107ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.611ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VAL | SETUP | 0.639ns| -0.139ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.571ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALI | SETUP | 0.640ns| -0.140ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.591ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VAL | SETUP | 0.648ns| -0.148ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.526ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALI | SETUP | 0.929ns| -0.429ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.158ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | MINPERIOD | 1.071ns| 1.429ns| 0| 0 + clk_mem_pll = PERIOD TIMEGRP "fto | | | | | + p_dram0_memc_memc_u_infrastructure_clk_me | | | | | + m_pll" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GT | SETUP | 2.203ns| 5.797ns| 0| 0 + X_CLK" 125 MHz HIGH 50% | HOLD | 0.078ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP | 2.204ns| 5.796ns| 0| 0 + CLK" 125 MHz HIGH 50% | HOLD | 0.082ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 M | MINPERIOD | 2.462ns| 1.538ns| 0| 0 + Hz HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD | N/A | N/A| N/A| N/A| N/A + TIMEGRP "ftop_dram0_memc_memc_cl | | | | | + k_wr_i" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 4.987ns| 0| 0| 91995| 75758| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 4.987ns| N/A| 0| 0| 75758| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 5.213ns| 0| 412| 0| 13051436| +| TS_CLK_125 | 8.000ns| 10.427ns| N/A| 301| 0| 13032139| 0| +| TS_CLK_250 | 4.000ns| 4.410ns| N/A| 111| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +2 constraints not met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 534 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 6 mins 37 secs +Total CPU time to PAR completion: 7 mins 1 secs + +Peak Memory Usage: 2254 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 412 errors found. + +Number of error messages: 0 +Number of warning messages: 557 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/ml605-20140203_1611/fpgaTop.twr b/logs/ml605-20140203_1611/fpgaTop.twr new file mode 100644 index 00000000..3984e52a --- /dev/null +++ b/logs/ml605-20140203_1611/fpgaTop.twr @@ -0,0 +1,10753 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +/home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc6vlx240t,ff1156,C,-1 (PRODUCTION 1.17 2013-10-13, STEPPING level 0) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 91995 paths analyzed, 3687 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.761ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.985ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_27 (FF) + Requirement: 5.000ns + Data Path Delay: 3.902ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + ------------------------------------------------- --------------------------- + Total 3.902ns (1.375ns logic, 2.527ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.985ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_26 (FF) + Requirement: 5.000ns + Data Path Delay: 3.902ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + ------------------------------------------------- --------------------------- + Total 3.902ns (1.375ns logic, 2.527ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.985ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_25 (FF) + Requirement: 5.000ns + Data Path Delay: 3.902ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + ------------------------------------------------- --------------------------- + Total 3.902ns (1.375ns logic, 2.527ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.985ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_24 (FF) + Requirement: 5.000ns + Data Path Delay: 3.902ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + ------------------------------------------------- --------------------------- + Total 3.902ns (1.375ns logic, 2.527ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.022ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_12 (FF) + Requirement: 5.000ns + Data Path Delay: 3.860ns (Levels of Logic = 3) + Clock Path Skew: -0.083ns (0.990 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y100.CE net (fanout=32) 1.045 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y100.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<15> + ftop/ctop/inf/cp/timeServ_refFreeSpan_12 + ------------------------------------------------- --------------------------- + Total 3.860ns (1.375ns logic, 2.485ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.022ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_15 (FF) + Requirement: 5.000ns + Data Path Delay: 3.860ns (Levels of Logic = 3) + Clock Path Skew: -0.083ns (0.990 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y100.CE net (fanout=32) 1.045 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y100.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<15> + ftop/ctop/inf/cp/timeServ_refFreeSpan_15 + ------------------------------------------------- --------------------------- + Total 3.860ns (1.375ns logic, 2.485ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.022ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_13 (FF) + Requirement: 5.000ns + Data Path Delay: 3.860ns (Levels of Logic = 3) + Clock Path Skew: -0.083ns (0.990 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y100.CE net (fanout=32) 1.045 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y100.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<15> + ftop/ctop/inf/cp/timeServ_refFreeSpan_13 + ------------------------------------------------- --------------------------- + Total 3.860ns (1.375ns logic, 2.485ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.022ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_14 (FF) + Requirement: 5.000ns + Data Path Delay: 3.860ns (Levels of Logic = 3) + Clock Path Skew: -0.083ns (0.990 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.404 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<1> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y100.CE net (fanout=32) 1.045 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y100.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<15> + ftop/ctop/inf/cp/timeServ_refFreeSpan_14 + ------------------------------------------------- --------------------------- + Total 3.860ns (1.375ns logic, 2.485ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.023ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_13 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_25 (FF) + Requirement: 5.000ns + Data Path Delay: 3.864ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_13 to ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_13 + SLICE_X4Y89.C3 net (fanout=4) 0.858 ftop/ctop/inf/cp/timeServ_refFromRise<13> + SLICE_X4Y89.COUT Topcyc 0.340 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<2> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.BMUX Tcinb 0.221 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + ------------------------------------------------- --------------------------- + Total 3.864ns (1.284ns logic, 2.580ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.023ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_13 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_27 (FF) + Requirement: 5.000ns + Data Path Delay: 3.864ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_13 to ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_13 + SLICE_X4Y89.C3 net (fanout=4) 0.858 ftop/ctop/inf/cp/timeServ_refFromRise<13> + SLICE_X4Y89.COUT Topcyc 0.340 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<2> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.BMUX Tcinb 0.221 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + ------------------------------------------------- --------------------------- + Total 3.864ns (1.284ns logic, 2.580ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.023ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_13 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_24 (FF) + Requirement: 5.000ns + Data Path Delay: 3.864ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_13 to ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_13 + SLICE_X4Y89.C3 net (fanout=4) 0.858 ftop/ctop/inf/cp/timeServ_refFromRise<13> + SLICE_X4Y89.COUT Topcyc 0.340 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<2> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.BMUX Tcinb 0.221 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + ------------------------------------------------- --------------------------- + Total 3.864ns (1.284ns logic, 2.580ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.023ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_13 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_26 (FF) + Requirement: 5.000ns + Data Path Delay: 3.864ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_13 to ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.BQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_13 + SLICE_X4Y89.C3 net (fanout=4) 0.858 ftop/ctop/inf/cp/timeServ_refFromRise<13> + SLICE_X4Y89.COUT Topcyc 0.340 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<2> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<3> + SLICE_X4Y90.BMUX Tcinb 0.221 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + ------------------------------------------------- --------------------------- + Total 3.864ns (1.284ns logic, 2.580ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_27 (FF) + Requirement: 5.000ns + Data Path Delay: 3.866ns (Levels of Logic = 2) + Clock Path Skew: -0.075ns (0.995 - 1.070) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y92.DQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X4Y90.A1 net (fanout=4) 0.906 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X4Y90.BMUX Topab 0.515 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + ------------------------------------------------- --------------------------- + Total 3.866ns (1.238ns logic, 2.628ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_26 (FF) + Requirement: 5.000ns + Data Path Delay: 3.866ns (Levels of Logic = 2) + Clock Path Skew: -0.075ns (0.995 - 1.070) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y92.DQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X4Y90.A1 net (fanout=4) 0.906 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X4Y90.BMUX Topab 0.515 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + ------------------------------------------------- --------------------------- + Total 3.866ns (1.238ns logic, 2.628ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_25 (FF) + Requirement: 5.000ns + Data Path Delay: 3.866ns (Levels of Logic = 2) + Clock Path Skew: -0.075ns (0.995 - 1.070) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y92.DQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X4Y90.A1 net (fanout=4) 0.906 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X4Y90.BMUX Topab 0.515 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + ------------------------------------------------- --------------------------- + Total 3.866ns (1.238ns logic, 2.628ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_24 (FF) + Requirement: 5.000ns + Data Path Delay: 3.866ns (Levels of Logic = 2) + Clock Path Skew: -0.075ns (0.995 - 1.070) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y92.DQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X4Y90.A1 net (fanout=4) 0.906 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X4Y90.BMUX Topab 0.515 ftop/ctop/inf/cp/timeServ_jamFracVal<20> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_lut<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A6 net (fanout=4) 0.635 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1109_o_cy<5> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_24 + ------------------------------------------------- --------------------------- + Total 3.866ns (1.238ns logic, 2.628ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_25 (FF) + Requirement: 5.000ns + Data Path Delay: 3.857ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.359 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi1 + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_25 + ------------------------------------------------- --------------------------- + Total 3.857ns (1.330ns logic, 2.527ns route) + (34.5% logic, 65.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_delSecond_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_fracInc_49 (FF) + Requirement: 5.000ns + Data Path Delay: 3.864ns (Levels of Logic = 16) + Clock Path Skew: -0.071ns (0.990 - 1.061) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_delSecond_1 to ftop/ctop/inf/cp/timeServ_fracInc_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y83.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_delSecond_1 + SLICE_X11Y82.B5 net (fanout=1) 0.442 ftop/ctop/inf/cp/timeServ_delSecond<1> + SLICE_X11Y82.COUT Topcyb 0.404 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<3> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_lut<1>_INV_0 + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<3> + SLICE_X11Y83.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<3> + SLICE_X11Y83.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<7> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<7> + SLICE_X11Y84.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<7> + SLICE_X11Y84.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<11> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<11> + SLICE_X11Y85.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<11> + SLICE_X11Y85.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<15> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<15> + SLICE_X11Y86.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<15> + SLICE_X11Y86.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<19> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<19> + SLICE_X11Y87.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<19> + SLICE_X11Y87.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<23> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<23> + SLICE_X11Y88.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<23> + SLICE_X11Y88.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<27> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<27> + SLICE_X11Y89.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<27> + SLICE_X11Y89.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<31> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<31> + SLICE_X11Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<31> + SLICE_X11Y90.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<35> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<35> + SLICE_X11Y91.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<35> + SLICE_X11Y91.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<39> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<39> + SLICE_X11Y92.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<39> + SLICE_X11Y92.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<43> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<43> + SLICE_X11Y93.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<43> + SLICE_X11Y93.COUT Tbyp 0.078 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<47> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<47> + SLICE_X11Y94.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_cy<47> + SLICE_X11Y94.BMUX Tcinb 0.273 ftop/ctop/inf/cp/_281474976710656_MINUS_timeServ_delSecond__q1<49> + ftop/ctop/inf/cp/Msub__281474976710656_MINUS_timeServ_delSecond__q1_xor<49> + SLICE_X8Y98.B2 net (fanout=29) 0.899 ftop/ctop/inf/cp/_281474976710656_MINUS_timeServ_delSecond__q1<49> + SLICE_X8Y98.COUT Topcyb 0.406 ftop/ctop/inf/cp/timeServ_fracInc<43> + ftop/ctop/inf/cp/Maccum_timeServ_fracInc_lut<41> + ftop/ctop/inf/cp/Maccum_timeServ_fracInc_cy<43> + SLICE_X8Y99.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Maccum_timeServ_fracInc_cy<43> + SLICE_X8Y99.COUT Tbyp 0.078 ftop/ctop/inf/cp/timeServ_fracInc<47> + ftop/ctop/inf/cp/Maccum_timeServ_fracInc_cy<47> + SLICE_X8Y100.CIN net (fanout=1) 0.023 ftop/ctop/inf/cp/Maccum_timeServ_fracInc_cy<47> + SLICE_X8Y100.CLK Tcinck 0.100 ftop/ctop/inf/cp/timeServ_fracInc<49> + ftop/ctop/inf/cp/Maccum_timeServ_fracInc_xor<49> + ftop/ctop/inf/cp/timeServ_fracInc_49 + ------------------------------------------------- --------------------------- + Total 3.864ns (2.500ns logic, 1.364ns route) + (64.7% logic, 35.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_26 (FF) + Requirement: 5.000ns + Data Path Delay: 3.857ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.359 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi1 + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_26 + ------------------------------------------------- --------------------------- + Total 3.857ns (1.330ns logic, 2.527ns route) + (34.5% logic, 65.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSpan_27 (FF) + Requirement: 5.000ns + Data Path Delay: 3.857ns (Levels of Logic = 3) + Clock Path Skew: -0.078ns (0.995 - 1.073) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_14 to ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y90.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_refFromRise<15> + ftop/ctop/inf/cp/timeServ_refFromRise_14 + SLICE_X5Y89.B3 net (fanout=4) 0.852 ftop/ctop/inf/cp/timeServ_refFromRise<14> + SLICE_X5Y89.COUT Topcyb 0.359 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi1 + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X5Y90.AMUX Tcina 0.248 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A4 net (fanout=4) 0.588 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X9Y90.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_delSecond_EN + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y103.CE net (fanout=32) 1.087 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X9Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSpan<27> + ftop/ctop/inf/cp/timeServ_refFreeSpan_27 + ------------------------------------------------- --------------------------- + Total 3.857ns (1.330ns logic, 2.527ns route) + (34.5% logic, 65.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_25 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.487 - 0.450) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_25 to ftop/ctop/inf/cp/timeServ_refFreeSamp_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y102.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<27> + ftop/ctop/inf/cp/timeServ_refFreeCount_25 + SLICE_X8Y103.BX net (fanout=4) 0.106 ftop/ctop/inf/cp/timeServ_refFreeCount<25> + SLICE_X8Y103.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_refFreeSamp<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_25 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.009ns logic, 0.106ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_17 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.484 - 0.447) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_17 to ftop/ctop/inf/cp/timeServ_refFreeSamp_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y100.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<19> + ftop/ctop/inf/cp/timeServ_refFreeCount_17 + SLICE_X8Y101.BX net (fanout=4) 0.106 ftop/ctop/inf/cp/timeServ_refFreeCount<17> + SLICE_X8Y101.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_refFreeSamp<19> + ftop/ctop/inf/cp/timeServ_refFreeSamp_17 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.009ns logic, 0.106ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.079ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_27 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_27 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.487 - 0.450) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_27 to ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y102.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<27> + ftop/ctop/inf/cp/timeServ_refFreeCount_27 + SLICE_X8Y103.DX net (fanout=3) 0.107 ftop/ctop/inf/cp/timeServ_refFreeCount<27> + SLICE_X8Y103.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_refFreeSamp<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.009ns logic, 0.107ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.079ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_19 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.484 - 0.447) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_19 to ftop/ctop/inf/cp/timeServ_refFreeSamp_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y100.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<19> + ftop/ctop/inf/cp/timeServ_refFreeCount_19 + SLICE_X8Y101.DX net (fanout=4) 0.107 ftop/ctop/inf/cp/timeServ_refFreeCount<19> + SLICE_X8Y101.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_refFreeSamp<19> + ftop/ctop/inf/cp/timeServ_refFreeSamp_19 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.009ns logic, 0.107ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.109ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y112.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + SLICE_X1Y112.A5 net (fanout=3) 0.066 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + SLICE_X1Y112.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg_INV_458_o1_INV_0 + ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.109ns (0.043ns logic, 0.066ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_45 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.056 - 0.048) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 to ftop/ctop/inf/cp/timeServ_jamFracVal_45 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y106.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_29 + SLICE_X9Y104.BX net (fanout=1) 0.097 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<29> + SLICE_X9Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_45 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_46 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.056 - 0.048) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 to ftop/ctop/inf/cp/timeServ_jamFracVal_46 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y106.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_30 + SLICE_X9Y104.CX net (fanout=1) 0.097 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<30> + SLICE_X9Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_46 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_44 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.056 - 0.048) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 to ftop/ctop/inf/cp/timeServ_jamFracVal_44 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y106.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_28 + SLICE_X9Y104.AX net (fanout=1) 0.097 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<28> + SLICE_X9Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_44 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_47 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.056 - 0.048) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 to ftop/ctop/inf/cp/timeServ_jamFracVal_47 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y106.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_31 + SLICE_X9Y104.DX net (fanout=1) 0.097 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<31> + SLICE_X9Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<47> + ftop/ctop/inf/cp/timeServ_jamFracVal_47 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.112ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_7 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_7 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y110.DQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_7 + SLICE_X4Y111.DX net (fanout=2) 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + SLICE_X4Y111.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_7 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.112ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y110.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 + SLICE_X4Y111.AX net (fanout=2) 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<4> + SLICE_X4Y111.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.026ns logic, 0.098ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y110.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_6 + SLICE_X4Y111.CX net (fanout=2) 0.100 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<6> + SLICE_X4Y111.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_6 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_5 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.064 - 0.052) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_5 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y110.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_5 + SLICE_X4Y111.BX net (fanout=2) 0.100 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<5> + SLICE_X4Y111.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<7> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_5 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y87.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y87.A5 net (fanout=3) 0.071 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y87.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg_INV_458_o1_INV_0 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.114ns (0.043ns logic, 0.071ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X124Y161.DQ Tcko 0.115 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 + SLICE_X124Y161.A4 net (fanout=1) 0.101 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + SLICE_X124Y161.CLK Tah (-Th) 0.101 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3>_rt + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.014ns logic, 0.101ns route) + (12.2% logic, 87.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_xo2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_xo2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_xo2 to ftop/ctop/inf/cp/timeServ_xo2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y96.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/timeServ_xo2 + SLICE_X11Y96.A5 net (fanout=5) 0.072 ftop/ctop/inf/cp/timeServ_xo2 + SLICE_X11Y96.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/Mcount_timeServ_refFreeCount_lut<0>_INV_0 + ftop/ctop/inf/cp/timeServ_xo2 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.043ns logic, 0.072ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.060 - 0.049) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y107.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 + SLICE_X7Y107.BX net (fanout=2) 0.105 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<1> + SLICE_X7Y107.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.022ns logic, 0.105ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y114.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + SLICE_X4Y114.A5 net (fanout=3) 0.077 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + SLICE_X4Y114.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg_INV_458_o1_INV_0 + ftop/ctop/inf/cp/timeServ_refPerPPS/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/itc1/now/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/itc1/now/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/itc1/now/sync/sToggleReg to ftop/ctop/inf/itc1/now/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X38Y81.AQ Tcko 0.115 ftop/ctop/inf/itc1/now/sync/sToggleReg + ftop/ctop/inf/itc1/now/sync/sToggleReg + SLICE_X38Y81.A5 net (fanout=3) 0.077 ftop/ctop/inf/itc1/now/sync/sToggleReg + SLICE_X38Y81.CLK Tah (-Th) 0.076 ftop/ctop/inf/itc1/now/sync/sToggleReg + ftop/ctop/inf/itc1/now/sync/sToggleReg_INV_458_o1_INV_0 + ftop/ctop/inf/itc1/now/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.120ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y107.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + SLICE_X6Y107.C5 net (fanout=2) 0.078 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + SLICE_X6Y107.CLK Tah (-Th) 0.056 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[2]_xor_20_OUT_1_xo<0>1 + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.120ns (0.042ns logic, 0.078ns route) + (35.0% logic, 65.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Location pin: IDELAYCTRL_X1Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Location pin: IDELAYCTRL_X1Y4.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Location pin: IDELAYCTRL_X2Y1.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Location pin: IDELAYCTRL_X2Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Location pin: MMCM_ADV_X0Y6.CLKOUT0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Location pin: MMCM_ADV_X0Y6.CLKOUT2 + Clock network: ftop/dram0/memc_memc/clk_wr_i +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.571ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys0_clk_O_BUFG/I0 + Logical resource: ftop/sys0_clk_O_BUFG/I0 + Location pin: BUFGCTRL_X0Y1.I0 + Clock network: ftop/sys0_clk_O +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKIN(Finmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKFBOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Location pin: MMCM_ADV_X0Y6.CLKFBOUT + Clock network: ftop/dram0/memc_memc/u_infrastructure/clkfbout_pll +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Location pin: MMCM_ADV_X0Y6.CLKOUT1 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_pll +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dLastState/SR + Location pin: SLICE_X0Y81.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg1/SR + Location pin: SLICE_X0Y81.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Location pin: SLICE_X0Y81.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg/SR + Location pin: SLICE_X0Y122.SR + Clock network: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Location pin: SLICE_X1Y112.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sSyncReg1/SR + Location pin: SLICE_X1Y123.SR + Clock network: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sSyncReg2/SR + Location pin: SLICE_X1Y123.SR + Clock network: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dLastState/SR + Location pin: SLICE_X1Y133.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.538ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% +PRIORITY 100; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 13032139 paths analyzed, 145457 endpoints analyzed, 301 failing endpoints + 301 timing errors detected. (300 setup errors, 1 hold error, 0 component switching limit errors) + Minimum period is 10.427ns. +-------------------------------------------------------------------------------- +Slack (setup path): -2.427ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 (FF) + Requirement: 8.000ns + Data Path Delay: 10.277ns (Levels of Logic = 8) + Clock Path Skew: -0.081ns (1.023 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CE net (fanout=2) 0.716 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ------------------------------------------------- --------------------------- + Total 10.277ns (1.520ns logic, 8.757ns route) + (14.8% logic, 85.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.425ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 (FF) + Requirement: 8.000ns + Data Path Delay: 10.273ns (Levels of Logic = 8) + Clock Path Skew: -0.083ns (1.021 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CE net (fanout=2) 0.712 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ------------------------------------------------- --------------------------- + Total 10.273ns (1.520ns logic, 8.753ns route) + (14.8% logic, 85.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.392ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 (FF) + Requirement: 8.000ns + Data Path Delay: 10.239ns (Levels of Logic = 8) + Clock Path Skew: -0.084ns (1.020 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.C6 net (fanout=15) 1.151 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.C Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CE net (fanout=1) 0.800 ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CLK Tceck 0.246 ftop/ctop/inf/cp/wrkAct_D_IN<1>3 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + ------------------------------------------------- --------------------------- + Total 10.239ns (1.448ns logic, 8.791ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.386ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 (FF) + Requirement: 8.000ns + Data Path Delay: 10.235ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.022 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.B6 net (fanout=15) 1.156 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.B Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CE net (fanout=1) 0.719 ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ------------------------------------------------- --------------------------- + Total 10.235ns (1.520ns logic, 8.715ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.386ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 (FF) + Requirement: 8.000ns + Data Path Delay: 10.235ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.022 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.B6 net (fanout=15) 1.156 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.B Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CE net (fanout=1) 0.719 ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 + ------------------------------------------------- --------------------------- + Total 10.235ns (1.520ns logic, 8.715ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.377ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 (FF) + Requirement: 8.000ns + Data Path Delay: 10.224ns (Levels of Logic = 8) + Clock Path Skew: -0.084ns (1.023 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CE net (fanout=2) 0.716 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ------------------------------------------------- --------------------------- + Total 10.224ns (1.520ns logic, 8.704ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.375ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 (FF) + Requirement: 8.000ns + Data Path Delay: 10.220ns (Levels of Logic = 8) + Clock Path Skew: -0.086ns (1.021 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CE net (fanout=2) 0.712 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ------------------------------------------------- --------------------------- + Total 10.220ns (1.520ns logic, 8.700ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.342ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 (FF) + Requirement: 8.000ns + Data Path Delay: 10.186ns (Levels of Logic = 8) + Clock Path Skew: -0.087ns (1.020 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.C6 net (fanout=15) 1.151 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.C Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CE net (fanout=1) 0.800 ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CLK Tceck 0.246 ftop/ctop/inf/cp/wrkAct_D_IN<1>3 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + ------------------------------------------------- --------------------------- + Total 10.186ns (1.448ns logic, 8.738ns route) + (14.2% logic, 85.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.336ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 (FF) + Requirement: 8.000ns + Data Path Delay: 10.182ns (Levels of Logic = 8) + Clock Path Skew: -0.085ns (1.022 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.B6 net (fanout=15) 1.156 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.B Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CE net (fanout=1) 0.719 ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ------------------------------------------------- --------------------------- + Total 10.182ns (1.520ns logic, 8.662ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.336ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 (FF) + Requirement: 8.000ns + Data Path Delay: 10.182ns (Levels of Logic = 8) + Clock Path Skew: -0.085ns (1.022 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.B6 net (fanout=15) 1.156 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.B Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CE net (fanout=1) 0.719 ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_1 + ------------------------------------------------- --------------------------- + Total 10.182ns (1.520ns logic, 8.662ns route) + (14.9% logic, 85.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.326ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 (FF) + Requirement: 8.000ns + Data Path Delay: 10.175ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.022 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X59Y114.B6 net (fanout=15) 1.293 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X59Y114.B Tilo 0.068 ftop/ctop/inf/cp/_n13575<34>2_REPLICA_221 + ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CE net (fanout=1) 0.556 ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CLK Tceck 0.284 ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + ------------------------------------------------- --------------------------- + Total 10.175ns (1.486ns logic, 8.689ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.316ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 (FF) + Requirement: 8.000ns + Data Path Delay: 10.165ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.023 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C4 net (fanout=56) 1.203 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_523 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.B3 net (fanout=2) 1.276 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.BMUX Topbb 0.389 ftop/ctop/inf/cp/wci_13_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_2_f8 + SLICE_X63Y103.D5 net (fanout=3) 0.616 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 + SLICE_X63Y103.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T1 + SLICE_X58Y104.C4 net (fanout=37) 0.542 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CE net (fanout=2) 0.716 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ------------------------------------------------- --------------------------- + Total 10.165ns (1.564ns logic, 8.601ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 (FF) + Requirement: 8.000ns + Data Path Delay: 10.161ns (Levels of Logic = 8) + Clock Path Skew: -0.084ns (1.021 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C4 net (fanout=56) 1.203 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_523 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.B3 net (fanout=2) 1.276 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.BMUX Topbb 0.389 ftop/ctop/inf/cp/wci_13_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_2_f8 + SLICE_X63Y103.D5 net (fanout=3) 0.616 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 + SLICE_X63Y103.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T1 + SLICE_X58Y104.C4 net (fanout=37) 0.542 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CE net (fanout=2) 0.712 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ------------------------------------------------- --------------------------- + Total 10.161ns (1.564ns logic, 8.597ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.312ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 (FF) + Requirement: 8.000ns + Data Path Delay: 10.161ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.023 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A6 net (fanout=56) 1.227 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CE net (fanout=2) 0.716 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X61Y103.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_34 + ------------------------------------------------- --------------------------- + Total 10.161ns (1.564ns logic, 8.597ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.310ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 (FF) + Requirement: 8.000ns + Data Path Delay: 10.157ns (Levels of Logic = 8) + Clock Path Skew: -0.084ns (1.021 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A6 net (fanout=56) 1.227 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y114.B6 net (fanout=15) 1.201 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y114.B Tilo 0.068 ftop/flash0/flashC_tsWD<5> + ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CE net (fanout=2) 0.712 ftop/ctop/inf/cp/cpReq_EN_REPLICA_297 + SLICE_X59Y102.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_27 + ------------------------------------------------- --------------------------- + Total 10.157ns (1.564ns logic, 8.593ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.288ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<22>_REPLICA_30 (FF) + Requirement: 8.000ns + Data Path Delay: 10.137ns (Levels of Logic = 8) + Clock Path Skew: -0.082ns (1.022 - 1.104) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_respF/empty_reg to ftop/ctop/inf/cp/cpReq<22>_REPLICA_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X65Y103.DQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + ftop/ctop/inf/cp/wci_10_respF/empty_reg + SLICE_X46Y109.A4 net (fanout=41) 1.387 ftop/ctop/inf/cp/wci_10_respF_EMPTY_N + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X59Y114.B6 net (fanout=15) 1.293 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X59Y114.B Tilo 0.068 ftop/ctop/inf/cp/_n13575<34>2_REPLICA_221 + ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CE net (fanout=1) 0.556 ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CLK Tceck 0.246 ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + ftop/ctop/inf/cp/cpReq<22>_REPLICA_30 + ------------------------------------------------- --------------------------- + Total 10.137ns (1.448ns logic, 8.689ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.281ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 (FF) + Requirement: 8.000ns + Data Path Delay: 10.127ns (Levels of Logic = 8) + Clock Path Skew: -0.085ns (1.020 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C4 net (fanout=56) 1.203 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_523 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.B3 net (fanout=2) 1.276 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.BMUX Topbb 0.389 ftop/ctop/inf/cp/wci_13_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_2_f8 + SLICE_X63Y103.D5 net (fanout=3) 0.616 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 + SLICE_X63Y103.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T1 + SLICE_X58Y104.C4 net (fanout=37) 0.542 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.C6 net (fanout=15) 1.151 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.C Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CE net (fanout=1) 0.800 ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CLK Tceck 0.246 ftop/ctop/inf/cp/wrkAct_D_IN<1>3 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + ------------------------------------------------- --------------------------- + Total 10.127ns (1.492ns logic, 8.635ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 (FF) + Requirement: 8.000ns + Data Path Delay: 10.123ns (Levels of Logic = 8) + Clock Path Skew: -0.085ns (1.020 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A6 net (fanout=56) 1.227 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.C6 net (fanout=15) 1.151 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.C Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CE net (fanout=1) 0.800 ftop/ctop/inf/cp/cpReq_EN_REPLICA_295 + SLICE_X60Y101.CLK Tceck 0.246 ftop/ctop/inf/cp/wrkAct_D_IN<1>3 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_4 + ------------------------------------------------- --------------------------- + Total 10.123ns (1.492ns logic, 8.631ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.276ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_busy (FF) + Destination: ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 (FF) + Requirement: 8.000ns + Data Path Delay: 10.122ns (Levels of Logic = 8) + Clock Path Skew: -0.085ns (1.022 - 1.107) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_busy to ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y104.AQ Tcko 0.337 ftop/ctop/inf/cp/wci_10_busy + ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A5 net (fanout=40) 1.334 ftop/ctop/inf/cp/wci_10_busy + SLICE_X46Y109.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864_REPLICA_586 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.B2 net (fanout=5) 1.159 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_529 + SLICE_X63Y108.BMUX Topbb 0.389 ftop/ctop/inf/cp/cpReq<36>_REPLICA_572 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750_5 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326_2_f8 + SLICE_X58Y102.D6 net (fanout=3) 0.642 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 + SLICE_X58Y102.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T1 + SLICE_X58Y104.C2 net (fanout=3) 0.605 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X59Y114.B6 net (fanout=15) 1.293 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X59Y114.B Tilo 0.068 ftop/ctop/inf/cp/_n13575<34>2_REPLICA_221 + ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CE net (fanout=1) 0.556 ftop/ctop/inf/cp/cpReq_EN_REPLICA_298 + SLICE_X56Y105.CLK Tceck 0.284 ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + ftop/ctop/inf/cp/cpReq<23>_REPLICA_172 + ------------------------------------------------- --------------------------- + Total 10.122ns (1.486ns logic, 8.636ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.275ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_10_reqF_cntr_r (FF) + Destination: ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 (FF) + Requirement: 8.000ns + Data Path Delay: 10.123ns (Levels of Logic = 8) + Clock Path Skew: -0.083ns (1.022 - 1.105) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_10_reqF_cntr_r to ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X64Y104.AQ Tcko 0.381 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C4 net (fanout=56) 1.203 ftop/ctop/inf/cp/wci_10_reqF_cntr_r + SLICE_X46Y103.C Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_523 + ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.B3 net (fanout=2) 1.276 ftop/ctop/inf/cp/NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918_REPLICA_524 + SLICE_X65Y106.BMUX Topbb 0.389 ftop/ctop/inf/cp/wci_13_wReset_n + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951_2_f8 + SLICE_X63Y103.D5 net (fanout=3) 0.616 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 + SLICE_X63Y103.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T1 + SLICE_X58Y104.C4 net (fanout=37) 0.542 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T + SLICE_X58Y104.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<22>_REPLICA_29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C2 net (fanout=1) 0.807 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X53Y102.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A3 net (fanout=1) 0.666 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead22 + SLICE_X57Y105.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead12 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X84Y122.C6 net (fanout=20) 1.574 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X84Y122.C Tilo 0.068 ftop/ctop/inf/noc_sm1/pktMerge/fi0HasPrio + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X63Y113.B6 net (fanout=15) 1.156 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X63Y113.B Tilo 0.068 ftop/ctop/inf/cp/wci_1_respF/RST_inv + ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CE net (fanout=1) 0.719 ftop/ctop/inf/cp/cpReq_EN_REPLICA_296 + SLICE_X63Y99.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ftop/ctop/inf/cp/cpReq<7>_REPLICA_7 + ------------------------------------------------- --------------------------- + Total 10.123ns (1.564ns logic, 8.559ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack (hold path): -0.035ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pAF_head_wrapped (FF) + Destination: ftop/pciw_i2pAF_tail_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.287ns (Levels of Logic = 1) + Clock Path Skew: 0.133ns (1.223 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pAF_head_wrapped to ftop/pciw_i2pAF_tail_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y159.AQ Tcko 0.098 ftop/pciw_i2pAF_head_wrapped + ftop/pciw_i2pAF_head_wrapped + SLICE_X144Y163.C5 net (fanout=7) 0.265 ftop/pciw_i2pAF_head_wrapped + SLICE_X144Y163.CLK Tah (-Th) 0.076 ftop/pciw_i2pAF_tail_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_enq_update_tail11 + ftop/pciw_i2pAF_tail_wrapped + ------------------------------------------------- --------------------------- + Total 0.287ns (0.022ns logic, 0.265ns route) + (7.7% logic, 92.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_69 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_69_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.264ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.170 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_69 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_69_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y116.BQ Tcko 0.098 ftop/pciw_p2iS<71> + ftop/pciw_p2iS_69 + SLICE_X152Y112.BX net (fanout=1) 0.193 ftop/pciw_p2iS<69> + SLICE_X152Y112.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<71> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_69_0 + ------------------------------------------------- --------------------------- + Total 0.264ns (0.071ns logic, 0.193ns route) + (26.9% logic, 73.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.001ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_101 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_101_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.267ns (Levels of Logic = 0) + Clock Path Skew: 0.077ns (1.173 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_101 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_101_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y116.BQ Tcko 0.098 ftop/pciw_p2iS<103> + ftop/pciw_p2iS_101 + SLICE_X158Y116.BX net (fanout=1) 0.196 ftop/pciw_p2iS<101> + SLICE_X158Y116.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<103> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_101_0 + ------------------------------------------------- --------------------------- + Total 0.267ns (0.071ns logic, 0.196ns route) + (26.6% logic, 73.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_1 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.264ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.163 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_1 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y112.BQ Tcko 0.098 ftop/pciw_p2iS<3> + ftop/pciw_p2iS_1 + SLICE_X146Y109.BX net (fanout=1) 0.193 ftop/pciw_p2iS<1> + SLICE_X146Y109.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<3> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_1_0 + ------------------------------------------------- --------------------------- + Total 0.264ns (0.071ns logic, 0.193ns route) + (26.9% logic, 73.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/app/appW1/wmemi_reqF_q_1_26 (FF) + Destination: ftop/ctop/app/appW1/wmemi_reqF_q_0_26 (FF) + Requirement: 0.000ns + Data Path Delay: 0.110ns (Levels of Logic = 1) + Clock Path Skew: 0.108ns (0.736 - 0.628) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/app/appW1/wmemi_reqF_q_1_26 to ftop/ctop/app/appW1/wmemi_reqF_q_0_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X31Y159.DQ Tcko 0.098 ftop/ctop/app/appW1/wmemi_reqF_q_1<26> + ftop/ctop/app/appW1/wmemi_reqF_q_1_26 + SLICE_X30Y160.C6 net (fanout=1) 0.088 ftop/ctop/app/appW1/wmemi_reqF_q_1<26> + SLICE_X30Y160.CLK Tah (-Th) 0.076 ftop/ctop_wmemiM0_MAddr<15> + ftop/ctop/app/appW1/wmemi_reqF_q_0_D_IN<26>1 + ftop/ctop/app/appW1/wmemi_reqF_q_0_26 + ------------------------------------------------- --------------------------- + Total 0.110ns (0.022ns logic, 0.088ns route) + (20.0% logic, 80.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_102 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_102_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.077ns (1.173 - 1.096) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_102 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_102_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y116.CQ Tcko 0.098 ftop/pciw_p2iS<103> + ftop/pciw_p2iS_102 + SLICE_X158Y116.CX net (fanout=1) 0.200 ftop/pciw_p2iS<102> + SLICE_X158Y116.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<103> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_102_0 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.068ns logic, 0.200ns route) + (25.4% logic, 74.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.004ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_117 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_117_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.077ns (1.170 - 1.093) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_117 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_117_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y110.BQ Tcko 0.098 ftop/pciw_p2iS<119> + ftop/pciw_p2iS_117 + SLICE_X158Y110.BX net (fanout=1) 0.199 ftop/pciw_p2iS<117> + SLICE_X158Y110.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<119> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_117_0 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.071ns logic, 0.199ns route) + (26.3% logic, 73.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_15 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_15_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.168 - 1.093) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_15 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_15_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y111.DQ Tcko 0.115 ftop/pciw_p2iS<15> + ftop/pciw_p2iS_15 + SLICE_X152Y109.DX net (fanout=1) 0.192 ftop/pciw_p2iS<15> + SLICE_X152Y109.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<15> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_15_0 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.077ns logic, 0.192ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.012ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_116 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_116_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 0) + Clock Path Skew: 0.077ns (1.170 - 1.093) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_116 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_116_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y110.AQ Tcko 0.098 ftop/pciw_p2iS<119> + ftop/pciw_p2iS_116 + SLICE_X158Y110.AX net (fanout=1) 0.216 ftop/pciw_p2iS<116> + SLICE_X158Y110.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<119> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_116_0 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.062ns logic, 0.216ns route) + (22.3% logic, 77.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.013ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_27 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_27_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 0) + Clock Path Skew: 0.067ns (1.160 - 1.093) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_27 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_27_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X157Y109.DQ Tcko 0.098 ftop/pciw_p2iS<27> + ftop/pciw_p2iS_27 + SLICE_X158Y102.DX net (fanout=1) 0.209 ftop/pciw_p2iS<27> + SLICE_X158Y102.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<27> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_27_0 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.060ns logic, 0.209ns route) + (22.3% logic, 77.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_127 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_127_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 0) + Clock Path Skew: 0.068ns (1.163 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_127 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_127_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y111.DQ Tcko 0.098 ftop/pciw_p2iS<127> + ftop/pciw_p2iS_127 + SLICE_X158Y104.DX net (fanout=1) 0.211 ftop/pciw_p2iS<127> + SLICE_X158Y104.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<127> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_127_0 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.060ns logic, 0.211ns route) + (22.1% logic, 77.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_23 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_23_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.273ns (Levels of Logic = 0) + Clock Path Skew: 0.069ns (1.164 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_23 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_23_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y111.DQ Tcko 0.098 ftop/pciw_p2iS<23> + ftop/pciw_p2iS_23 + SLICE_X158Y105.DX net (fanout=1) 0.213 ftop/pciw_p2iS<23> + SLICE_X158Y105.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<23> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_23_0 + ------------------------------------------------- --------------------------- + Total 0.273ns (0.060ns logic, 0.213ns route) + (22.0% logic, 78.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_24 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_24_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 0) + Clock Path Skew: 0.067ns (1.160 - 1.093) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_24 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_24_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X157Y109.AQ Tcko 0.098 ftop/pciw_p2iS<27> + ftop/pciw_p2iS_24 + SLICE_X158Y102.AX net (fanout=1) 0.209 ftop/pciw_p2iS<24> + SLICE_X158Y102.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<27> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_24_0 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.062ns logic, 0.209ns route) + (22.9% logic, 77.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_20 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_20_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 0) + Clock Path Skew: 0.069ns (1.164 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_20 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_20_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y111.AQ Tcko 0.098 ftop/pciw_p2iS<23> + ftop/pciw_p2iS_20 + SLICE_X158Y105.AX net (fanout=1) 0.212 ftop/pciw_p2iS<20> + SLICE_X158Y105.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<23> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_20_0 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.062ns logic, 0.212ns route) + (22.6% logic, 77.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_2 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.060ns (1.131 - 1.071) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_2 to ftop/pciw_pciDevice/dD_OUT_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y105.CQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<3> + ftop/pciw_pciDevice/sDataSyncIn_2 + SLICE_X130Y101.CX net (fanout=1) 0.259 ftop/pciw_pciDevice/sDataSyncIn<2> + SLICE_X130Y101.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<3> + ftop/pciw_pciDevice/dD_OUT_2 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.009ns logic, 0.259ns route) + (3.4% logic, 96.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_1 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.060ns (1.131 - 1.071) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_1 to ftop/pciw_pciDevice/dD_OUT_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y105.BQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<3> + ftop/pciw_pciDevice/sDataSyncIn_1 + SLICE_X130Y101.BX net (fanout=1) 0.259 ftop/pciw_pciDevice/sDataSyncIn<1> + SLICE_X130Y101.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<3> + ftop/pciw_pciDevice/dD_OUT_1 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.009ns logic, 0.259ns route) + (3.4% logic, 96.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_22 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_22_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 0) + Clock Path Skew: 0.069ns (1.164 - 1.095) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_22 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_22_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y111.CQ Tcko 0.098 ftop/pciw_p2iS<23> + ftop/pciw_p2iS_22 + SLICE_X158Y105.CX net (fanout=1) 0.210 ftop/pciw_p2iS<22> + SLICE_X158Y105.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<23> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_22_0 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.068ns logic, 0.210ns route) + (24.5% logic, 75.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.021ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_0 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.060ns (1.131 - 1.071) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_0 to ftop/pciw_pciDevice/dD_OUT_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y105.AQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<3> + ftop/pciw_pciDevice/sDataSyncIn_0 + SLICE_X130Y101.AX net (fanout=1) 0.261 ftop/pciw_pciDevice/sDataSyncIn<0> + SLICE_X130Y101.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<3> + ftop/pciw_pciDevice/dD_OUT_0 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.009ns logic, 0.261ns route) + (3.3% logic, 96.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.021ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_91 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_91_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 0) + Clock Path Skew: 0.064ns (1.158 - 1.094) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_91 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_91_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y110.DQ Tcko 0.098 ftop/pciw_p2iS<91> + ftop/pciw_p2iS_91 + SLICE_X152Y101.DX net (fanout=1) 0.214 ftop/pciw_p2iS<91> + SLICE_X152Y101.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<91> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_91_0 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.060ns logic, 0.214ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.021ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_3 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.060ns (1.131 - 1.071) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_3 to ftop/pciw_pciDevice/dD_OUT_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y105.DQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<3> + ftop/pciw_pciDevice/sDataSyncIn_3 + SLICE_X130Y101.DX net (fanout=1) 0.261 ftop/pciw_pciDevice/sDataSyncIn<3> + SLICE_X130Y101.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<3> + ftop/pciw_pciDevice/dD_OUT_3 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.009ns logic, 0.261ns route) + (3.3% logic, 96.7% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Location pin: GTXE1_X0Y15.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Location pin: GTXE1_X0Y14.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Location pin: GTXE1_X0Y13.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Location pin: GTXE1_X0Y12.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% +PRIORITY 1; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 19297 paths analyzed, 6214 endpoints analyzed, 111 failing endpoints + 111 timing errors detected. (111 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.410ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMD + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMC + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMB + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.410ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr12_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.305ns (Levels of Logic = 2) + Clock Path Skew: -0.042ns (1.592 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr12_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X148Y177.CE net (fanout=13) 0.641 ftop/pciw_fI2P/BUS_0003 + SLICE_X148Y177.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<71> + ftop/pciw_fI2P/Mram_arr12_RAMA + ------------------------------------------------- --------------------------- + Total 4.305ns (1.108ns logic, 3.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.337ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.235ns (Levels of Logic = 2) + Clock Path Skew: -0.039ns (1.595 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y171.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y171.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD + ------------------------------------------------- --------------------------- + Total 4.235ns (1.108ns logic, 3.127ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.330ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.226ns (Levels of Logic = 2) + Clock Path Skew: -0.041ns (1.593 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y174.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y174.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMA + ------------------------------------------------- --------------------------- + Total 4.226ns (1.108ns logic, 3.118ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.330ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.226ns (Levels of Logic = 2) + Clock Path Skew: -0.041ns (1.593 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y174.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y174.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.226ns (1.108ns logic, 3.118ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.330ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.226ns (Levels of Logic = 2) + Clock Path Skew: -0.041ns (1.593 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y174.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y174.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.226ns (1.108ns logic, 3.118ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.330ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr1_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.226ns (Levels of Logic = 2) + Clock Path Skew: -0.041ns (1.593 - 1.634) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X155Y171.D6 net (fanout=83) 2.107 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X155Y171.D Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A5 net (fanout=7) 0.449 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_234 + SLICE_X149Y173.A Tilo 0.068 ftop/pciw_i2pS<75> + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X146Y174.CE net (fanout=13) 0.562 ftop/pciw_fI2P/BUS_0003 + SLICE_X146Y174.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<5> + ftop/pciw_fI2P/Mram_arr1_RAMB + ------------------------------------------------- --------------------------- + Total 4.226ns (1.108ns logic, 3.118ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack (hold path): 0.001ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (1.227 - 1.147) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y161.CQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X149Y166.B5 net (fanout=84) 0.212 ftop/pciw_i2pS<134> + SLICE_X149Y166.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/MUX_pciw_Prelude_inst_changeSpecialWires_2_rg_write_1__SEL_13 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.058ns logic, 0.212ns route) + (21.5% logic, 78.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.011ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_58 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.218 - 1.139) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_58 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y167.CQ Tcko 0.098 ftop/pciw_i2pS<59> + ftop/pciw_i2pS_58 + SLICE_X142Y167.C2 net (fanout=1) 0.257 ftop/pciw_i2pS<58> + SLICE_X142Y167.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN541 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 + ------------------------------------------------- --------------------------- + Total 0.279ns (0.022ns logic, 0.257ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 (FF) + Requirement: 0.000ns + Data Path Delay: 0.284ns (Levels of Logic = 1) + Clock Path Skew: 0.081ns (1.228 - 1.147) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y161.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X150Y166.B5 net (fanout=83) 0.226 ftop/pciw_i2pS<135> + SLICE_X150Y166.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<67> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN621 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 + ------------------------------------------------- --------------------------- + Total 0.284ns (0.058ns logic, 0.226ns route) + (20.4% logic, 79.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.104ns (Levels of Logic = 1) + Clock Path Skew: 0.085ns (0.533 - 0.448) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + SLICE_X151Y132.BQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + SLICE_X149Y132.C3 net (fanout=8) 0.180 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + SLICE_X149Y132.C Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>51 + PCIE_X0Y1.PIPERX2DATA14 net (fanout=1) 0.282 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<14> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.490 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ---------------------------------------------------- --------------------------- + Total 0.104ns (-0.358ns logic, 0.462ns route) + (-344.2% logic, 444.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (0.533 - 0.447) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------------ ------------------- + SLICE_X149Y132.CQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q + SLICE_X146Y131.D6 net (fanout=6) 0.187 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxvalid_q + SLICE_X146Y131.D Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2CHARISK<0> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/USER_RXCHARISK<0>1 + PCIE_X0Y1.PIPERX2CHARISK0 net (fanout=1) 0.292 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2CHARISK<0> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.505 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ------------------------------------------------------ --------------------------- + Total 0.106ns (-0.373ns logic, 0.479ns route) + (-351.9% logic, 451.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 (FF) + Requirement: 0.000ns + Data Path Delay: 0.289ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (1.227 - 1.147) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y161.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X149Y166.B4 net (fanout=83) 0.231 ftop/pciw_i2pS<135> + SLICE_X149Y166.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/MUX_pciw_Prelude_inst_changeSpecialWires_2_rg_write_1__SEL_13 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + ------------------------------------------------- --------------------------- + Total 0.289ns (0.058ns logic, 0.231ns route) + (20.1% logic, 79.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rx_status_q_0 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 1) + Clock Path Skew: 0.082ns (0.533 - 0.451) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rx_status_q_0 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + SLICE_X148Y125.AQ Tcko 0.115 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rx_status_q<2> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rx_status_q_0 + SLICE_X151Y124.B4 net (fanout=1) 0.185 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rx_status_q<0> + SLICE_X151Y124.B Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3STATUS<0> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RX_STATUS11 + PCIE_X0Y1.PIPERX3STATUS0 net (fanout=1) 0.234 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3STATUS<0> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.463 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ----------------------------------------------------- --------------------------- + Total 0.105ns (-0.314ns logic, 0.419ns route) + (-299.0% logic, 399.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMD + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMA + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMB + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr8_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.065ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr8_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.DQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X152Y123.D2 net (fanout=18) 0.246 ftop/pciw_fP2I/tail<1> + SLICE_X152Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<47> + ftop/pciw_fP2I/Mram_arr8_RAMC + ------------------------------------------------- --------------------------- + Total 0.065ns (-0.181ns logic, 0.246ns route) + (-278.5% logic, 378.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.030ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_129 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 (FF) + Requirement: 0.000ns + Data Path Delay: 0.298ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.228 - 1.149) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_129 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X152Y163.BQ Tcko 0.115 ftop/pciw_i2pS<131> + ftop/pciw_i2pS_129 + SLICE_X150Y166.B3 net (fanout=3) 0.240 ftop/pciw_i2pS<129> + SLICE_X150Y166.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<67> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN621 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_65 + ------------------------------------------------- --------------------------- + Total 0.298ns (0.058ns logic, 0.240ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.030ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_0 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.314ns (Levels of Logic = 1) + Clock Path Skew: 0.095ns (1.216 - 1.121) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_0 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X131Y166.AQ Tcko 0.098 ftop/pciw_i2pS<3> + ftop/pciw_i2pS_0 + SLICE_X139Y165.A6 net (fanout=1) 0.271 ftop/pciw_i2pS<0> + SLICE_X139Y165.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<3> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN110 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_0 + ------------------------------------------------- --------------------------- + Total 0.314ns (0.043ns logic, 0.271ns route) + (13.7% logic, 86.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.035ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_0 (FF) + Destination: ftop/pciw_fP2I/Mram_arr6_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.072ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.490 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_0 to ftop/pciw_fP2I/Mram_arr6_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.CQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_0 + SLICE_X148Y123.D1 net (fanout=18) 0.253 ftop/pciw_fP2I/tail<0> + SLICE_X148Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<35> + ftop/pciw_fP2I/Mram_arr6_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.072ns (-0.181ns logic, 0.253ns route) + (-251.4% logic, 351.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.035ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_0 (FF) + Destination: ftop/pciw_fP2I/Mram_arr6_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.072ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.490 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_0 to ftop/pciw_fP2I/Mram_arr6_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.CQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_0 + SLICE_X148Y123.D1 net (fanout=18) 0.253 ftop/pciw_fP2I/tail<0> + SLICE_X148Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<35> + ftop/pciw_fP2I/Mram_arr6_RAMA + ------------------------------------------------- --------------------------- + Total 0.072ns (-0.181ns logic, 0.253ns route) + (-251.4% logic, 351.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.035ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_0 (FF) + Destination: ftop/pciw_fP2I/Mram_arr6_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.072ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.490 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_0 to ftop/pciw_fP2I/Mram_arr6_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y123.CQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_0 + SLICE_X148Y123.D1 net (fanout=18) 0.253 ftop/pciw_fP2I/tail<0> + SLICE_X148Y123.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<35> + ftop/pciw_fP2I/Mram_arr6_RAMB + ------------------------------------------------- --------------------------- + Total 0.072ns (-0.181ns logic, 0.253ns route) + (-251.4% logic, 351.4% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tpciper_PIPECLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Location pin: PCIE_X0Y1.PIPECLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X6Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Location pin: RAMB36_X6Y26.CLKBWRCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X7Y27.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2442 paths analyzed, 535 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.796ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 5.860ns (Levels of Logic = 3) + Clock Path Skew: 0.099ns (0.993 - 0.894) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y46.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D4 net (fanout=13) 2.870 ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/_n0454_inv211 + SLICE_X128Y22.A4 net (fanout=9) 0.990 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X128Y22.A Tilo 0.068 ftop/gbe0/gmac/N0 + ftop/gbe0/gmac/_n0454_inv2 + SLICE_X128Y23.B2 net (fanout=2) 0.609 ftop/gbe0/gmac/_n0454_inv2 + SLICE_X128Y23.B Tilo 0.068 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxActive_EN1 + SLICE_X130Y19.CE net (fanout=1) 0.566 ftop/gbe0/gmac/rxRS_rxActive_EN + SLICE_X130Y19.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 5.860ns (0.825ns logic, 5.035ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.414ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 8.000ns + Data Path Delay: 5.651ns (Levels of Logic = 3) + Clock Path Skew: 0.100ns (0.994 - 0.894) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y46.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D4 net (fanout=13) 2.870 ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/_n0454_inv211 + SLICE_X128Y22.A4 net (fanout=9) 0.990 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X128Y22.A Tilo 0.068 ftop/gbe0/gmac/N0 + ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D2 net (fanout=2) 0.725 ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D Tilo 0.068 ftop/gbe0/gmac/_n0454_inv + ftop/gbe0/gmac/_n0454_inv1 + SLICE_X128Y24.CE net (fanout=1) 0.241 ftop/gbe0/gmac/_n0454_inv + SLICE_X128Y24.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 5.651ns (0.825ns logic, 4.826ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.414ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Requirement: 8.000ns + Data Path Delay: 5.651ns (Levels of Logic = 3) + Clock Path Skew: 0.100ns (0.994 - 0.894) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y46.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D4 net (fanout=13) 2.870 ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/_n0454_inv211 + SLICE_X128Y22.A4 net (fanout=9) 0.990 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X128Y22.A Tilo 0.068 ftop/gbe0/gmac/N0 + ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D2 net (fanout=2) 0.725 ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D Tilo 0.068 ftop/gbe0/gmac/_n0454_inv + ftop/gbe0/gmac/_n0454_inv1 + SLICE_X128Y24.CE net (fanout=1) 0.241 ftop/gbe0/gmac/_n0454_inv + SLICE_X128Y24.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 5.651ns (0.825ns logic, 4.826ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.414ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_3 (FF) + Requirement: 8.000ns + Data Path Delay: 5.651ns (Levels of Logic = 3) + Clock Path Skew: 0.100ns (0.994 - 0.894) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y46.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D4 net (fanout=13) 2.870 ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/_n0454_inv211 + SLICE_X128Y22.A4 net (fanout=9) 0.990 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X128Y22.A Tilo 0.068 ftop/gbe0/gmac/N0 + ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D2 net (fanout=2) 0.725 ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D Tilo 0.068 ftop/gbe0/gmac/_n0454_inv + ftop/gbe0/gmac/_n0454_inv1 + SLICE_X128Y24.CE net (fanout=1) 0.241 ftop/gbe0/gmac/_n0454_inv + SLICE_X128Y24.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + ------------------------------------------------- --------------------------- + Total 5.651ns (0.825ns logic, 4.826ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.414ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.651ns (Levels of Logic = 3) + Clock Path Skew: 0.100ns (0.994 - 0.894) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y46.BQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D4 net (fanout=13) 2.870 ftop/gbe0/gmac/rxRS_rxER + SLICE_X136Y16.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/_n0454_inv211 + SLICE_X128Y22.A4 net (fanout=9) 0.990 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X128Y22.A Tilo 0.068 ftop/gbe0/gmac/N0 + ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D2 net (fanout=2) 0.725 ftop/gbe0/gmac/_n0454_inv2 + SLICE_X129Y23.D Tilo 0.068 ftop/gbe0/gmac/_n0454_inv + ftop/gbe0/gmac/_n0454_inv1 + SLICE_X128Y24.CE net (fanout=1) 0.241 ftop/gbe0/gmac/_n0454_inv + SLICE_X128Y24.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + ------------------------------------------------- --------------------------- + Total 5.651ns (0.825ns logic, 4.826ns route) + (14.6% logic, 85.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.753ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 5.202ns (Levels of Logic = 4) + Clock Path Skew: -0.010ns (0.825 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y6.CE net (fanout=9) 1.278 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y6.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 5.202ns (0.937ns logic, 4.265ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.753ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_14 (FF) + Requirement: 8.000ns + Data Path Delay: 5.202ns (Levels of Logic = 4) + Clock Path Skew: -0.010ns (0.825 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y6.CE net (fanout=9) 1.278 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y6.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_14 + ------------------------------------------------- --------------------------- + Total 5.202ns (0.937ns logic, 4.265ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.753ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 5.202ns (Levels of Logic = 4) + Clock Path Skew: -0.010ns (0.825 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y6.CE net (fanout=9) 1.278 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y6.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 5.202ns (0.937ns logic, 4.265ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.753ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_15 (FF) + Requirement: 8.000ns + Data Path Delay: 5.202ns (Levels of Logic = 4) + Clock Path Skew: -0.010ns (0.825 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y6.CE net (fanout=9) 1.278 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y6.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<15> + ftop/gbe0/gmac/rxRS_crc/rRemainder_15 + ------------------------------------------------- --------------------------- + Total 5.202ns (0.937ns logic, 4.265ns route) + (18.0% logic, 82.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.791ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_5 (FF) + Requirement: 8.000ns + Data Path Delay: 5.168ns (Levels of Logic = 4) + Clock Path Skew: -0.006ns (0.829 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X151Y5.CE net (fanout=9) 1.210 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X151Y5.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + ------------------------------------------------- --------------------------- + Total 5.168ns (0.971ns logic, 4.197ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.791ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.168ns (Levels of Logic = 4) + Clock Path Skew: -0.006ns (0.829 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X151Y5.CE net (fanout=9) 1.210 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X151Y5.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.168ns (0.971ns logic, 4.197ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.791ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_6 (FF) + Requirement: 8.000ns + Data Path Delay: 5.168ns (Levels of Logic = 4) + Clock Path Skew: -0.006ns (0.829 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X151Y5.CE net (fanout=9) 1.210 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X151Y5.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + ------------------------------------------------- --------------------------- + Total 5.168ns (0.971ns logic, 4.197ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.791ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 5.168ns (Levels of Logic = 4) + Clock Path Skew: -0.006ns (0.829 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X151Y5.CE net (fanout=9) 1.210 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X151Y5.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 5.168ns (0.971ns logic, 4.197ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.819ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_3 (FF) + Requirement: 8.000ns + Data Path Delay: 5.139ns (Levels of Logic = 4) + Clock Path Skew: -0.007ns (0.828 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X150Y7.CE net (fanout=9) 1.181 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X150Y7.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_3 + ------------------------------------------------- --------------------------- + Total 5.139ns (0.971ns logic, 4.168ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.819ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 5.139ns (Levels of Logic = 4) + Clock Path Skew: -0.007ns (0.828 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X150Y7.CE net (fanout=9) 1.181 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X150Y7.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 5.139ns (0.971ns logic, 4.168ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.819ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.139ns (Levels of Logic = 4) + Clock Path Skew: -0.007ns (0.828 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X150Y7.CE net (fanout=9) 1.181 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X150Y7.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 5.139ns (0.971ns logic, 4.168ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.819ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_0 (FF) + Requirement: 8.000ns + Data Path Delay: 5.139ns (Levels of Logic = 4) + Clock Path Skew: -0.007ns (0.828 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X150Y7.CE net (fanout=9) 1.181 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X150Y7.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_0 + ------------------------------------------------- --------------------------- + Total 5.139ns (0.971ns logic, 4.168ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.981ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_8 (FF) + Requirement: 8.000ns + Data Path Delay: 4.973ns (Levels of Logic = 4) + Clock Path Skew: -0.011ns (0.824 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y8.CE net (fanout=9) 1.049 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y8.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_8 + ------------------------------------------------- --------------------------- + Total 4.973ns (0.937ns logic, 4.036ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.981ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 4.973ns (Levels of Logic = 4) + Clock Path Skew: -0.011ns (0.824 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y8.CE net (fanout=9) 1.049 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y8.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 4.973ns (0.937ns logic, 4.036ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.981ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_9 (FF) + Requirement: 8.000ns + Data Path Delay: 4.973ns (Levels of Logic = 4) + Clock Path Skew: -0.011ns (0.824 - 0.835) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X138Y15.B5 net (fanout=18) 1.244 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X138Y15.B Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X138Y15.A6 net (fanout=1) 0.124 ftop/gbe0/gmac/N2 + SLICE_X138Y15.A Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A5 net (fanout=13) 0.788 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X144Y7.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X137Y16.A5 net (fanout=33) 0.831 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X137Y16.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X148Y8.CE net (fanout=9) 1.049 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X148Y8.CLK Tceck 0.284 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_9 + ------------------------------------------------- --------------------------- + Total 4.973ns (0.937ns logic, 4.036ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_38 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_46 (FF) + Requirement: 0.000ns + Data Path Delay: 0.082ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_38 to ftop/gbe0/gmac/rxRS_rxPipe_46 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y14.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe_38 + SLICE_X143Y14.C5 net (fanout=2) 0.066 ftop/gbe0/gmac/rxRS_rxPipe<38> + SLICE_X143Y14.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe<38>_rt + ftop/gbe0/gmac/rxRS_rxPipe_46 + ------------------------------------------------- --------------------------- + Total 0.082ns (0.016ns logic, 0.066ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_36 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_44 (FF) + Requirement: 0.000ns + Data Path Delay: 0.082ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_36 to ftop/gbe0/gmac/rxRS_rxPipe_44 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y14.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe_36 + SLICE_X143Y14.A5 net (fanout=2) 0.066 ftop/gbe0/gmac/rxRS_rxPipe<36> + SLICE_X143Y14.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe<36>_rt + ftop/gbe0/gmac/rxRS_rxPipe_44 + ------------------------------------------------- --------------------------- + Total 0.082ns (0.016ns logic, 0.066ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.133ns (Levels of Logic = 0) + Clock Path Skew: 0.031ns (0.408 - 0.377) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y13.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X142Y14.D2 net (fanout=5) 0.297 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X142Y14.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + ------------------------------------------------- --------------------------- + Total 0.133ns (-0.164ns logic, 0.297ns route) + (-123.3% logic, 223.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.110ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_39 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_47 (FF) + Requirement: 0.000ns + Data Path Delay: 0.110ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_39 to ftop/gbe0/gmac/rxRS_rxPipe_47 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y14.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe_39 + SLICE_X143Y14.D4 net (fanout=2) 0.095 ftop/gbe0/gmac/rxRS_rxPipe<39> + SLICE_X143Y14.CLK Tah (-Th) 0.083 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe<39>_rt + ftop/gbe0/gmac/rxRS_rxPipe_47 + ------------------------------------------------- --------------------------- + Total 0.110ns (0.015ns logic, 0.095ns route) + (13.6% logic, 86.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_37 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxPipe_45 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_37 to ftop/gbe0/gmac/rxRS_rxPipe_45 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y14.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe_37 + SLICE_X143Y14.B4 net (fanout=2) 0.096 ftop/gbe0/gmac/rxRS_rxPipe<37> + SLICE_X143Y14.CLK Tah (-Th) 0.080 ftop/gbe0/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/rxRS_rxPipe<37>_rt + ftop/gbe0/gmac/rxRS_rxPipe_45 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.018ns logic, 0.096ns route) + (15.8% logic, 84.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.058 - 0.048) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y13.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + SLICE_X146Y13.CX net (fanout=5) 0.117 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<2> + SLICE_X146Y13.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.009ns logic, 0.117ns route) + (7.1% logic, 92.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y24.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + SLICE_X128Y24.C5 net (fanout=3) 0.077 ftop/gbe0/gmac/rxRS_preambleCnt_value<2> + SLICE_X128Y24.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_rxRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.121ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.131ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.058 - 0.048) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y13.AQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_0 + SLICE_X146Y13.AX net (fanout=6) 0.122 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<0> + SLICE_X146Y13.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.131ns (0.009ns logic, 0.122ns route) + (6.9% logic, 93.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.122ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 to ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y13.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + SLICE_X147Y13.C5 net (fanout=5) 0.080 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<2> + SLICE_X147Y13.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/rxRS_rxF/Mxor_sGEnqPtr1[0]_sGEnqPtr1[4]_xor_14_OUT_1_xo<0>1 + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.122ns (0.042ns logic, 0.080ns route) + (34.4% logic, 65.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.123ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_26 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_26 to ftop/gbe0/gmac/rxRS_crc/rRemainder_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y5.CQ Tcko 0.098 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_26 + SLICE_X145Y5.B5 net (fanout=15) 0.082 ftop/gbe0/gmac/rxRS_crc/rRemainder<26> + SLICE_X145Y5.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder$D_IN<25>1 + ftop/gbe0/gmac/rxRS_crc/rRemainder_25 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.041ns logic, 0.082ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_fullD (FF) + Destination: ftop/gbe0/gmac/rxRS_ovfBit/sSyncReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 1) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_fullD to ftop/gbe0/gmac/rxRS_ovfBit/sSyncReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y14.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_fullD + ftop/gbe0/gmac/rxRS_fullD + SLICE_X128Y14.A5 net (fanout=1) 0.112 ftop/gbe0/gmac/rxRS_fullD + SLICE_X128Y14.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/rxRS_ovfBit/sSyncReg + ftop/gbe0/gmac/rxRS_ovfBit_sD_IN1 + ftop/gbe0/gmac/rxRS_ovfBit/sSyncReg + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.125ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 to ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y23.DQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + SLICE_X128Y23.BX net (fanout=1) 0.099 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + SLICE_X128Y23.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg1 + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.026ns logic, 0.099ns route) + (20.8% logic, 79.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.126ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y24.AQ Tcko 0.115 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + SLICE_X128Y24.A5 net (fanout=5) 0.087 ftop/gbe0/gmac/rxRS_preambleCnt_value<0> + SLICE_X128Y24.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_rxRS_preambleCnt_value_xor<0>11_INV_0 + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.039ns logic, 0.087ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 4.668ns (period - min period limit) + Period: 8.000ns + Min period limit: 3.332ns (300.120MHz) (Tbrper_I) + Physical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Logical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Location pin: BUFR_X2Y3.I + Clock network: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1/CLK + Location pin: SLICE_X142Y14.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X142Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X142Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X142Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 6107 paths analyzed, 683 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.797ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.203ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.715ns (Levels of Logic = 5) + Clock Path Skew: -0.047ns (0.973 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.715ns (0.679ns logic, 5.036ns route) + (11.9% logic, 88.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.474ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 5.444ns (Levels of Logic = 4) + Clock Path Skew: -0.047ns (0.973 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y61.D1 net (fanout=15) 1.627 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 5.444ns (0.611ns logic, 4.833ns route) + (11.2% logic, 88.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.510ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.406ns (Levels of Logic = 5) + Clock Path Skew: -0.049ns (0.971 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A4 net (fanout=8) 1.107 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data81 + SLICE_X153Y58.B1 net (fanout=13) 0.737 ftop/gbe0/gmac/txRS_crc_add_data<7> + SLICE_X153Y58.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X153Y58.C2 net (fanout=2) 0.586 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X153Y58.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 5.406ns (0.682ns logic, 4.724ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.684ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.066ns (Levels of Logic = 5) + Clock Path Skew: -0.215ns (1.486 - 1.701) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y39.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X153Y42.B3 net (fanout=13) 0.907 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X153Y42.B Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X147Y50.A6 net (fanout=12) 0.738 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.066ns (0.679ns logic, 4.387ns route) + (13.4% logic, 86.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.713ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.179ns (Levels of Logic = 5) + Clock Path Skew: -0.073ns (0.973 - 1.046) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_2 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y42.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_2 + SLICE_X148Y39.B2 net (fanout=39) 0.751 ftop/gbe0/gmac/txRS_emitFCS<2> + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.179ns (0.679ns logic, 4.500ns route) + (13.1% logic, 86.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.761ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_isSOF (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.129ns (Levels of Logic = 5) + Clock Path Skew: -0.075ns (0.973 - 1.048) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_isSOF to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/txRS_isSOF + SLICE_X146Y50.A2 net (fanout=8) 1.125 ftop/gbe0/gmac/txRS_isSOF + SLICE_X146Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11_SW0 + SLICE_X147Y50.A1 net (fanout=1) 0.583 ftop/gbe0/gmac/N6 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.129ns (0.679ns logic, 4.450ns route) + (13.2% logic, 86.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.793ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 5.123ns (Levels of Logic = 5) + Clock Path Skew: -0.049ns (0.971 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y60.D5 net (fanout=15) 1.114 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y60.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X154Y60.C6 net (fanout=1) 0.121 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X154Y60.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 5.123ns (0.682ns logic, 4.441ns route) + (13.3% logic, 86.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.849ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 4.897ns (Levels of Logic = 5) + Clock Path Skew: -0.219ns (1.486 - 1.705) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y38.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X148Y39.B3 net (fanout=10) 0.469 ftop/gbe0/gmac/txRS_txF_dEMPTY_N + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 4.897ns (0.679ns logic, 4.218ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.859ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 5.057ns (Levels of Logic = 5) + Clock Path Skew: -0.049ns (0.971 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B1 net (fanout=8) 1.153 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data41 + SLICE_X154Y60.D6 net (fanout=14) 0.807 ftop/gbe0/gmac/txRS_crc_add_data<3> + SLICE_X154Y60.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X154Y60.C6 net (fanout=1) 0.121 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X154Y60.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 5.057ns (0.682ns logic, 4.375ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.869ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 4.881ns (Levels of Logic = 5) + Clock Path Skew: -0.215ns (1.486 - 1.701) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y39.BQ Tcko 0.337 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X148Y39.B4 net (fanout=5) 0.453 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 4.881ns (0.679ns logic, 4.202ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.892ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txActive (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.000ns (Levels of Logic = 5) + Clock Path Skew: -0.073ns (0.973 - 1.046) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txActive to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y40.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txActive + ftop/gbe0/gmac/txRS_txActive + SLICE_X146Y50.A4 net (fanout=11) 0.952 ftop/gbe0/gmac/txRS_txActive + SLICE_X146Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11_SW0 + SLICE_X147Y50.A1 net (fanout=1) 0.583 ftop/gbe0/gmac/N6 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X155Y61.C3 net (fanout=15) 1.374 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X155Y61.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X155Y61.B3 net (fanout=1) 0.456 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X155Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 5.000ns (0.723ns logic, 4.277ns route) + (14.5% logic, 85.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.905ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_0 (FF) + Requirement: 8.000ns + Data Path Delay: 5.011ns (Levels of Logic = 4) + Clock Path Skew: -0.049ns (0.971 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A4 net (fanout=8) 1.107 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data81 + SLICE_X153Y58.A1 net (fanout=13) 0.996 ftop/gbe0/gmac/txRS_crc_add_data<7> + SLICE_X153Y58.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<0>11 + ftop/gbe0/gmac/txRS_crc/rRemainder_0 + ------------------------------------------------- --------------------------- + Total 5.011ns (0.614ns logic, 4.397ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.906ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_14 (FF) + Requirement: 8.000ns + Data Path Delay: 5.015ns (Levels of Logic = 5) + Clock Path Skew: -0.044ns (0.976 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B1 net (fanout=8) 1.153 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data41 + SLICE_X154Y56.D2 net (fanout=14) 0.765 ftop/gbe0/gmac/txRS_crc_add_data<3> + SLICE_X154Y56.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>2 + SLICE_X154Y56.C6 net (fanout=1) 0.121 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>2 + SLICE_X154Y56.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<14>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_14 + ------------------------------------------------- --------------------------- + Total 5.015ns (0.682ns logic, 4.333ns route) + (13.6% logic, 86.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.922ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Requirement: 8.000ns + Data Path Delay: 5.129ns (Levels of Logic = 1) + Clock Path Skew: 0.086ns (1.097 - 1.011) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 to ftop/gbe0/gmac/txRS_iobTxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X133Y50.AMUX Tshcko 0.422 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + SLICE_X116Y50.A4 net (fanout=4) 0.810 ftop/gbe0/gmac/txRS_txRst_OUT_RST + SLICE_X116Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + ftop/gbe0/gmac/txRS_iobTxClk_reset/RESET_OUT1_INV_0 + OLOGIC_X2Y71.SR net (fanout=11) 3.136 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + OLOGIC_X2Y71.CLK Tosrck 0.693 gmii_txd_7_OBUF + ftop/gbe0/gmac/txRS_iobTxData_7 + ------------------------------------------------- --------------------------- + Total 5.129ns (1.183ns logic, 3.946ns route) + (23.1% logic, 76.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.927ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 4.991ns (Levels of Logic = 4) + Clock Path Skew: -0.047ns (0.973 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B1 net (fanout=8) 1.153 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X149Y57.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data41 + SLICE_X154Y61.D2 net (fanout=14) 0.933 ftop/gbe0/gmac/txRS_crc_add_data<3> + SLICE_X154Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 4.991ns (0.611ns logic, 4.380ns route) + (12.2% logic, 87.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.933ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_txData_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.974ns (Levels of Logic = 5) + Clock Path Skew: -0.058ns (0.962 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_txData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X142Y49.D3 net (fanout=13) 1.320 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X142Y49.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF2 + SLICE_X142Y49.C2 net (fanout=2) 0.481 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF + SLICE_X142Y49.C Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF + ftop/gbe0/gmac/Mmux_txRS_txData_D_IN121 + SLICE_X143Y50.A3 net (fanout=1) 0.462 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN121 + SLICE_X143Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_txData<7> + ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X143Y55.C1 net (fanout=4) 0.742 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN12 + SLICE_X143Y55.CLK Tas 0.073 ftop/gbe0/gmac/txRS_txData<3> + ftop/gbe0/gmac/Mmux_txRS_txData_D_IN33 + ftop/gbe0/gmac/txRS_txData_2 + ------------------------------------------------- --------------------------- + Total 4.974ns (0.682ns logic, 4.292ns route) + (13.7% logic, 86.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.951ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Requirement: 8.000ns + Data Path Delay: 4.971ns (Levels of Logic = 5) + Clock Path Skew: -0.043ns (0.977 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y55.B1 net (fanout=15) 0.958 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y55.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>1 + SLICE_X154Y55.A6 net (fanout=1) 0.125 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>1 + SLICE_X154Y55.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<5>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_5 + ------------------------------------------------- --------------------------- + Total 4.971ns (0.682ns logic, 4.289ns route) + (13.7% logic, 86.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.955ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 4.795ns (Levels of Logic = 4) + Clock Path Skew: -0.215ns (1.486 - 1.701) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y39.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X153Y42.B3 net (fanout=13) 0.907 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X153Y42.B Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X147Y50.A6 net (fanout=12) 0.738 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y61.D1 net (fanout=15) 1.627 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 4.795ns (0.611ns logic, 4.184ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.982ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.934ns (Levels of Logic = 5) + Clock Path Skew: -0.049ns (0.971 - 1.020) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y42.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X148Y39.B1 net (fanout=38) 1.287 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A4 net (fanout=8) 1.107 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X150Y56.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data81 + SLICE_X153Y58.B1 net (fanout=13) 0.737 ftop/gbe0/gmac/txRS_crc_add_data<7> + SLICE_X153Y58.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X153Y58.D6 net (fanout=2) 0.117 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X153Y58.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<2>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 4.934ns (0.679ns logic, 4.255ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.984ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 4.908ns (Levels of Logic = 4) + Clock Path Skew: -0.073ns (0.973 - 1.046) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_2 to ftop/gbe0/gmac/txRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y42.DQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_2 + SLICE_X148Y39.B2 net (fanout=39) 0.751 ftop/gbe0/gmac/txRS_emitFCS<2> + SLICE_X148Y39.B Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X147Y50.A5 net (fanout=13) 1.007 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X147Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<6> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A3 net (fanout=8) 0.912 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X142Y55.A Tilo 0.068 ftop/ctop/inf/dp0/bml_mesgSize<15> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y61.D1 net (fanout=15) 1.627 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y61.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 4.908ns (0.611ns logic, 4.297ns route) + (12.4% logic, 87.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.078ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_0 to ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X133Y50.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + ftop/gbe0/gmac/txRS_txRst/reset_hold_0 + SLICE_X133Y50.A5 net (fanout=1) 0.062 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + SLICE_X133Y50.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + ftop/gbe0/gmac/txRS_txRst/reset_hold<0>_rt + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.078ns (0.016ns logic, 0.062ns route) + (20.5% logic, 79.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.085ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.491 - 0.453) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y34.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + SLICE_X157Y34.AX net (fanout=2) 0.101 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + SLICE_X157Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.022ns logic, 0.101ns route) + (17.9% logic, 82.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.097ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_lenCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_doPad (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 1) + Clock Path Skew: 0.037ns (0.491 - 0.454) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_lenCnt_value_2 to ftop/gbe0/gmac/txRS_doPad + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y38.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_lenCnt_value<3> + ftop/gbe0/gmac/txRS_lenCnt_value_2 + SLICE_X153Y38.B6 net (fanout=3) 0.093 ftop/gbe0/gmac/txRS_lenCnt_value<2> + SLICE_X153Y38.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_doPad + ftop/gbe0/gmac/txRS_lenCnt_value_45_ULT_59___d2091 + ftop/gbe0/gmac/txRS_doPad + ------------------------------------------------- --------------------------- + Total 0.134ns (0.041ns logic, 0.093ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.103ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/phyRst/rstSync/reset_hold_0 (FF) + Destination: ftop/gbe0/phyRst/rstSync/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/phyRst/rstSync/reset_hold_0 to ftop/gbe0/phyRst/rstSync/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y43.AQ Tcko 0.098 ftop/gbe0/phyRst/rstSync/reset_hold<0> + ftop/gbe0/phyRst/rstSync/reset_hold_0 + SLICE_X89Y42.AX net (fanout=1) 0.093 ftop/gbe0/phyRst/rstSync/reset_hold<0> + SLICE_X89Y42.CLK Tckdi (-Th) 0.076 gmii_rstn_OBUF + ftop/gbe0/phyRst/rstSync/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.022ns logic, 0.093ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.105ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_2 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y33.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_2 + SLICE_X156Y34.CX net (fanout=1) 0.095 ftop/gbe0/gmac/txRS_txF/dSyncReg1<2> + SLICE_X156Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_2 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.022ns logic, 0.095ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.105ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y33.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_0 + SLICE_X156Y34.AX net (fanout=1) 0.095 ftop/gbe0/gmac/txRS_txF/dSyncReg1<0> + SLICE_X156Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.022ns logic, 0.095ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.106ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y33.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_3 + SLICE_X156Y34.DX net (fanout=1) 0.096 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + SLICE_X156Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.107ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X156Y33.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_1 + SLICE_X156Y34.BX net (fanout=1) 0.097 ftop/gbe0/gmac/txRS_txF/dSyncReg1<1> + SLICE_X156Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.107ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.119ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y34.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X154Y34.DX net (fanout=2) 0.097 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X154Y34.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.119ns (0.022ns logic, 0.097ns route) + (18.5% logic, 81.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.109ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y34.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X155Y34.A5 net (fanout=2) 0.066 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X155Y34.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.043ns logic, 0.066ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_23 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_31 (FF) + Requirement: 0.000ns + Data Path Delay: 0.146ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.480 - 0.445) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_23 to ftop/gbe0/gmac/txRS_crc/rRemainder_31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y56.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + ftop/gbe0/gmac/txRS_crc/rRemainder_23 + SLICE_X148Y55.B5 net (fanout=2) 0.125 ftop/gbe0/gmac/txRS_crc/rRemainder<23> + SLICE_X148Y55.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<31>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_31 + ------------------------------------------------- --------------------------- + Total 0.146ns (0.021ns logic, 0.125ns route) + (14.4% logic, 85.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.117ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y35.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + SLICE_X155Y35.C5 net (fanout=5) 0.075 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<2> + SLICE_X155Y35.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_1_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.042ns logic, 0.075ns route) + (35.9% logic, 64.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.117ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.117ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y44.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + SLICE_X153Y44.C5 net (fanout=5) 0.075 ftop/gbe0/gmac/txRS_preambleCnt_value<2> + SLICE_X153Y44.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.117ns (0.042ns logic, 0.075ns route) + (35.9% logic, 64.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.127ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_emitFCS_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y42.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X149Y42.C5 net (fanout=44) 0.085 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X149Y42.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN22 + ftop/gbe0/gmac/txRS_emitFCS_1 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.042ns logic, 0.085ns route) + (33.1% logic, 66.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.128ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.128ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y35.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X155Y35.A5 net (fanout=6) 0.085 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X155Y35.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_INV_4072_o1_INV_0 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + ------------------------------------------------- --------------------------- + Total 0.128ns (0.043ns logic, 0.085ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.128ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.128ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_emitFCS_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y42.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X149Y42.B5 net (fanout=44) 0.087 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X149Y42.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN11 + ftop/gbe0/gmac/txRS_emitFCS_0 + ------------------------------------------------- --------------------------- + Total 0.128ns (0.041ns logic, 0.087ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.129ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y42.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + SLICE_X154Y42.C5 net (fanout=4) 0.087 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + SLICE_X154Y42.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.042ns logic, 0.087ns route) + (32.6% logic, 67.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.132ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.132ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y35.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X155Y35.D5 net (fanout=6) 0.091 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X155Y35.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_2_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.132ns (0.041ns logic, 0.091ns route) + (31.1% logic, 68.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X155Y34.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + SLICE_X155Y34.B4 net (fanout=2) 0.096 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + SLICE_X155Y34.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y42.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + SLICE_X154Y42.D5 net (fanout=6) 0.096 ftop/gbe0/gmac/txRS_ifgCnt_value<0> + SLICE_X154Y42.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>12 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 6.571ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys1_clk/I0 + Logical resource: ftop/sys1_clk/I0 + Location pin: BUFGCTRL_X0Y24.I0 + Clock network: ftop/sys1_clki_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_en_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxEna/CK + Location pin: OLOGIC_X2Y63.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_er_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxErr/CK + Location pin: OLOGIC_X2Y62.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_0_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData/CK + Location pin: OLOGIC_X2Y64.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_1_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_1/CK + Location pin: OLOGIC_X2Y65.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_2_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_2/CK + Location pin: OLOGIC_X2Y66.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_3_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_3/CK + Location pin: OLOGIC_X2Y67.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_4_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_4/CK + Location pin: OLOGIC_X2Y68.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_5_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_5/CK + Location pin: OLOGIC_X2Y69.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_6_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_6/CK + Location pin: OLOGIC_X2Y70.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_7_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_7/CK + Location pin: OLOGIC_X2Y71.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_gtx_clk_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxClk/CK + Location pin: OLOGIC_X2Y46.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: gmii_rstn_OBUF/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_1/SR + Location pin: SLICE_X89Y42.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/phyRst/rstSync/reset_hold<0>/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_0/SR + Location pin: SLICE_X89Y43.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_1/SR + Location pin: SLICE_X133Y50.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_0/SR + Location pin: SLICE_X133Y50.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Location pin: SLICE_X134Y42.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2/SR + Location pin: SLICE_X135Y42.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Location pin: SLICE_X140Y43.SR + Clock network: ftop/gbe0/gmac/txRS_unfBit/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF_dEMPTY_N/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg/SR + Location pin: SLICE_X149Y38.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD +TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 75758 paths analyzed, 22658 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.987ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.013ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.611ns (Levels of Logic = 2) + Clock Path Skew: -0.318ns (1.550 - 1.868) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y211.CQ Tcko 0.337 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/wr_calib_dly_r1_0_4 + SLICE_X89Y166.A5 net (fanout=80) 3.277 ftop/dram0/memc_memc_dbg_wr_calib_clk_delay<4> + SLICE_X89Y166.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o12 + SLICE_X88Y166.A5 net (fanout=1) 0.190 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o11 + SLICE_X88Y166.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[5]_wrdata_en_r3_Mux_24_o14 + SLICE_X89Y158.BX net (fanout=1) 0.637 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[5]_wrdata_en_r3_Mux_24_o + SLICE_X89Y158.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_2 + ------------------------------------------------- --------------------------- + Total 4.611ns (0.507ns logic, 4.104ns route) + (11.0% logic, 89.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.014ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.814ns (Levels of Logic = 2) + Clock Path Skew: -0.114ns (1.547 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X84Y199.B2 net (fanout=144) 2.819 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X84Y199.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMB_D1 + SLICE_X85Y169.A6 net (fanout=1) 1.517 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<249> + SLICE_X85Y169.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1531 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.814ns (0.478ns logic, 4.336ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.015ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.577ns (Levels of Logic = 3) + Clock Path Skew: -0.350ns (1.522 - 1.872) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y203.BQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X75Y203.A6 net (fanout=302) 0.131 ftop/dram0/memc_memc/rst + SLICE_X75Y203.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33].u_iob_dq/ocb_d2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X74Y164.C6 net (fanout=10) 1.554 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X74Y164.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X85Y147.D6 net (fanout=8) 1.220 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X85Y147.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y138.AX net (fanout=8) 1.097 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y138.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.577ns (0.575ns logic, 4.002ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.016ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.811ns (Levels of Logic = 2) + Clock Path Skew: -0.115ns (1.546 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X84Y199.C2 net (fanout=144) 2.815 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X84Y199.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMC_D1 + SLICE_X83Y171.A6 net (fanout=1) 1.518 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + SLICE_X83Y171.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1511 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.811ns (0.478ns logic, 4.333ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.018ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_7 (FF) + Requirement: 5.000ns + Data Path Delay: 4.787ns (Levels of Logic = 1) + Clock Path Skew: -0.137ns (1.545 - 1.682) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X49Y224.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<77> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 + SLICE_X89Y188.C1 net (fanout=63) 4.377 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<75> + SLICE_X89Y188.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_8 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mmux_dlyval_dq_reg_r[39]_cal1_dq_tap_cnt_r[4]_mux_212_OUT<4>21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_7 + ------------------------------------------------- --------------------------- + Total 4.787ns (0.410ns logic, 4.377ns route) + (8.6% logic, 91.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_fall0_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.805ns (Levels of Logic = 2) + Clock Path Skew: -0.117ns (1.544 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_fall0_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X84Y201.B3 net (fanout=144) 2.813 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X84Y201.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<115> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMB_D1 + SLICE_X80Y173.A6 net (fanout=1) 1.514 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<117> + SLICE_X80Y173.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/ocb_d1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall0491 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_fall0_r1 + ------------------------------------------------- --------------------------- + Total 4.805ns (0.478ns logic, 4.327ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_6 (FF) + Requirement: 5.000ns + Data Path Delay: 4.781ns (Levels of Logic = 1) + Clock Path Skew: -0.137ns (1.545 - 1.682) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X49Y224.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<77> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal1_cnt_cpt_r_0 + SLICE_X89Y188.B1 net (fanout=63) 4.374 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<75> + SLICE_X89Y188.CLK Tas 0.070 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_8 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mmux_dlyval_dq_reg_r[39]_cal1_dq_tap_cnt_r[4]_mux_213_OUT<4>21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dlyval_dq_reg_r_6 + ------------------------------------------------- --------------------------- + Total 4.781ns (0.407ns logic, 4.374ns route) + (8.5% logic, 91.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_rise1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.797ns (Levels of Logic = 2) + Clock Path Skew: -0.117ns (1.544 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_rise1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X84Y200.C2 net (fanout=144) 2.686 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X84Y200.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<181> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMC_D1 + SLICE_X77Y173.A6 net (fanout=1) 1.633 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<181> + SLICE_X77Y173.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise1491 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53].u_iob_dq/wr_data_rise1_r1 + ------------------------------------------------- --------------------------- + Total 4.797ns (0.478ns logic, 4.319ns route) + (10.0% logic, 90.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.030ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_rise1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.793ns (Levels of Logic = 2) + Clock Path Skew: -0.119ns (1.542 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_rise1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 + SLICE_X84Y200.A1 net (fanout=144) 2.718 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<0> + SLICE_X84Y200.AMUX Tilo 0.196 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<181> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMA + SLICE_X83Y175.A6 net (fanout=1) 1.469 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<184> + SLICE_X83Y175.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise1521 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_rise1_r1 + ------------------------------------------------- --------------------------- + Total 4.793ns (0.606ns logic, 4.187ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.034ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.791ns (Levels of Logic = 2) + Clock Path Skew: -0.117ns (1.544 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X84Y199.A3 net (fanout=144) 2.950 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X84Y199.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMA_D1 + SLICE_X85Y172.A6 net (fanout=1) 1.363 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<251> + SLICE_X85Y172.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1551 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.791ns (0.478ns logic, 4.313ns route) + (10.0% logic, 90.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.037ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.555ns (Levels of Logic = 3) + Clock Path Skew: -0.350ns (1.522 - 1.872) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X74Y203.BQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X75Y203.A6 net (fanout=302) 0.131 ftop/dram0/memc_memc/rst + SLICE_X75Y203.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33].u_iob_dq/ocb_d2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X74Y164.C6 net (fanout=10) 1.554 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X74Y164.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X85Y147.D6 net (fanout=8) 1.220 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + SLICE_X85Y147.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y138.AX net (fanout=8) 1.097 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X65Y138.CLK Tdick 0.012 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.555ns (0.553ns logic, 4.002ns route) + (12.1% logic, 87.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.040ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.788ns (Levels of Logic = 3) + Clock Path Skew: -0.114ns (1.547 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.BQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_1 + SLICE_X96Y198.B2 net (fanout=144) 2.099 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<1> + SLICE_X96Y198.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<55> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMB_D1 + SLICE_X84Y169.B6 net (fanout=1) 1.915 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<57> + SLICE_X84Y169.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0531 + SLICE_X84Y169.D6 net (fanout=1) 0.129 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<57> + SLICE_X84Y169.CLK Tas 0.172 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.788ns (0.645ns logic, 4.143ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.042ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall0_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.774ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (1.535 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall0_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_0 + SLICE_X84Y205.A1 net (fanout=144) 2.740 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<0> + SLICE_X84Y205.AMUX Tilo 0.196 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<109> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMA + SLICE_X76Y180.A6 net (fanout=1) 1.428 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<112> + SLICE_X76Y180.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49].u_iob_dq/ocb_d3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall0431 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[48].u_iob_dq/wr_data_fall0_r1 + ------------------------------------------------- --------------------------- + Total 4.774ns (0.606ns logic, 4.168ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.043ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.779ns (Levels of Logic = 3) + Clock Path Skew: -0.120ns (1.541 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_3 + SLICE_X84Y210.B4 net (fanout=144) 2.405 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + SLICE_X84Y210.BMUX Tilo 0.201 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<43> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMB + SLICE_X73Y185.B6 net (fanout=1) 1.437 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<44> + SLICE_X73Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0391 + SLICE_X73Y185.D6 net (fanout=1) 0.117 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<44> + SLICE_X73Y185.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.779ns (0.820ns logic, 3.959ns route) + (17.2% logic, 82.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.047ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg (FF) + Destination: ftop/dram0/uclkUpdateCnt_21 (FF) + Requirement: 5.000ns + Data Path Delay: 4.627ns (Levels of Logic = 3) + Clock Path Skew: -0.268ns (1.462 - 1.730) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg to ftop/dram0/uclkUpdateCnt_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y208.DQ Tcko 0.337 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C4 net (fanout=3) 0.909 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C Tilo 0.068 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sRDY1 + SLICE_X57Y194.B5 net (fanout=1) 1.012 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt_sRDY + SLICE_X57Y194.B Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A4 net (fanout=1) 0.399 ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN4 + SLICE_X41Y198.CE net (fanout=100) 1.448 ftop/dram0/dbg_cpt_first_edge_cnt_sEN + SLICE_X41Y198.CLK Tceck 0.318 ftop/dram0/uclkUpdateCnt<23> + ftop/dram0/uclkUpdateCnt_21 + ------------------------------------------------- --------------------------- + Total 4.627ns (0.859ns logic, 3.768ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.047ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg (FF) + Destination: ftop/dram0/uclkUpdateCnt_20 (FF) + Requirement: 5.000ns + Data Path Delay: 4.627ns (Levels of Logic = 3) + Clock Path Skew: -0.268ns (1.462 - 1.730) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg to ftop/dram0/uclkUpdateCnt_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y208.DQ Tcko 0.337 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C4 net (fanout=3) 0.909 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C Tilo 0.068 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sRDY1 + SLICE_X57Y194.B5 net (fanout=1) 1.012 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt_sRDY + SLICE_X57Y194.B Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A4 net (fanout=1) 0.399 ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN4 + SLICE_X41Y198.CE net (fanout=100) 1.448 ftop/dram0/dbg_cpt_first_edge_cnt_sEN + SLICE_X41Y198.CLK Tceck 0.318 ftop/dram0/uclkUpdateCnt<23> + ftop/dram0/uclkUpdateCnt_20 + ------------------------------------------------- --------------------------- + Total 4.627ns (0.859ns logic, 3.768ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.047ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg (FF) + Destination: ftop/dram0/uclkUpdateCnt_22 (FF) + Requirement: 5.000ns + Data Path Delay: 4.627ns (Levels of Logic = 3) + Clock Path Skew: -0.268ns (1.462 - 1.730) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg to ftop/dram0/uclkUpdateCnt_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y208.DQ Tcko 0.337 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C4 net (fanout=3) 0.909 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C Tilo 0.068 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sRDY1 + SLICE_X57Y194.B5 net (fanout=1) 1.012 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt_sRDY + SLICE_X57Y194.B Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A4 net (fanout=1) 0.399 ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN4 + SLICE_X41Y198.CE net (fanout=100) 1.448 ftop/dram0/dbg_cpt_first_edge_cnt_sEN + SLICE_X41Y198.CLK Tceck 0.318 ftop/dram0/uclkUpdateCnt<23> + ftop/dram0/uclkUpdateCnt_22 + ------------------------------------------------- --------------------------- + Total 4.627ns (0.859ns logic, 3.768ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.047ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg (FF) + Destination: ftop/dram0/uclkUpdateCnt_23 (FF) + Requirement: 5.000ns + Data Path Delay: 4.627ns (Levels of Logic = 3) + Clock Path Skew: -0.268ns (1.462 - 1.730) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg to ftop/dram0/uclkUpdateCnt_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y208.DQ Tcko 0.337 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C4 net (fanout=3) 0.909 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + SLICE_X63Y208.C Tilo 0.068 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sToggleReg + ftop/dram0/dbg_wl_odelay_dqs_tap_cnt/sync/sRDY1 + SLICE_X57Y194.B5 net (fanout=1) 1.012 ftop/dram0/dbg_wl_odelay_dqs_tap_cnt_sRDY + SLICE_X57Y194.B Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A4 net (fanout=1) 0.399 ftop/dram0/dbg_cpt_first_edge_cnt_sEN3 + SLICE_X57Y194.A Tilo 0.068 ftop/dram0/dbg_wr_calib_clk_delay/sDataSyncIn<11> + ftop/dram0/dbg_cpt_first_edge_cnt_sEN4 + SLICE_X41Y198.CE net (fanout=100) 1.448 ftop/dram0/dbg_cpt_first_edge_cnt_sEN + SLICE_X41Y198.CLK Tceck 0.318 ftop/dram0/uclkUpdateCnt<23> + ftop/dram0/uclkUpdateCnt_23 + ------------------------------------------------- --------------------------- + Total 4.627ns (0.859ns logic, 3.768ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_r_0_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.580ns (Levels of Logic = 2) + Clock Path Skew: -0.313ns (1.550 - 1.863) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_r_0_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y215.BQ Tcko 0.337 ftop/dram0/memc_memc_dbg_wl_dqs_inverted<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_r_0_1 + SLICE_X90Y160.A4 net (fanout=81) 3.193 ftop/dram0/memc_memc_dbg_wl_dqs_inverted<1> + SLICE_X90Y160.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[3]_wrdata_en_r3_Mux_15_o12 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[3]_wrdata_en_r3_Mux_15_o13 + SLICE_X88Y159.A4 net (fanout=1) 0.412 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[3]_wrdata_en_r3_Mux_15_o12 + SLICE_X88Y159.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dq_oe_n<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_calib_dly[3]_wrdata_en_r3_Mux_15_o14 + SLICE_X88Y155.BX net (fanout=1) 0.487 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/wr_calib_dly[3]_wrdata_en_r3_Mux_15_o + SLICE_X88Y155.CLK Tdick 0.015 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_oe_n<6> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/ocb_d1_1 + ------------------------------------------------- --------------------------- + Total 4.580ns (0.488ns logic, 4.092ns route) + (10.7% logic, 89.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.056ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54].u_iob_dq/wr_data_rise1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.761ns (Levels of Logic = 2) + Clock Path Skew: -0.125ns (1.536 - 1.661) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54].u_iob_dq/wr_data_rise1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y208.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X84Y200.B3 net (fanout=144) 2.822 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X84Y200.BMUX Tilo 0.198 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<181> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMB + SLICE_X83Y180.A6 net (fanout=1) 1.331 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<182> + SLICE_X83Y180.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise1501 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54].u_iob_dq/wr_data_rise1_r1 + ------------------------------------------------- --------------------------- + Total 4.761ns (0.608ns logic, 4.153ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.044ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy_dly_r_9 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy (FF) + Requirement: 0.000ns + Data Path Delay: 0.080ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.516 - 0.480) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy_dly_r_9 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X87Y228.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy_dly_r_9 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy_dly_r_9 + SLICE_X84Y228.AX net (fanout=1) 0.095 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy_dly_r_9 + SLICE_X84Y228.CLK Tckdi (-Th) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant_config_r<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctrl_sync/rdpath_rdy + ------------------------------------------------- --------------------------- + Total 0.080ns (-0.015ns logic, 0.095ns route) + (-18.8% logic, 118.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.049ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_160 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.060ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.063 - 0.052) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_160 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y209.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<163> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_160 + SLICE_X96Y209.AI net (fanout=1) 0.049 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<160> + SLICE_X96Y209.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<157> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.060ns (0.011ns logic, 0.049ns route) + (18.3% logic, 81.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_r_5 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_and_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.067ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_r_5 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_and_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y238.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_r_5 + SLICE_X18Y238.A6 net (fanout=1) 0.045 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_r_5 + SLICE_X18Y238.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_and_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/out11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall1_and_r + ------------------------------------------------- --------------------------- + Total 0.067ns (0.022ns logic, 0.045ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.067ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.076ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y224.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_0 + SLICE_X128Y224.D6 net (fanout=4) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl<0> + SLICE_X128Y224.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_ns<3>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_rd_data0/strict_mode.rd_data_buf_addr_r_lcl_3 + ------------------------------------------------- --------------------------- + Total 0.076ns (0.021ns logic, 0.055ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_reqF/data0_reg_53 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_181 (FF) + Requirement: 0.000ns + Data Path Delay: 0.179ns (Levels of Logic = 0) + Clock Path Skew: 0.110ns (0.799 - 0.689) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_reqF/data0_reg_53 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_181 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y199.CQ Tcko 0.098 ftop/dram0/memc_reqF_D_OUT<54> + ftop/dram0/memc_reqF/data0_reg_53 + SLICE_X92Y200.BX net (fanout=3) 0.170 ftop/dram0/memc_reqF_D_OUT<53> + SLICE_X92Y200.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<183> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_181 + ------------------------------------------------- --------------------------- + Total 0.179ns (0.009ns logic, 0.170ns route) + (5.0% logic, 95.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.069ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_reqF/data0_reg_52 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_180 (FF) + Requirement: 0.000ns + Data Path Delay: 0.179ns (Levels of Logic = 0) + Clock Path Skew: 0.110ns (0.799 - 0.689) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_reqF/data0_reg_52 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_180 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y199.BQ Tcko 0.098 ftop/dram0/memc_reqF_D_OUT<54> + ftop/dram0/memc_reqF/data0_reg_52 + SLICE_X92Y200.AX net (fanout=3) 0.170 ftop/dram0/memc_reqF_D_OUT<52> + SLICE_X92Y200.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<183> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_180 + ------------------------------------------------- --------------------------- + Total 0.179ns (0.009ns logic, 0.170ns route) + (5.0% logic, 95.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_164 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.507 - 0.470) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_164 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y210.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<167> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_164 + SLICE_X96Y210.BI net (fanout=1) 0.095 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<164> + SLICE_X96Y210.CLK Tdh (-Th) 0.086 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<163> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMB + ------------------------------------------------- --------------------------- + Total 0.107ns (0.012ns logic, 0.095ns route) + (11.2% logic, 88.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.070ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_reqF/data0_reg_54 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_182 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 0) + Clock Path Skew: 0.110ns (0.799 - 0.689) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_reqF/data0_reg_54 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_182 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y199.DQ Tcko 0.098 ftop/dram0/memc_reqF_D_OUT<54> + ftop/dram0/memc_reqF/data0_reg_54 + SLICE_X92Y200.CX net (fanout=3) 0.171 ftop/dram0/memc_reqF_D_OUT<54> + SLICE_X92Y200.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<183> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_182 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.009ns logic, 0.171ns route) + (5.0% logic, 95.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.010ns (0.058 - 0.048) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y213.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<73> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_done_state_r_1 + SLICE_X102Y213.A6 net (fanout=5) 0.059 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<71> + SLICE_X102Y213.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done_next<3>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd_top/gen_pd[0].gen_pd_inst.u_phy_pd/pd_incdec_done + ------------------------------------------------- --------------------------- + Total 0.081ns (0.022ns logic, 0.059ns route) + (27.2% logic, 72.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y233.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + SLICE_X12Y233.B6 net (fanout=5) 0.063 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r_15 + SLICE_X12Y233.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r[5][1]_pat_fall0[1][1]_equal_563_o<1>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_fall0_r_5 + ------------------------------------------------- --------------------------- + Total 0.084ns (0.021ns logic, 0.063ns route) + (25.0% logic, 75.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.084ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y223.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1_0 + SLICE_X60Y223.D1 net (fanout=1) 0.265 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r1<0> + SLICE_X60Y223.CLK Tah (-Th) 0.279 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB + ------------------------------------------------- --------------------------- + Total 0.084ns (-0.181ns logic, 0.265ns route) + (-215.5% logic, 315.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_76 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.473 - 0.437) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_76 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X117Y197.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<79> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_76 + SLICE_X118Y196.AI net (fanout=1) 0.100 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<76> + SLICE_X118Y196.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<73> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.111ns (0.011ns logic, 0.100ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_r_0_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.508 - 0.472) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_r_0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y218.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_0 + SLICE_X88Y217.AX net (fanout=2) 0.104 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_wl_0 + SLICE_X88Y217.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_r_0<0> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/inv_dqs_r_0_0 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.009ns logic, 0.104ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume (FF) + Requirement: 0.000ns + Data Path Delay: 0.086ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.050 - 0.041) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X83Y220.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + SLICE_X82Y220.D6 net (fanout=1) 0.045 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r2 + SLICE_X82Y220.CLK Tah (-Th) 0.057 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rdlvl_pat_resume + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume_r_rdlvl_resume_r2_OR_7850_o1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wrlvl/rdlvl_resume + ------------------------------------------------- --------------------------- + Total 0.086ns (0.041ns logic, 0.045ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise1_r_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise1_r_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.481 - 0.446) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise1_r_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise1_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X21Y235.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<40> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_rise1_r_0 + SLICE_X22Y235.A6 net (fanout=1) 0.094 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<37> + SLICE_X22Y235.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise1_r_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise1_r[0][1]_old_sr_rise1_r[0][1]_equal_258_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_match_rise1_r_0 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.022ns logic, 0.094ns route) + (19.0% logic, 81.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMA_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMB_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMC_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<89>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1/CLK + Location pin: SLICE_X16Y186.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA/CLK + Location pin: SLICE_X16Y197.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA/CLK + Location pin: SLICE_X16Y197.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA_D1/CLK + Location pin: SLICE_X16Y197.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<95>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem16_RAMA_D1/CLK + Location pin: SLICE_X16Y197.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = +PERIOD TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" +TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.429ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" TS_SYS0CLK * 2 + HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.071ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 997.500ns (max period limit - period) + Period: 2.500ns + Max period limit: 1000.000ns (1.000MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD TIMEGRP +"ftop_dram0_memc_memc_clk_wr_i" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.035ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.535ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.231ns (Levels of Logic = 1) + Clock Path Delay: 1.291ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.369 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X102Y47.DX net (fanout=1) 0.867 gmii_rxd_7_IBUF + SLICE_X102Y47.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.231ns (0.364ns logic, 0.867ns route) + (29.6% logic, 70.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.376 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.291ns (0.774ns logic, 0.517ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.734ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.813ns (Levels of Logic = 1) + Clock Path Delay: 2.554ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.669 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X102Y47.DX net (fanout=1) 1.312 gmii_rxd_7_IBUF + SLICE_X102Y47.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.813ns (0.501ns logic, 1.312ns route) + (27.6% logic, 72.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.943 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.554ns (1.227ns logic, 1.327ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.045ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.545ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.221ns (Levels of Logic = 1) + Clock Path Delay: 1.291ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.374 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X102Y47.CX net (fanout=1) 0.852 gmii_rxd_6_IBUF + SLICE_X102Y47.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.221ns (0.369ns logic, 0.852ns route) + (30.2% logic, 69.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.376 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.291ns (0.774ns logic, 0.517ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.686ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.765ns (Levels of Logic = 1) + Clock Path Delay: 2.554ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.672 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X102Y47.CX net (fanout=1) 1.261 gmii_rxd_6_IBUF + SLICE_X102Y47.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.765ns (0.504ns logic, 1.261ns route) + (28.6% logic, 71.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.943 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.554ns (1.227ns logic, 1.327ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.051ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.551ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.215ns (Levels of Logic = 1) + Clock Path Delay: 1.291ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.390 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X102Y47.BX net (fanout=1) 0.830 gmii_rxd_5_IBUF + SLICE_X102Y47.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.215ns (0.385ns logic, 0.830ns route) + (31.7% logic, 68.3% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.376 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.291ns (0.774ns logic, 0.517ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.674ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.753ns (Levels of Logic = 1) + Clock Path Delay: 2.554ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.686 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X102Y47.BX net (fanout=1) 1.235 gmii_rxd_5_IBUF + SLICE_X102Y47.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.753ns (0.518ns logic, 1.235ns route) + (29.5% logic, 70.5% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.943 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.554ns (1.227ns logic, 1.327ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.148ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.648ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.118ns (Levels of Logic = 1) + Clock Path Delay: 1.291ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.433 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X102Y47.AX net (fanout=1) 0.690 gmii_rxd_4_IBUF + SLICE_X102Y47.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.118ns (0.428ns logic, 0.690ns route) + (38.3% logic, 61.7% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.376 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.291ns (0.774ns logic, 0.517ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.526ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.605ns (Levels of Logic = 1) + Clock Path Delay: 2.554ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.723 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X102Y47.AX net (fanout=1) 1.050 gmii_rxd_4_IBUF + SLICE_X102Y47.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.605ns (0.555ns logic, 1.050ns route) + (34.6% logic, 65.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y47.CLK net (fanout=40) 0.943 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.554ns (1.227ns logic, 1.327ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.050ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.550ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.263ns (Levels of Logic = 1) + Clock Path Delay: 1.338ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.435 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X102Y39.DX net (fanout=1) 0.833 gmii_rxd_3_IBUF + SLICE_X102Y39.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.263ns (0.430ns logic, 0.833ns route) + (34.0% logic, 66.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.423 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.338ns (0.774ns logic, 0.564ns route) + (57.8% logic, 42.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.665ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.799ns (Levels of Logic = 1) + Clock Path Delay: 2.609ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.725 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X102Y39.DX net (fanout=1) 1.242 gmii_rxd_3_IBUF + SLICE_X102Y39.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.799ns (0.557ns logic, 1.242ns route) + (31.0% logic, 69.0% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.998 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.609ns (1.227ns logic, 1.382ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.104ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.604ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.209ns (Levels of Logic = 1) + Clock Path Delay: 1.338ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.375 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X102Y39.CX net (fanout=1) 0.839 gmii_rxd_2_IBUF + SLICE_X102Y39.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.209ns (0.370ns logic, 0.839ns route) + (30.6% logic, 69.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.423 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.338ns (0.774ns logic, 0.564ns route) + (57.8% logic, 42.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.630ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.764ns (Levels of Logic = 1) + Clock Path Delay: 2.609ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.673 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X102Y39.CX net (fanout=1) 1.259 gmii_rxd_2_IBUF + SLICE_X102Y39.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.764ns (0.505ns logic, 1.259ns route) + (28.6% logic, 71.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.998 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.609ns (1.227ns logic, 1.382ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.107ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.607ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.206ns (Levels of Logic = 1) + Clock Path Delay: 1.338ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.381 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X102Y39.BX net (fanout=1) 0.830 gmii_rxd_1_IBUF + SLICE_X102Y39.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.206ns (0.376ns logic, 0.830ns route) + (31.2% logic, 68.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.423 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.338ns (0.774ns logic, 0.564ns route) + (57.8% logic, 42.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.611ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.745ns (Levels of Logic = 1) + Clock Path Delay: 2.609ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.678 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X102Y39.BX net (fanout=1) 1.235 gmii_rxd_1_IBUF + SLICE_X102Y39.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.745ns (0.510ns logic, 1.235ns route) + (29.2% logic, 70.8% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.998 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.609ns (1.227ns logic, 1.382ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.139ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.639ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.174ns (Levels of Logic = 1) + Clock Path Delay: 1.338ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.435 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X102Y39.AX net (fanout=1) 0.744 gmii_rxd_0_IBUF + SLICE_X102Y39.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.174ns (0.430ns logic, 0.744ns route) + (36.6% logic, 63.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.423 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.338ns (0.774ns logic, 0.564ns route) + (57.8% logic, 42.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.571ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.705ns (Levels of Logic = 1) + Clock Path Delay: 2.609ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.725 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X102Y39.AX net (fanout=1) 1.148 gmii_rxd_0_IBUF + SLICE_X102Y39.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.705ns (0.557ns logic, 1.148ns route) + (32.7% logic, 67.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X102Y39.CLK net (fanout=40) 0.998 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.609ns (1.227ns logic, 1.382ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.140ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.640ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.173ns (Levels of Logic = 1) + Clock Path Delay: 1.338ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.425 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X103Y37.DX net (fanout=1) 0.744 gmii_rx_dv_IBUF + SLICE_X103Y37.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.173ns (0.429ns logic, 0.744ns route) + (36.6% logic, 63.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X103Y37.CLK net (fanout=40) 0.423 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.338ns (0.774ns logic, 0.564ns route) + (57.8% logic, 42.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.591ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.725ns (Levels of Logic = 1) + Clock Path Delay: 2.609ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.716 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X103Y37.DX net (fanout=1) 1.148 gmii_rx_dv_IBUF + SLICE_X103Y37.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.725ns (0.577ns logic, 1.148ns route) + (33.4% logic, 66.6% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X103Y37.CLK net (fanout=40) 0.998 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.609ns (1.227ns logic, 1.382ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.429ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.929ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.811ns (Levels of Logic = 1) + Clock Path Delay: 1.265ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.393 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y46.BX net (fanout=1) 0.414 gmii_rx_er_IBUF + SLICE_X93Y46.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 0.811ns (0.397ns logic, 0.414ns route) + (49.0% logic, 51.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y46.CLK net (fanout=40) 0.350 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.265ns (0.774ns logic, 0.491ns route) + (61.2% logic, 38.8% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.158ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.188ns (Levels of Logic = 1) + Clock Path Delay: 2.505ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.689 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y46.BX net (fanout=1) 0.638 gmii_rx_er_IBUF + SLICE_X93Y46.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 1.188ns (0.550ns logic, 0.638ns route) + (46.3% logic, 53.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y46.CLK net (fanout=40) 0.894 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.505ns (1.227ns logic, 1.278ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Pin to Pin Skew Constraint; + + 1 path analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- +Slack: 0.108ns (maxskew - uncertainty - (arrival1 - arrival2)) + Max skew: 0.450ns + Arrival 1: 2.658ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Arrival 2: 2.505ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/USERCLK + Clock Uncertainty: 0.189ns + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 4.987ns| 0| 0| 91995| 75758| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 4.987ns| N/A| 0| 0| 75758| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 5.213ns| 0| 412| 0| 13051436| +| TS_CLK_125 | 8.000ns| 10.427ns| N/A| 301| 0| 13032139| 0| +| TS_CLK_250 | 4.000ns| 4.410ns| N/A| 111| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +2 constraints not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock gmii_rx_clk +------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +------------+------------+------------+------------+------------+------------------+--------+ +gmii_rx_dv | -0.140(R)| FAST | 0.909(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rx_er | -0.429(R)| FAST | 1.342(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<0> | -0.139(R)| FAST | 0.929(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<1> | -0.107(R)| FAST | 0.889(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<2> | -0.104(R)| FAST | 0.870(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<3> | -0.050(R)| FAST | 0.835(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<4> | -0.148(R)| FAST | 0.974(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<5> | -0.051(R)| FAST | 0.826(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<6> | -0.045(R)| FAST | 0.814(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<7> | -0.035(R)| FAST | 0.766(R)| SLOW |ftop/rxclkBnd | 0.000| +------------+------------+------------+------------+------------+------------------+--------+ + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 5.796| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 4.987| | | | +sys0_clkp | 4.987| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 4.987| | | | +sys0_clkp | 4.987| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.797| | | | +sys1_clkp | 5.797| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.797| | | | +sys1_clkp | 5.797| | | | +---------------+---------+---------+---------+---------+ + +COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.731; Ideal Clock Offset To Actual Clock 0.599; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<7> | -0.035(R)| FAST | 0.766(R)| SLOW | 0.535| 1.734| -0.599| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.035| - | 0.766| - | 0.535| 1.734| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.769; Ideal Clock Offset To Actual Clock 0.571; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<6> | -0.045(R)| FAST | 0.814(R)| SLOW | 0.545| 1.686| -0.571| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.045| - | 0.814| - | 0.545| 1.686| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.775; Ideal Clock Offset To Actual Clock 0.561; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<5> | -0.051(R)| FAST | 0.826(R)| SLOW | 0.551| 1.674| -0.561| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.051| - | 0.826| - | 0.551| 1.674| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.826; Ideal Clock Offset To Actual Clock 0.439; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<4> | -0.148(R)| FAST | 0.974(R)| SLOW | 0.648| 1.526| -0.439| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.148| - | 0.974| - | 0.648| 1.526| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.785; Ideal Clock Offset To Actual Clock 0.558; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<3> | -0.050(R)| FAST | 0.835(R)| SLOW | 0.550| 1.665| -0.558| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.050| - | 0.835| - | 0.550| 1.665| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.766; Ideal Clock Offset To Actual Clock 0.513; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<2> | -0.104(R)| FAST | 0.870(R)| SLOW | 0.604| 1.630| -0.513| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.104| - | 0.870| - | 0.604| 1.630| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.782; Ideal Clock Offset To Actual Clock 0.502; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<1> | -0.107(R)| FAST | 0.889(R)| SLOW | 0.607| 1.611| -0.502| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.107| - | 0.889| - | 0.607| 1.611| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.790; Ideal Clock Offset To Actual Clock 0.466; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<0> | -0.139(R)| FAST | 0.929(R)| SLOW | 0.639| 1.571| -0.466| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.139| - | 0.929| - | 0.639| 1.571| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.769; Ideal Clock Offset To Actual Clock 0.476; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_dv | -0.140(R)| FAST | 0.909(R)| SLOW | 0.640| 1.591| -0.476| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.140| - | 0.909| - | 0.640| 1.591| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.913; Ideal Clock Offset To Actual Clock 0.114; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_er | -0.429(R)| FAST | 1.342(R)| SLOW | 0.929| 1.158| -0.114| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.429| - | 1.342| - | 0.929| 1.158| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + + +Timing summary: +--------------- + +Timing errors: 412 Score: 346570 (Setup/Max: 346535, Hold: 35) + +Constraints cover 13227748 paths, 0 nets, and 222465 connections + +Design statistics: + Minimum period: 10.427ns{1} (Maximum frequency: 95.905MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Mon Feb 3 16:09:36 2014 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 1689 MB + + + diff --git a/logs/ml605-20140203_1611/fpgaTop_map.mrp b/logs/ml605-20140203_1611/fpgaTop_map.mrp new file mode 100644 index 00000000..0f51847e --- /dev/null +++ b/logs/ml605-20140203_1611/fpgaTop_map.mrp @@ -0,0 +1,8532 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc6vlx240t-ff1156-1 -w -logic_opt on -xe n -mt on -t 1 -register_duplication on -ir off -pr off +-lc off -power off -o fpgaTop_map.ncd fpgaTop.ngd fpgaTop.pcf +Target Device : xc6vlx240t +Target Package : ff1156 +Target Speed : -1 +Mapper Version : virtex6 -- $Revision: 1.55 $ +Mapped Date : Mon Feb 3 15:39:23 2014 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 600 +Slice Logic Utilization: + Number of Slice Registers: 35,513 out of 301,440 11% + Number used as Flip Flops: 35,506 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 43,543 out of 150,720 28% + Number used as logic: 37,698 out of 150,720 25% + Number using O6 output only: 34,100 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,188 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 762 + Number with same-slice register load: 630 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 17,310 out of 37,680 45% + Number of LUT Flip Flop pairs used: 51,912 + Number with an unused Flip Flop: 17,424 out of 51,912 33% + Number with an unused LUT: 8,369 out of 51,912 16% + Number of fully used LUT-FF pairs: 26,119 out of 51,912 50% + Number of unique control sets: 2,055 + Number of slice register sites lost + to control set restrictions: 9,858 out of 301,440 3% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + +Average Fanout of Non-Clock Nets: 4.11 + +Peak Memory Usage: 2468 MB +Total REAL time to MAP completion: 22 mins 18 secs +Total CPU time to MAP completion (all processors): 23 mins 8 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_10_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_11_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_12_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_13_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_14_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_15_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_0_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_1_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_2_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_3_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_4_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_5_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_6_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_7_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_8_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_9_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. + The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:2045 - The MMCM_ADV block has CLKOUT pins + that do not drive the same kind of BUFFER load. Routing from the different buffer types will not be phase aligned. + +Section 3 - Informational +------------------------- +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network N100 has no load. +INFO:LIT:395 - The above info message is repeated 4337 more times for the + following (max. 5 shown): + N101, + N102, + N103, + N104, + N105 + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to + 1.050 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_0" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_0) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_1" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_1) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_2" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_2) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_3" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_3) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_4" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_4) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_5" (Output Signal = ftop/ctop/inf/cp/cpReq<6>_REPLICA_5) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_6" (Output Signal = ftop/ctop/inf/cp/cpReq<7>_REPLICA_6) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_7" (Output Signal = ftop/ctop/inf/cp/cpReq<7>_REPLICA_7) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_8" (Output Signal = ftop/ctop/inf/cp/cpReq<7>_REPLICA_8) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_9" (Output Signal = ftop/ctop/inf/cp/cpReq<7>_REPLICA_9) + was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_10" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_10) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_11" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_11) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_12" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_12) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_13" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_13) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_14" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_14) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_15" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_15) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_16" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_16) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_17" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_17) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_18" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_18) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_19" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_19) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_20) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_21) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_25" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_25) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_26" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_26) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_27) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_28" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_28) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_29" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_29) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_30" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_30) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_31" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_31) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_32" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_32) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_33" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_33) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_34" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_34) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_35" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_35) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<22>_REPLICA_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>_REPLICA_36) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_22" (Output Signal = + ftop/ctop/inf/cp/cpReq<22>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_63" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_63) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_64" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_64) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_65" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_65) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_66" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_66) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_67" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_67) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_68" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_68) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_69" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_69) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_70" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_70) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_165" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_165) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_166" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_166) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_167" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_167) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_168" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_168) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_169" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_169) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_170" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_170) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_171" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_171) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_172" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_172) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_173" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_173) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_174" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_174) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_175" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_175) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_176" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_176) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_177" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_177) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_178" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_178) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_179" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_179) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_180" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_180) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_246" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_246) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_247" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_247) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_248" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_248) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_249" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_249) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_250" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_250) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_251" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_251) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_252" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_252) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_253" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_253) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_254" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_254) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_255" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_255) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_256" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_256) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_257" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_257) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_258" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_258) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_270" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_270) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_271" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_271) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_570" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_570) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_571" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_571) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_572" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_572) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_573" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_573) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_574" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_574) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_575" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_575) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_576" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_576) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_577" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_577) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_578" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_578) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_579" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_579) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq_21_REPLICA_601" (Output Signal = + ftop/ctop/inf/cp/cpReq_21_REPLICA_601) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 378 block(s) removed + 422 block(s) optimized away +1789 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +Loadless block "ftop/ctop/inf/cpTlp/Msub_byteCount__h207611" (ROM) removed. +Loadless block "ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block "ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram +[0].RAM32M0" (RAM32M) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<4>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<3>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<2>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<1>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<0>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_0" (FF) removed. +Loadless block "ftop/gbe0/gmac/gmii_rx_clk" (BUFIODQS) removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<31>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<30>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<29>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<28>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<27>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<26>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<25>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<24>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<23>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<22>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<21>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<20>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<19>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<18>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<17>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<16>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<7>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<6>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<5>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<4>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<3>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<2>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tcfg_req_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_terr_drop_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rsrc_dsc_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rerrfwd_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_rd_wr_done_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_err_cpl_rdy_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_rdy_n" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msienable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixenable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixfm" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_en" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_status" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_gen2_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_partner_gen2_supported" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_upcfg_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_received_hot_rst" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCCHECKEN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCGENEN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGERRAERHEADERLOGSETN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRCOR" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRNONFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMASNAK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETO" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETOACK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMPME" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDSETSLOTPOWERLIMIT" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDUNLOCK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVASREQL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL23N" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVREQACKN" is sourceless +and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGSLOTCONTROLELECTROMECHILCTLPULSE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTION" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONTYPE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRA" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRB" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRC" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRD" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRE" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRF" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRG" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRH" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRI" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRJ" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRK" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDRDY" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/LNKCLKEN" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRESET" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLPHYLNKUPN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/RECEIVEDFUNCLVLRSTN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNRECRCERRN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNTDLLPDSTRDYN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<15>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<14>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<13>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<12>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<11>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<10>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<9>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<8>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<7>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<0>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<31>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<30>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<29>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<28>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<27>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<26>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<25>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<24>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<23>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<22>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<21>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<20>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<19>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<18>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<17>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<16>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<47>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<46>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<45>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<44>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<43>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<42>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<41>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<40>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<39>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<38>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<37>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<36>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<35>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<34>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<33>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<32>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<63>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<62>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<61>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<60>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<59>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<58>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<57>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<56>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<55>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<54>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<53>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<52>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<51>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<50>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<49>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<48>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<68>" +is sourceless and has been removed. +The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n008211" (ROM) removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n0082" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" (SFF) removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" (ROM) +removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" is sourceless and +has been removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<23>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<22>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<21>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<20>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<19>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<18>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<17>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<16>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<15>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<14>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<13>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<12>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_2_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_2_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_2_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_2_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_2_memory_DOB<27>" is sourceless and has been +removed. +The signal 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"ftop/cap0/dataBram_0_memory/DOA<27>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<26>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<25>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<24>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<23>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<22>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<21>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<20>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<19>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<18>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<17>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<16>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dqs_n_tap_cnt<32>" is sourceless and has +been removed. + Sourceless block "ftop/dram0/memc_memc/scl_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/scl" is sourceless and has been removed. + Sourceless block "ftop/dram0/memc_memc/sda_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/sda" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/N1" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<39>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<38>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<37>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<36>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<35>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<34>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<33>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<32>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<31>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<30>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<29>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<28>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<27>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<26>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<25>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<24>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<23>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<22>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<21>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<20>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<19>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<18>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<17>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<16>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<15>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<14>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<13>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<12>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<11>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<10>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<9>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<8>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<7>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<6>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<5>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<4>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<3>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<2>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<1>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<0>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/ddr_parity" is sourceless and has +been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<9>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<8>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<7>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<6>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<5>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<4>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<3>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<2>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<1>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<0>" +is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/inv_dqs<0>1 +" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<97>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<99>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<100>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<101>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<102>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<103>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<104>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<105>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<106>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<107>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<160>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<161>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<162>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<163>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<164>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<165>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<166>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<167>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<168>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<169>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<170>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<171>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<172>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<173>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<174>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<175>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<176>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<177>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<178>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<179>" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_infrastructure/PSDONE" is sourceless and has +been removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[100].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[101].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[102].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[103].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[104].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[105].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[106].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[107].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[97].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[99].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[160].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[161].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[162].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[163].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[164].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[165].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[166].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[167].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[168].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[169].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[170].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[171].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[172].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[173].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[174].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[175].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[176].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[177].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[178].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[179].u_RAM64X1D" (RAM64X1D) removed. +Unused block "ftop/dram0/memc_memc/XST_GND" (ZERO) removed. +Unused block "ftop/dram0/memc_memc/XST_VCC" (ONE) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/u_out_ +parity" (OSERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. + +Optimized Block(s): +TYPE BLOCK +VCC XST_VCC +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/axbluart/a4l_a4wrData_fifof/XST_GND +GND ftop/axbluart/bluart/XST_GND +VCC ftop/axbluart/bluart/XST_VCC +GND ftop/axbluart/bluart/rxF/XST_GND +GND ftop/cap0/XST_GND +VCC ftop/cap0/XST_VCC +GND ftop/cap0/dataBram_0_memory/XST_GND +VCC ftop/cap0/dataBram_0_memory/XST_VCC +GND ftop/cap0/dataBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_0_memory/XST_GND +VCC ftop/cap0/metaBram_0_memory/XST_VCC +GND ftop/cap0/metaBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_1_memory/XST_GND +VCC ftop/cap0/metaBram_1_memory/XST_VCC +GND ftop/cap0/metaBram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_2_memory/XST_GND +VCC ftop/cap0/metaBram_2_memory/XST_VCC +GND ftop/cap0/metaBram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_3_memory/XST_GND +VCC ftop/cap0/metaBram_3_memory/XST_VCC +GND ftop/cap0/metaBram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/wci_wslv_reqF/XST_GND +GND ftop/cap0/wsiS_reqFifo/XST_GND +VCC ftop/cap0/wsiS_reqFifo/XST_VCC +GND ftop/ctop/app/XST_GND +GND ftop/ctop/app/appW1/XST_GND +VCC ftop/ctop/app/appW1/XST_VCC +GND ftop/ctop/app/appW1/rgen_gsF/XST_GND +GND ftop/ctop/app/appW1/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW2/XST_GND +VCC ftop/ctop/app/appW2/XST_VCC +GND ftop/ctop/app/appW2/respF_memory/XST_GND +VCC ftop/ctop/app/appW2/respF_memory/XST_VCC +GND ftop/ctop/app/appW2/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/XST_GND +VCC ftop/ctop/app/appW3/XST_VCC +GND ftop/ctop/app/appW3/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/appW4/XST_GND +VCC ftop/ctop/app/appW4/XST_VCC +GND ftop/ctop/app/appW4/respF_memory/XST_GND +VCC ftop/ctop/app/appW4/respF_memory/XST_VCC +GND ftop/ctop/app/appW4/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW4/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/id/XST_GND +VCC ftop/ctop/app/id/XST_VCC +GND ftop/ctop/inf/cp/XST_GND +VCC ftop/ctop/inf/cp/XST_VCC +GND ftop/ctop/inf/cp/rom_memory/XST_GND +VCC ftop/ctop/inf/cp/rom_memory/XST_VCC +GND ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/ctop/inf/cp/timeServ_setRefF/XST_GND +VCC ftop/ctop/inf/cp/wci_10_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_11_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_12_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_13_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_14_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_1_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_2_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_3_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_4_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_8_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_9_mReset/rstSync/XST_VCC +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h207610 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20762 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20763 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20764 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20765 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20766 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20767 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20768 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20769 + optimized to 1 +GND ftop/ctop/inf/cpTlp/XST_GND +VCC ftop/ctop/inf/cpTlp/XST_VCC +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp0/XST_GND +VCC ftop/ctop/inf/dp0/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/wci_reqF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_reqF/XST_GND +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp1/XST_GND +VCC ftop/ctop/inf/dp1/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/wci_reqF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_dhF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_reqF/XST_GND +GND ftop/dram0/XST_GND +VCC ftop/dram0/XST_VCC +GND ftop/dram0/dbg_dqs_n_tap_cnt/XST_GND +GND ftop/dram0/dbg_dqs_p_tap_cnt/XST_GND +GND ftop/dram0/dbg_rdlvl_err/XST_GND +GND ftop/dram0/lreqF/XST_GND +GND ftop/dram0/lrespF/XST_GND +GND ftop/dram0/memc_memc/u_infrastructure/XST_GND +VCC ftop/dram0/memc_memc/u_infrastructure/XST_VCC +GND ftop/dram0/memc_memc/u_iodelay_ctrl/XST_GND +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_state0/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd +_top/gen_pd[0].gen_pd_inst.u_phy_pd/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wr +lvl/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_G +ND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_V +CC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctr +l_sync/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_VCC +VCC ftop/dram0/memc_rst_stretch_n/XST_VCC +GND ftop/dram0/wci_wslv_reqF/XST_GND +GND ftop/flash0/XST_GND +VCC ftop/flash0/XST_VCC +GND ftop/flash0/wci_wslv_reqF/XST_GND +GND ftop/fmc150/XST_GND +VCC ftop/fmc150/XST_VCC +VCC ftop/fmc150/fcCdc_testRst/XST_VCC +VCC ftop/fmc150/spiCDC_slowReset/XST_VCC +VCC ftop/fmc150/spiDAC_slowReset/XST_VCC +GND ftop/fmc150/wci_wslv_reqF/XST_GND +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/rxRS_rxRst/XST_VCC +GND ftop/gbe0/gmac/txRS_txF/XST_GND +VCC ftop/gbe0/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbe0/wci_wslv_reqF/XST_GND +GND ftop/lcd_ctrl/XST_GND +VCC ftop/lcd_ctrl/XST_VCC +GND ftop/pciw_fI2P/XST_GND +GND ftop/pciw_fP2I/XST_GND +VCC ftop/pciw_p125rst/XST_VCC +VCC ftop/pciw_p250rst/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_VCC +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/XS +T_GND +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_VCC +VCC ftop/sys0_rst/XST_VCC +GND ftop/wmemiTap/XST_GND +VCC ftop/wmemiTap/XST_VCC +LUT2 ftop/ctop/inf/noc_sm2/pktFork/fo1/Result<2>_SW0 + optimized to 0 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ddr3_addr<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<8> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<9> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<10> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<11> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<12> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cas_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ck_n<0> | IOBS | OUTPUT | DIFF_SSTL15 | | | | | | | +| ddr3_ck_p<0> | IOBM | OUTPUT | DIFF_SSTL15 | | | | OSERDES | | | +| ddr3_cke<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cs_n<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_dm<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dq<0> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<1> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<2> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<3> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<4> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<5> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<6> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<7> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<8> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<9> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<10> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<11> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<12> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<13> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<14> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<15> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<16> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<17> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<18> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<19> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<20> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<21> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<22> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<23> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<24> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<25> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<26> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<27> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<28> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<29> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<30> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<31> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<32> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<33> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<34> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<35> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<36> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<37> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<38> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<39> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<40> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<41> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<42> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<43> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<44> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<45> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<46> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<47> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<48> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<49> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<50> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<51> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<52> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<53> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<54> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<55> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<56> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<57> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<58> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<59> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<60> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<61> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<62> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<63> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_n<0> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<1> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<2> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<3> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<4> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<5> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<6> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<7> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_p<0> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_p<1> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<2> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<3> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<4> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<5> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<6> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<7> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_odt<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ras_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_reset_n | IOB | OUTPUT | SSTL15 | | | | ODDR | | | +| ddr3_we_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| flash_addr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_ce_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_oe_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_wait | IOB | INPUT | LVCMOS25 | | | | | | | +| flash_we_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_clk_n | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_clk_p | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_pdn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_refen | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| flp_com_sclk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_com_sdc2m | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| gmii_rx_clk | IOB | INPUT | LVCMOS25 | | | | | | FIXED | +| gmii_rx_dv | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rx_er | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<7> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| lcd_db<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_e | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rw | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdd | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| pci0_clkn | IPAD | INPUT | | | | | | | | +| pci0_clkp | IPAD | INPUT | | | | | | | | +| pci0_reset_n | IOB | INPUT | LVCMOS25 | | | | | PULLUP | | +| pci_exp_rxn<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<3> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<3> | IPAD | INPUT | | | | | | | | +| pci_exp_txn<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<3> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<3> | OPAD | OUTPUT | | | | | | | | +| ppsExtIn | IOB | INPUT | LVCMOS25 | | | | | | | +| ppsOut | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| sys0_clkn | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys0_clkp | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys1_clkn | IPAD | INPUT | | | | | | | | +| sys1_clkp | IPAD | INPUT | | | | | | | | +| upads_cts_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_rts | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| upads_rx_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_tx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_pcie0" + No COMPRESSION specified for Area Group "AG_pcie0" + RANGE: SLICE_X136Y147:SLICE_X155Y120 + Slice Logic Utilization: + Number of Slice Registers: 460 out of 4,480 10% + Number of Slice LUTs: 681 out of 2,240 30% + Number used as logic: 677 + Number used as Memory: 4 + Slice Logic Distribution: + Number of occupied Slices: 283 out of 560 50% + Number of LUT Flip Flop pairs used: 752 + Number with an unused Flip Flop: 324 out of 752 43% + Number with an unused LUT: 55 out of 752 7% + Number of fully used LUT-FF pairs: 373 out of 752 49% + Number of RAMB36E1/FIFO36E1s: 8 + Number using RAMB36E1 only: 8 + Number using FIFO36E1 only: 0 + + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/rtl/mkAXBLUART.v b/rtl/mkAXBLUART.v new file mode 100644 index 00000000..bece5aba --- /dev/null +++ b/rtl/mkAXBLUART.v @@ -0,0 +1,941 @@ +// +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) +// +// On Mon Feb 3 15:04:27 EST 2014 +// +// +// Ports: +// Name I/O size props +// s_axi_AWREADY O 1 reg +// s_axi_WREADY O 1 reg +// s_axi_BVALID O 1 +// s_axi_BRESP O 2 reg +// s_axi_ARREADY O 1 reg +// s_axi_RVALID O 1 +// s_axi_RDATA O 32 reg +// s_axi_RRESP O 2 reg +// upads_rts O 1 const +// upads_tx O 1 reg +// s_axi_aclk I 1 clock +// s_axi_aresetn I 1 reset +// s_axi_AWADDR I 32 reg +// s_axi_AWPROT I 3 reg +// s_axi_WDATA I 32 reg +// s_axi_WSTRB I 4 reg +// s_axi_ARADDR I 32 reg +// s_axi_ARPROT I 3 reg +// upads_cts_arg I 1 reg +// upads_rx_arg I 1 reg +// s_axi_AWVALID I 1 +// s_axi_WVALID I 1 +// s_axi_BREADY I 1 +// s_axi_ARVALID I 1 +// s_axi_RREADY I 1 +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkAXBLUART(s_axi_aclk, + s_axi_aresetn, + + s_axi_AWVALID, + + s_axi_AWREADY, + + s_axi_AWADDR, + + s_axi_AWPROT, + + s_axi_WVALID, + + s_axi_WREADY, + + s_axi_WDATA, + + s_axi_WSTRB, + + s_axi_BVALID, + + s_axi_BREADY, + + s_axi_BRESP, + + s_axi_ARVALID, + + s_axi_ARREADY, + + s_axi_ARADDR, + + s_axi_ARPROT, + + s_axi_RVALID, + + s_axi_RREADY, + + s_axi_RDATA, + + s_axi_RRESP, + + upads_rts, + + upads_tx, + + upads_cts_arg, + + upads_rx_arg); + input s_axi_aclk; + input s_axi_aresetn; + + // action method s_axi_mAWVALID + input s_axi_AWVALID; + + // value method s_axi_sAWREADY + output s_axi_AWREADY; + + // action method s_axi_mAWADDR + input [31 : 0] s_axi_AWADDR; + + // action method s_axi_mAWPROT + input [2 : 0] s_axi_AWPROT; + + // action method s_axi_mWVALID + input s_axi_WVALID; + + // value method s_axi_sWREADY + output s_axi_WREADY; + + // action method s_axi_mWDATA + input [31 : 0] s_axi_WDATA; + + // action method s_axi_mWSTRB + input [3 : 0] s_axi_WSTRB; + + // value method s_axi_sBVALID + output s_axi_BVALID; + + // action method s_axi_mBREADY + input s_axi_BREADY; + + // value method s_axi_sBRESP + output [1 : 0] s_axi_BRESP; + + // action method s_axi_mARVALID + input s_axi_ARVALID; + + // value method s_axi_sARREADY + output s_axi_ARREADY; + + // action method s_axi_mARADDR + input [31 : 0] s_axi_ARADDR; + + // action method s_axi_mARPROT + input [2 : 0] s_axi_ARPROT; + + // value method s_axi_sRVALID + output s_axi_RVALID; + + // action method s_axi_mRREADY + input s_axi_RREADY; + + // value method s_axi_sRDATA + output [31 : 0] s_axi_RDATA; + + // value method s_axi_sRRESP + output [1 : 0] s_axi_RRESP; + + // value method upads_rts + output upads_rts; + + // value method upads_tx + output upads_tx; + + // action method upads_cts + input upads_cts_arg; + + // action method upads_rx + input upads_rx_arg; + + // signals for module outputs + wire [31 : 0] s_axi_RDATA; + wire [1 : 0] s_axi_BRESP, s_axi_RRESP; + wire s_axi_ARREADY, + s_axi_AWREADY, + s_axi_BVALID, + s_axi_RVALID, + s_axi_WREADY, + upads_rts, + upads_tx; + + // inlined wires + wire [35 : 0] a4l_a4wrData_data_wire_wget; + wire [34 : 0] a4l_a4rdAddr_data_wire_wget, a4l_a4wrAddr_data_wire_wget; + wire [33 : 0] a4l_a4rdResp_fifof_x_wire_wget; + wire [31 : 0] a4ls_rdAddr_w_wget, a4ls_wrAddr_w_wget, a4ls_wrData_w_wget; + wire [3 : 0] a4ls_wrStrb_w_wget; + wire [2 : 0] a4ls_rdProt_w_wget, a4ls_wrProt_w_wget; + wire [1 : 0] a4l_a4wrResp_fifof_x_wire_wget; + wire a4l_a4rdAddr_enq_enq_whas, + a4l_a4rdAddr_enq_valid_whas, + a4l_a4rdResp_deq_deq_whas, + a4l_a4rdResp_deq_ready_whas, + a4l_a4rdResp_fifof_dequeueing_whas, + a4l_a4rdResp_fifof_enqueueing_whas, + a4l_a4rdResp_fifof_x_wire_whas, + a4l_a4wrAddr_enq_enq_whas, + a4l_a4wrAddr_enq_valid_whas, + a4l_a4wrData_enq_enq_whas, + a4l_a4wrData_enq_valid_whas, + a4l_a4wrResp_deq_deq_whas, + a4l_a4wrResp_deq_ready_whas, + a4l_a4wrResp_fifof_dequeueing_whas, + a4l_a4wrResp_fifof_enqueueing_whas, + a4l_a4wrResp_fifof_x_wire_whas, + a4ls_rdAddrVal_w_wget, + a4ls_rdAddrVal_w_whas, + a4ls_rdAddr_w_whas, + a4ls_rdProt_w_whas, + a4ls_rdRespRdy_w_wget, + a4ls_rdRespRdy_w_whas, + a4ls_wrAddrVal_w_wget, + a4ls_wrAddrVal_w_whas, + a4ls_wrAddr_w_whas, + a4ls_wrDataVal_w_wget, + a4ls_wrDataVal_w_whas, + a4ls_wrData_w_whas, + a4ls_wrProt_w_whas, + a4ls_wrRespRdy_w_wget, + a4ls_wrRespRdy_w_whas, + a4ls_wrStrb_w_whas; + + // register a4l_a4rdResp_fifof_cntr_r + reg [1 : 0] a4l_a4rdResp_fifof_cntr_r; + wire [1 : 0] a4l_a4rdResp_fifof_cntr_r_D_IN; + wire a4l_a4rdResp_fifof_cntr_r_EN; + + // register a4l_a4rdResp_fifof_q_0 + reg [33 : 0] a4l_a4rdResp_fifof_q_0; + reg [33 : 0] a4l_a4rdResp_fifof_q_0_D_IN; + wire a4l_a4rdResp_fifof_q_0_EN; + + // register a4l_a4rdResp_fifof_q_1 + reg [33 : 0] a4l_a4rdResp_fifof_q_1; + reg [33 : 0] a4l_a4rdResp_fifof_q_1_D_IN; + wire a4l_a4rdResp_fifof_q_1_EN; + + // register a4l_a4wrResp_fifof_cntr_r + reg [1 : 0] a4l_a4wrResp_fifof_cntr_r; + wire [1 : 0] a4l_a4wrResp_fifof_cntr_r_D_IN; + wire a4l_a4wrResp_fifof_cntr_r_EN; + + // register a4l_a4wrResp_fifof_q_0 + reg [1 : 0] a4l_a4wrResp_fifof_q_0; + reg [1 : 0] a4l_a4wrResp_fifof_q_0_D_IN; + wire a4l_a4wrResp_fifof_q_0_EN; + + // register a4l_a4wrResp_fifof_q_1 + reg [1 : 0] a4l_a4wrResp_fifof_q_1; + wire [1 : 0] a4l_a4wrResp_fifof_q_1_D_IN; + wire a4l_a4wrResp_fifof_q_1_EN; + + // register r0 + reg [31 : 0] r0; + wire [31 : 0] r0_D_IN; + wire r0_EN; + + // register r4 + reg [31 : 0] r4; + wire [31 : 0] r4_D_IN; + wire r4_EN; + + // register r8 + reg [31 : 0] r8; + wire [31 : 0] r8_D_IN; + wire r8_EN; + + // register rC + reg [31 : 0] rC; + wire [31 : 0] rC_D_IN; + wire rC_EN; + + // register uartInited + reg uartInited; + wire uartInited_D_IN, uartInited_EN; + + // register uartTxtP + reg [5 : 0] uartTxtP; + wire [5 : 0] uartTxtP_D_IN; + wire uartTxtP_EN; + + // ports of submodule a4l_a4rdAddr_fifof + wire [34 : 0] a4l_a4rdAddr_fifof_D_IN, a4l_a4rdAddr_fifof_D_OUT; + wire a4l_a4rdAddr_fifof_CLR, + a4l_a4rdAddr_fifof_DEQ, + a4l_a4rdAddr_fifof_EMPTY_N, + a4l_a4rdAddr_fifof_ENQ, + a4l_a4rdAddr_fifof_FULL_N; + + // ports of submodule a4l_a4wrAddr_fifof + wire [34 : 0] a4l_a4wrAddr_fifof_D_IN, a4l_a4wrAddr_fifof_D_OUT; + wire a4l_a4wrAddr_fifof_CLR, + a4l_a4wrAddr_fifof_DEQ, + a4l_a4wrAddr_fifof_EMPTY_N, + a4l_a4wrAddr_fifof_ENQ, + a4l_a4wrAddr_fifof_FULL_N; + + // ports of submodule a4l_a4wrData_fifof + wire [35 : 0] a4l_a4wrData_fifof_D_IN, a4l_a4wrData_fifof_D_OUT; + wire a4l_a4wrData_fifof_CLR, + a4l_a4wrData_fifof_DEQ, + a4l_a4wrData_fifof_EMPTY_N, + a4l_a4wrData_fifof_ENQ, + a4l_a4wrData_fifof_FULL_N; + + // ports of submodule bluart + wire [15 : 0] bluart_setClkDiv_put; + wire [7 : 0] bluart_rxChar_get, + bluart_rxLevel, + bluart_txChar_put, + bluart_txLevel; + wire bluart_EN_rxChar_get, + bluart_EN_setClkDiv_put, + bluart_EN_txChar_put, + bluart_RDY_rxChar_get, + bluart_RDY_txChar_put, + bluart_pads_cts_arg, + bluart_pads_rts, + bluart_pads_rx_arg, + bluart_pads_tx; + + // rule scheduling signals + wire CAN_FIRE_RL_a4l_cfwr, + WILL_FIRE_RL_a4l_a4rdResp_fifof_both, + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr, + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr, + WILL_FIRE_RL_a4l_a4wrResp_fifof_both, + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr, + WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr, + WILL_FIRE_RL_a4l_cfrd, + WILL_FIRE_RL_a4l_cfwr, + WILL_FIRE_RL_init_uart_text; + + // inputs to muxes for submodule ports + reg [7 : 0] MUX_bluart_txChar_put_1__VAL_2; + wire [33 : 0] MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1, + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2, + MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2; + wire [1 : 0] MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2, + MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2, + MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2; + wire MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1, + MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2, + MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1, + MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2, + MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1, + MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2, + MUX_bluart_txChar_put_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h6161, v__h6550, v__h6582; + reg [31 : 0] v__h6235; + reg [7 : 0] put__h3589; + wire [31 : 0] rdat__h6319, rdat__h6325, v__h6356; + wire [5 : 0] x__h3633; + wire [1 : 0] a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60, + a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27; + wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; + + // value method s_axi_sAWREADY + assign s_axi_AWREADY = a4l_a4wrAddr_fifof_FULL_N ; + + // value method s_axi_sWREADY + assign s_axi_WREADY = a4l_a4wrData_fifof_FULL_N ; + + // value method s_axi_sBVALID + assign s_axi_BVALID = a4l_a4wrResp_fifof_cntr_r != 2'd0 ; + + // value method s_axi_sBRESP + assign s_axi_BRESP = a4l_a4wrResp_fifof_q_0 ; + + // value method s_axi_sARREADY + assign s_axi_ARREADY = a4l_a4rdAddr_fifof_FULL_N ; + + // value method s_axi_sRVALID + assign s_axi_RVALID = a4l_a4rdResp_fifof_cntr_r != 2'd0 ; + + // value method s_axi_sRDATA + assign s_axi_RDATA = a4l_a4rdResp_fifof_q_0[31:0] ; + + // value method s_axi_sRRESP + assign s_axi_RRESP = a4l_a4rdResp_fifof_q_0[33:32] ; + + // value method upads_rts + assign upads_rts = bluart_pads_rts ; + + // value method upads_tx + assign upads_tx = bluart_pads_tx ; + + // submodule a4l_a4rdAddr_fifof + FIFO2 #(.width(32'd35), + .guarded(32'd1)) a4l_a4rdAddr_fifof(.RST(s_axi_aresetn), + .CLK(s_axi_aclk), + .D_IN(a4l_a4rdAddr_fifof_D_IN), + .ENQ(a4l_a4rdAddr_fifof_ENQ), + .DEQ(a4l_a4rdAddr_fifof_DEQ), + .CLR(a4l_a4rdAddr_fifof_CLR), + .D_OUT(a4l_a4rdAddr_fifof_D_OUT), + .FULL_N(a4l_a4rdAddr_fifof_FULL_N), + .EMPTY_N(a4l_a4rdAddr_fifof_EMPTY_N)); + + // submodule a4l_a4wrAddr_fifof + FIFO2 #(.width(32'd35), + .guarded(32'd1)) a4l_a4wrAddr_fifof(.RST(s_axi_aresetn), + .CLK(s_axi_aclk), + .D_IN(a4l_a4wrAddr_fifof_D_IN), + .ENQ(a4l_a4wrAddr_fifof_ENQ), + .DEQ(a4l_a4wrAddr_fifof_DEQ), + .CLR(a4l_a4wrAddr_fifof_CLR), + .D_OUT(a4l_a4wrAddr_fifof_D_OUT), + .FULL_N(a4l_a4wrAddr_fifof_FULL_N), + .EMPTY_N(a4l_a4wrAddr_fifof_EMPTY_N)); + + // submodule a4l_a4wrData_fifof + FIFO2 #(.width(32'd36), + .guarded(32'd1)) a4l_a4wrData_fifof(.RST(s_axi_aresetn), + .CLK(s_axi_aclk), + .D_IN(a4l_a4wrData_fifof_D_IN), + .ENQ(a4l_a4wrData_fifof_ENQ), + .DEQ(a4l_a4wrData_fifof_DEQ), + .CLR(a4l_a4wrData_fifof_CLR), + .D_OUT(a4l_a4wrData_fifof_D_OUT), + .FULL_N(a4l_a4wrData_fifof_FULL_N), + .EMPTY_N(a4l_a4wrData_fifof_EMPTY_N)); + + // submodule bluart + mkBLUART bluart(.CLK(s_axi_aclk), + .RST_N(s_axi_aresetn), + .pads_cts_arg(bluart_pads_cts_arg), + .pads_rx_arg(bluart_pads_rx_arg), + .setClkDiv_put(bluart_setClkDiv_put), + .txChar_put(bluart_txChar_put), + .EN_setClkDiv_put(bluart_EN_setClkDiv_put), + .EN_txChar_put(bluart_EN_txChar_put), + .EN_rxChar_get(bluart_EN_rxChar_get), + .RDY_setClkDiv_put(), + .txLevel(bluart_txLevel), + .RDY_txLevel(), + .rxLevel(bluart_rxLevel), + .RDY_rxLevel(), + .RDY_txChar_put(bluart_RDY_txChar_put), + .rxChar_get(bluart_rxChar_get), + .RDY_rxChar_get(bluart_RDY_rxChar_get), + .pads_rts(bluart_pads_rts), + .pads_tx(bluart_pads_tx)); + + // rule RL_a4l_cfrd + assign WILL_FIRE_RL_a4l_cfrd = + a4l_a4rdResp_fifof_cntr_r != 2'd2 && + a4l_a4rdAddr_fifof_EMPTY_N && + (a4l_a4rdAddr_fifof_D_OUT[7:0] != 8'h30 || + bluart_RDY_rxChar_get) ; + + // rule RL_init_uart_text + assign WILL_FIRE_RL_init_uart_text = bluart_RDY_txChar_put && !uartInited ; + + // rule RL_a4l_cfwr + assign CAN_FIRE_RL_a4l_cfwr = + a4l_a4wrResp_fifof_cntr_r != 2'd2 && + a4l_a4wrAddr_fifof_EMPTY_N && + a4l_a4wrData_fifof_EMPTY_N && + (a4l_a4wrAddr_fifof_D_OUT[7:0] != 8'h2C || + bluart_RDY_txChar_put) ; + assign WILL_FIRE_RL_a4l_cfwr = + CAN_FIRE_RL_a4l_cfwr && !WILL_FIRE_RL_init_uart_text ; + + // rule RL_a4l_a4wrResp_fifof_incCtr + assign WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr = + WILL_FIRE_RL_a4l_cfwr && WILL_FIRE_RL_a4l_cfwr && + !a4l_a4wrResp_fifof_dequeueing_whas ; + + // rule RL_a4l_a4wrResp_fifof_decCtr + assign WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr = + a4l_a4wrResp_fifof_dequeueing_whas && !WILL_FIRE_RL_a4l_cfwr ; + + // rule RL_a4l_a4wrResp_fifof_both + assign WILL_FIRE_RL_a4l_a4wrResp_fifof_both = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrResp_fifof_dequeueing_whas && + WILL_FIRE_RL_a4l_cfwr ; + + // rule RL_a4l_a4rdResp_fifof_incCtr + assign WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr = + WILL_FIRE_RL_a4l_cfrd && WILL_FIRE_RL_a4l_cfrd && + !a4l_a4rdResp_fifof_dequeueing_whas ; + + // rule RL_a4l_a4rdResp_fifof_decCtr + assign WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr = + a4l_a4rdResp_fifof_dequeueing_whas && !WILL_FIRE_RL_a4l_cfrd ; + + // rule RL_a4l_a4rdResp_fifof_both + assign WILL_FIRE_RL_a4l_a4rdResp_fifof_both = + WILL_FIRE_RL_a4l_cfrd && a4l_a4rdResp_fifof_dequeueing_whas && + WILL_FIRE_RL_a4l_cfrd ; + + // inputs to muxes for submodule ports + assign MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr && + a4l_a4rdResp_fifof_cntr_r == 2'd0 ; + assign MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo7 ; + assign MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr && + a4l_a4rdResp_fifof_cntr_r == 2'd1 ; + assign MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo5 ; + assign MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1 = + WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr && + a4l_a4wrResp_fifof_cntr_r == 2'd0 ; + assign MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2 = + WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo3 ; + assign MUX_bluart_txChar_put_1__SEL_1 = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h2C ; + assign MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2 = + a4l_a4rdResp_fifof_cntr_r + 2'd1 ; + assign MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 = { 2'd0, v__h6235 } ; + assign MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2 = + (a4l_a4rdResp_fifof_cntr_r == 2'd1) ? + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 : + a4l_a4rdResp_fifof_q_1 ; + assign MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2 = + (a4l_a4rdResp_fifof_cntr_r == 2'd2) ? + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 : + 34'd0 ; + assign MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2 = + a4l_a4wrResp_fifof_cntr_r + 2'd1 ; + assign MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2 = + (a4l_a4wrResp_fifof_cntr_r == 2'd1) ? + 2'd0 : + a4l_a4wrResp_fifof_q_1 ; + always@(uartTxtP or put__h3589) + begin + case (uartTxtP) + 6'd0, 6'd42: MUX_bluart_txChar_put_1__VAL_2 = 8'h0D; + 6'd1, 6'd43: MUX_bluart_txChar_put_1__VAL_2 = 8'h0A; + default: MUX_bluart_txChar_put_1__VAL_2 = put__h3589; + endcase + end + + // inlined wires + assign a4l_a4wrResp_fifof_x_wire_wget = 2'd0 ; + assign a4l_a4wrResp_fifof_x_wire_whas = WILL_FIRE_RL_a4l_cfwr ; + assign a4l_a4rdResp_fifof_x_wire_wget = + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 ; + assign a4l_a4rdResp_fifof_x_wire_whas = WILL_FIRE_RL_a4l_cfrd ; + assign a4ls_wrAddrVal_w_wget = 1'd1 ; + assign a4ls_wrAddrVal_w_whas = s_axi_AWVALID ; + assign a4ls_wrDataVal_w_wget = 1'd1 ; + assign a4ls_wrDataVal_w_whas = s_axi_WVALID ; + assign a4ls_wrRespRdy_w_wget = 1'd1 ; + assign a4ls_wrRespRdy_w_whas = s_axi_BREADY ; + assign a4ls_rdAddrVal_w_wget = 1'd1 ; + assign a4ls_rdAddrVal_w_whas = s_axi_ARVALID ; + assign a4ls_rdRespRdy_w_wget = 1'd1 ; + assign a4ls_rdRespRdy_w_whas = s_axi_RREADY ; + assign a4ls_wrAddr_w_wget = s_axi_AWADDR ; + assign a4ls_wrAddr_w_whas = 1'd1 ; + assign a4ls_wrProt_w_wget = s_axi_AWPROT ; + assign a4ls_wrProt_w_whas = 1'd1 ; + assign a4ls_wrData_w_wget = s_axi_WDATA ; + assign a4ls_wrData_w_whas = 1'd1 ; + assign a4ls_wrStrb_w_wget = s_axi_WSTRB ; + assign a4ls_wrStrb_w_whas = 1'd1 ; + assign a4ls_rdAddr_w_wget = s_axi_ARADDR ; + assign a4ls_rdAddr_w_whas = 1'd1 ; + assign a4ls_rdProt_w_wget = s_axi_ARPROT ; + assign a4ls_rdProt_w_whas = 1'd1 ; + assign a4l_a4wrAddr_enq_valid_whas = s_axi_AWVALID ; + assign a4l_a4wrAddr_enq_enq_whas = 1'b0 ; + assign a4l_a4wrData_enq_valid_whas = s_axi_WVALID ; + assign a4l_a4wrData_enq_enq_whas = 1'b0 ; + assign a4l_a4wrResp_fifof_enqueueing_whas = WILL_FIRE_RL_a4l_cfwr ; + assign a4l_a4wrResp_fifof_dequeueing_whas = + a4l_a4wrResp_fifof_cntr_r != 2'd0 && s_axi_BREADY ; + assign a4l_a4wrResp_deq_ready_whas = s_axi_BREADY ; + assign a4l_a4wrResp_deq_deq_whas = 1'b0 ; + assign a4l_a4rdAddr_enq_valid_whas = s_axi_ARVALID ; + assign a4l_a4rdAddr_enq_enq_whas = 1'b0 ; + assign a4l_a4rdResp_fifof_enqueueing_whas = WILL_FIRE_RL_a4l_cfrd ; + assign a4l_a4rdResp_fifof_dequeueing_whas = + a4l_a4rdResp_fifof_cntr_r != 2'd0 && s_axi_RREADY ; + assign a4l_a4rdResp_deq_ready_whas = s_axi_RREADY ; + assign a4l_a4rdResp_deq_deq_whas = 1'b0 ; + assign a4l_a4wrAddr_data_wire_wget = { s_axi_AWPROT, s_axi_AWADDR } ; + assign a4l_a4wrData_data_wire_wget = { s_axi_WSTRB, s_axi_WDATA } ; + assign a4l_a4rdAddr_data_wire_wget = { s_axi_ARPROT, s_axi_ARADDR } ; + + // register a4l_a4rdResp_fifof_cntr_r + assign a4l_a4rdResp_fifof_cntr_r_D_IN = + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ? + a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 : + MUX_a4l_a4rdResp_fifof_cntr_r_write_1__VAL_2 ; + assign a4l_a4rdResp_fifof_cntr_r_EN = + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr || + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr ; + + // register a4l_a4rdResp_fifof_q_0 + always@(MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1 or + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2 or + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr or a4l_a4rdResp_fifof_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_1: + a4l_a4rdResp_fifof_q_0_D_IN = + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4rdResp_fifof_q_0_write_1__SEL_2: + a4l_a4rdResp_fifof_q_0_D_IN = + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr: + a4l_a4rdResp_fifof_q_0_D_IN = a4l_a4rdResp_fifof_q_1; + default: a4l_a4rdResp_fifof_q_0_D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4rdResp_fifof_q_0_EN = + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr && + a4l_a4rdResp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo7 || + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ; + + // register a4l_a4rdResp_fifof_q_1 + always@(MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1 or + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1 or + MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2 or + MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_1: + a4l_a4rdResp_fifof_q_1_D_IN = + MUX_a4l_a4rdResp_fifof_q_0_write_1__VAL_1; + MUX_a4l_a4rdResp_fifof_q_1_write_1__SEL_2: + a4l_a4rdResp_fifof_q_1_D_IN = + MUX_a4l_a4rdResp_fifof_q_1_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr: + a4l_a4rdResp_fifof_q_1_D_IN = 34'd0; + default: a4l_a4rdResp_fifof_q_1_D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign a4l_a4rdResp_fifof_q_1_EN = + WILL_FIRE_RL_a4l_a4rdResp_fifof_incCtr && + a4l_a4rdResp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_a4l_a4rdResp_fifof_both && _dfoo5 || + WILL_FIRE_RL_a4l_a4rdResp_fifof_decCtr ; + + // register a4l_a4wrResp_fifof_cntr_r + assign a4l_a4wrResp_fifof_cntr_r_D_IN = + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ? + a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 : + MUX_a4l_a4wrResp_fifof_cntr_r_write_1__VAL_2 ; + assign a4l_a4wrResp_fifof_cntr_r_EN = + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr || + WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr ; + + // register a4l_a4wrResp_fifof_q_0 + always@(MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1 or + MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2 or + MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2 or + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr or a4l_a4wrResp_fifof_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_1: + a4l_a4wrResp_fifof_q_0_D_IN = 2'd0; + MUX_a4l_a4wrResp_fifof_q_0_write_1__SEL_2: + a4l_a4wrResp_fifof_q_0_D_IN = + MUX_a4l_a4wrResp_fifof_q_0_write_1__VAL_2; + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr: + a4l_a4wrResp_fifof_q_0_D_IN = a4l_a4wrResp_fifof_q_1; + default: a4l_a4wrResp_fifof_q_0_D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign a4l_a4wrResp_fifof_q_0_EN = + WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr && + a4l_a4wrResp_fifof_cntr_r == 2'd0 || + WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo3 || + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ; + + // register a4l_a4wrResp_fifof_q_1 + assign a4l_a4wrResp_fifof_q_1_D_IN = 2'd0 ; + assign a4l_a4wrResp_fifof_q_1_EN = + WILL_FIRE_RL_a4l_a4wrResp_fifof_incCtr && + a4l_a4wrResp_fifof_cntr_r == 2'd1 || + WILL_FIRE_RL_a4l_a4wrResp_fifof_both && _dfoo1 || + WILL_FIRE_RL_a4l_a4wrResp_fifof_decCtr ; + + // register r0 + assign r0_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ; + assign r0_EN = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h0 ; + + // register r4 + assign r4_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ; + assign r4_EN = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h04 ; + + // register r8 + assign r8_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ; + assign r8_EN = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h08 ; + + // register rC + assign rC_D_IN = a4l_a4wrData_fifof_D_OUT[31:0] ; + assign rC_EN = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h0C ; + + // register uartInited + assign uartInited_D_IN = 1'd1 ; + assign uartInited_EN = WILL_FIRE_RL_init_uart_text && uartTxtP == 6'd43 ; + + // register uartTxtP + assign uartTxtP_D_IN = uartTxtP + 6'd1 ; + assign uartTxtP_EN = WILL_FIRE_RL_init_uart_text ; + + // submodule a4l_a4rdAddr_fifof + assign a4l_a4rdAddr_fifof_D_IN = a4l_a4rdAddr_data_wire_wget ; + assign a4l_a4rdAddr_fifof_ENQ = a4l_a4rdAddr_fifof_FULL_N && s_axi_ARVALID ; + assign a4l_a4rdAddr_fifof_DEQ = WILL_FIRE_RL_a4l_cfrd ; + assign a4l_a4rdAddr_fifof_CLR = 1'b0 ; + + // submodule a4l_a4wrAddr_fifof + assign a4l_a4wrAddr_fifof_D_IN = a4l_a4wrAddr_data_wire_wget ; + assign a4l_a4wrAddr_fifof_ENQ = a4l_a4wrAddr_fifof_FULL_N && s_axi_AWVALID ; + assign a4l_a4wrAddr_fifof_DEQ = WILL_FIRE_RL_a4l_cfwr ; + assign a4l_a4wrAddr_fifof_CLR = 1'b0 ; + + // submodule a4l_a4wrData_fifof + assign a4l_a4wrData_fifof_D_IN = a4l_a4wrData_data_wire_wget ; + assign a4l_a4wrData_fifof_ENQ = a4l_a4wrData_fifof_FULL_N && s_axi_WVALID ; + assign a4l_a4wrData_fifof_DEQ = WILL_FIRE_RL_a4l_cfwr ; + assign a4l_a4wrData_fifof_CLR = 1'b0 ; + + // submodule bluart + assign bluart_pads_cts_arg = upads_cts_arg ; + assign bluart_pads_rx_arg = upads_rx_arg ; + assign bluart_setClkDiv_put = a4l_a4wrData_fifof_D_OUT[15:0] ; + assign bluart_txChar_put = + MUX_bluart_txChar_put_1__SEL_1 ? + a4l_a4wrData_fifof_D_OUT[7:0] : + MUX_bluart_txChar_put_1__VAL_2 ; + assign bluart_EN_setClkDiv_put = + WILL_FIRE_RL_a4l_cfwr && a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h20 ; + assign bluart_EN_txChar_put = + WILL_FIRE_RL_a4l_cfwr && + a4l_a4wrAddr_fifof_D_OUT[7:0] == 8'h2C || + WILL_FIRE_RL_init_uart_text ; + assign bluart_EN_rxChar_get = + WILL_FIRE_RL_a4l_cfrd && a4l_a4rdAddr_fifof_D_OUT[7:0] == 8'h30 ; + + // remaining internal signals + assign _dfoo1 = + a4l_a4wrResp_fifof_cntr_r != 2'd2 || + a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + a4l_a4wrResp_fifof_cntr_r != 2'd1 || + a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + a4l_a4rdResp_fifof_cntr_r != 2'd2 || + a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 == 2'd1 ; + assign _dfoo7 = + a4l_a4rdResp_fifof_cntr_r != 2'd1 || + a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 == 2'd0 ; + assign a4l_a4rdResp_fifof_cntr_r_2_MINUS_1___d60 = + a4l_a4rdResp_fifof_cntr_r - 2'd1 ; + assign a4l_a4wrResp_fifof_cntr_r_9_MINUS_1___d27 = + a4l_a4wrResp_fifof_cntr_r - 2'd1 ; + assign rdat__h6319 = { 24'd0, bluart_txLevel } ; + assign rdat__h6325 = { 24'd0, bluart_rxLevel } ; + assign v__h6356 = { 24'd0, bluart_rxChar_get } ; + assign x__h3633 = uartTxtP - 6'd2 ; + always@(a4l_a4rdAddr_fifof_D_OUT or + bluart_rxChar_get or + r0 or r4 or r8 or rC or rdat__h6319 or rdat__h6325 or v__h6356) + begin + case (a4l_a4rdAddr_fifof_D_OUT[7:0]) + 8'h0: v__h6235 = r0; + 8'h04: v__h6235 = r4; + 8'h08: v__h6235 = r8; + 8'h0C: v__h6235 = rC; + 8'h10: v__h6235 = 32'hDEADBEEF; + 8'h14: v__h6235 = 32'hBABECAFE; + 8'h18: v__h6235 = 32'hF00DFACE; + 8'h1C: v__h6235 = 32'hFEEDC0DE; + 8'h24: v__h6235 = rdat__h6319; + 8'h28: v__h6235 = rdat__h6325; + 8'h30: v__h6235 = v__h6356; + default: v__h6235 = { 24'd0, bluart_rxChar_get }; + endcase + end + always@(x__h3633) + begin + case (x__h3633) + 6'd0, 6'd5, 6'd15: put__h3589 = 8'd65; + 6'd1: put__h3589 = 8'd88; + 6'd2: put__h3589 = 8'd66; + 6'd3, 6'd28, 6'd29: put__h3589 = 8'd76; + 6'd4: put__h3589 = 8'd85; + 6'd6, 6'd22: put__h3589 = 8'd82; + 6'd7: put__h3589 = 8'd84; + 6'd8: put__h3589 = 8'd46; + 6'd9: put__h3589 = 8'd98; + 6'd10, 6'd26: put__h3589 = 8'd115; + 6'd11: put__h3589 = 8'd118; + 6'd12, 6'd14, 6'd21, 6'd27, 6'd31, 6'd35: put__h3589 = 8'd32; + 6'd13: put__h3589 = 8'd45; + 6'd16: put__h3589 = 8'd116; + 6'd17: put__h3589 = 8'd111; + 6'd18: put__h3589 = 8'd109; + 6'd19: put__h3589 = 8'd105; + 6'd20, 6'd33: put__h3589 = 8'd99; + 6'd23: put__h3589 = 8'd117; + 6'd24: put__h3589 = 8'd108; + 6'd25: put__h3589 = 8'd101; + 6'd30: put__h3589 = 8'd67; + 6'd32: put__h3589 = 8'd40; + 6'd34: put__h3589 = 8'd41; + 6'd36: put__h3589 = 8'd50; + 6'd37: put__h3589 = 8'd48; + 6'd38: put__h3589 = 8'd49; + 6'd39: put__h3589 = 8'd52; + default: put__h3589 = 8'b10101010 /* unspecified value */ ; + endcase + end + + // handling of inlined registers + + always@(posedge s_axi_aclk) + begin + if (s_axi_aresetn == `BSV_RESET_VALUE) + begin + a4l_a4rdResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4rdResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 34'd0; + a4l_a4rdResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 34'd0; + a4l_a4wrResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4wrResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY 2'd0; + a4l_a4wrResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + r0 <= `BSV_ASSIGNMENT_DELAY 32'd0; + r4 <= `BSV_ASSIGNMENT_DELAY 32'd0; + r8 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rC <= `BSV_ASSIGNMENT_DELAY 32'd0; + uartInited <= `BSV_ASSIGNMENT_DELAY 1'd0; + uartTxtP <= `BSV_ASSIGNMENT_DELAY 6'd0; + end + else + begin + if (a4l_a4rdResp_fifof_cntr_r_EN) + a4l_a4rdResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdResp_fifof_cntr_r_D_IN; + if (a4l_a4rdResp_fifof_q_0_EN) + a4l_a4rdResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdResp_fifof_q_0_D_IN; + if (a4l_a4rdResp_fifof_q_1_EN) + a4l_a4rdResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY + a4l_a4rdResp_fifof_q_1_D_IN; + if (a4l_a4wrResp_fifof_cntr_r_EN) + a4l_a4wrResp_fifof_cntr_r <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrResp_fifof_cntr_r_D_IN; + if (a4l_a4wrResp_fifof_q_0_EN) + a4l_a4wrResp_fifof_q_0 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrResp_fifof_q_0_D_IN; + if (a4l_a4wrResp_fifof_q_1_EN) + a4l_a4wrResp_fifof_q_1 <= `BSV_ASSIGNMENT_DELAY + a4l_a4wrResp_fifof_q_1_D_IN; + if (r0_EN) r0 <= `BSV_ASSIGNMENT_DELAY r0_D_IN; + if (r4_EN) r4 <= `BSV_ASSIGNMENT_DELAY r4_D_IN; + if (r8_EN) r8 <= `BSV_ASSIGNMENT_DELAY r8_D_IN; + if (rC_EN) rC <= `BSV_ASSIGNMENT_DELAY rC_D_IN; + if (uartInited_EN) + uartInited <= `BSV_ASSIGNMENT_DELAY uartInited_D_IN; + if (uartTxtP_EN) uartTxtP <= `BSV_ASSIGNMENT_DELAY uartTxtP_D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + a4l_a4rdResp_fifof_cntr_r = 2'h2; + a4l_a4rdResp_fifof_q_0 = 34'h2AAAAAAAA; + a4l_a4rdResp_fifof_q_1 = 34'h2AAAAAAAA; + a4l_a4wrResp_fifof_cntr_r = 2'h2; + a4l_a4wrResp_fifof_q_0 = 2'h2; + a4l_a4wrResp_fifof_q_1 = 2'h2; + r0 = 32'hAAAAAAAA; + r4 = 32'hAAAAAAAA; + r8 = 32'hAAAAAAAA; + rC = 32'hAAAAAAAA; + uartInited = 1'h0; + uartTxtP = 6'h2A; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge s_axi_aclk) + begin + #0; + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfrd) + begin + v__h6550 = $time; + #0; + end + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfrd) + $display("[%0d]: %m: AXI4-LITE CONFIG READ Addr:%0x", + v__h6550, + a4l_a4rdAddr_fifof_D_OUT[31:0]); + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfrd) + begin + v__h6582 = $time; + #0; + end + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfrd) + $display("[%0d]: %m: AXI4-LITE CONFIG READ RESPOSNE Data:%0x", + v__h6582, + v__h6235); + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfwr) + begin + v__h6161 = $time; + #0; + end + if (s_axi_aresetn != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_a4l_cfwr) + $display("[%0d]: %m: AXI4-LITE CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h6161, + a4l_a4wrAddr_fifof_D_OUT[31:0], + a4l_a4wrData_fifof_D_OUT[35:32], + a4l_a4wrData_fifof_D_OUT[31:0]); + end + // synopsys translate_on +endmodule // mkAXBLUART + diff --git a/rtl/mkBLUART.v b/rtl/mkBLUART.v index c33888a2..e0079198 100644 --- a/rtl/mkBLUART.v +++ b/rtl/mkBLUART.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:31 EST 2014 +// On Mon Feb 3 15:00:05 EST 2014 // // // Ports: diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index b4ce2886..8b848e02 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:17 EST 2014 +// On Mon Feb 3 15:04:56 EST 2014 // // // Ports: @@ -512,7 +512,6 @@ module mkBiasWorker16B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, - WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -537,12 +536,13 @@ module mkBiasWorker16B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, + MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__SEL_2, - MUX_wci_wslv_illegalEdge_write_1__VAL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -565,8 +565,7 @@ module mkBiasWorker16B(wciS0_Clk, rdat__h11601, rdat__h11609; wire [15 : 0] x__h11463; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, - wsiM_reqFifo_cntr_r_37_MINUS_1___d247; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -647,13 +646,6 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; - // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -736,11 +728,14 @@ module mkBiasWorker16B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; + assign MUX_biasValue_write_1__SEL_2 = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -774,7 +769,7 @@ module mkBiasWorker16B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -810,6 +805,7 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h11369 } ; + assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -843,7 +839,7 @@ module mkBiasWorker16B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -933,7 +929,7 @@ module mkBiasWorker16B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register controlReg assign controlReg_D_IN = @@ -942,7 +938,7 @@ module mkBiasWorker16B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -965,11 +961,11 @@ module mkBiasWorker16B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; assign wci_wslv_illegalEdge_EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1116,7 +1112,7 @@ module mkBiasWorker16B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1307,10 +1303,10 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; assign rdat__h11459 = hasDebugLogic ? { 16'd0, x__h11463 } : 32'd0 ; assign rdat__h11559 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h11573 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1320,7 +1316,6 @@ module mkBiasWorker16B(wciS0_Clk, assign rdat__h11609 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; - assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h11463 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[151:120] + biasValue, @@ -1575,10 +1570,10 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1641,7 +1636,7 @@ module mkBiasWorker16B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1653,7 +1648,7 @@ module mkBiasWorker16B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index 358c993d..000be995 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:20 EST 2014 +// On Mon Feb 3 15:04:59 EST 2014 // // // Ports: @@ -512,7 +512,6 @@ module mkBiasWorker32B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, - WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -537,12 +536,13 @@ module mkBiasWorker32B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, + MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__SEL_2, - MUX_wci_wslv_illegalEdge_write_1__VAL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -565,8 +565,7 @@ module mkBiasWorker32B(wciS0_Clk, rdat__h12397, rdat__h12405; wire [15 : 0] x__h12259; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, - wsiM_reqFifo_cntr_r_37_MINUS_1___d247; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -647,13 +646,6 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; - // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -736,11 +728,14 @@ module mkBiasWorker32B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; + assign MUX_biasValue_write_1__SEL_2 = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -774,7 +769,7 @@ module mkBiasWorker32B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -810,6 +805,7 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h12165 } ; + assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -843,7 +839,7 @@ module mkBiasWorker32B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -933,7 +929,7 @@ module mkBiasWorker32B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register controlReg assign controlReg_D_IN = @@ -942,7 +938,7 @@ module mkBiasWorker32B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -965,11 +961,11 @@ module mkBiasWorker32B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; assign wci_wslv_illegalEdge_EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1116,7 +1112,7 @@ module mkBiasWorker32B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1307,10 +1303,10 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; assign rdat__h12255 = hasDebugLogic ? { 16'd0, x__h12259 } : 32'd0 ; assign rdat__h12355 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h12369 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1320,7 +1316,6 @@ module mkBiasWorker32B(wciS0_Clk, assign rdat__h12405 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; - assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h12259 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[295:264] + biasValue, @@ -1581,10 +1576,10 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1647,7 +1642,7 @@ module mkBiasWorker32B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1659,7 +1654,7 @@ module mkBiasWorker32B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index 3d0eb245..5ba55f32 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:18 EST 2014 +// On Mon Feb 3 15:04:57 EST 2014 // // // Ports: @@ -511,7 +511,6 @@ module mkBiasWorker4B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, - WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -536,12 +535,13 @@ module mkBiasWorker4B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, + MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__SEL_2, - MUX_wci_wslv_illegalEdge_write_1__VAL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -564,8 +564,7 @@ module mkBiasWorker4B(wciS0_Clk, rdat__h11011, x_data__h10099; wire [15 : 0] x__h10865; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, - wsiM_reqFifo_cntr_r_37_MINUS_1___d247; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -646,13 +645,6 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; - // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -735,11 +727,14 @@ module mkBiasWorker4B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; + assign MUX_biasValue_write_1__SEL_2 = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -773,7 +768,7 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -809,6 +804,7 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h10771 } ; + assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -842,7 +838,7 @@ module mkBiasWorker4B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -932,7 +928,7 @@ module mkBiasWorker4B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register controlReg assign controlReg_D_IN = @@ -941,7 +937,7 @@ module mkBiasWorker4B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -964,11 +960,11 @@ module mkBiasWorker4B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; assign wci_wslv_illegalEdge_EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1115,7 +1111,7 @@ module mkBiasWorker4B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1305,10 +1301,10 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; assign rdat__h10861 = hasDebugLogic ? { 16'd0, x__h10865 } : 32'd0 ; assign rdat__h10961 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h10975 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1318,7 +1314,6 @@ module mkBiasWorker4B(wciS0_Clk, assign rdat__h11011 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; - assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h10865 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = wsiS_reqFifo_D_OUT[43:12] + biasValue ; always@(wci_wslv_reqF_D_OUT or @@ -1567,10 +1562,10 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1633,7 +1628,7 @@ module mkBiasWorker4B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1645,7 +1640,7 @@ module mkBiasWorker4B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index b419efb4..192dc51d 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:19 EST 2014 +// On Mon Feb 3 15:04:58 EST 2014 // // // Ports: @@ -510,7 +510,6 @@ module mkBiasWorker8B(wciS0_Clk, // rule scheduling signals wire WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, - WILL_FIRE_RL_wci_ctrl_EiI, WILL_FIRE_RL_wci_ctrl_IsO, WILL_FIRE_RL_wci_ctrl_OrE, WILL_FIRE_RL_wci_wslv_ctl_op_complete, @@ -535,12 +534,13 @@ module mkBiasWorker8B(wciS0_Clk, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1, MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2; wire MUX_biasValue_write_1__SEL_1, + MUX_biasValue_write_1__SEL_2, MUX_controlReg_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__SEL_2, - MUX_wci_wslv_illegalEdge_write_1__VAL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -563,8 +563,7 @@ module mkBiasWorker8B(wciS0_Clk, rdat__h11203, rdat__h11211; wire [15 : 0] x__h11065; - wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, - wsiM_reqFifo_cntr_r_37_MINUS_1___d247; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp @@ -645,13 +644,6 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw_whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; - // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -734,11 +726,14 @@ module mkBiasWorker8B(wciS0_Clk, // inputs to muxes for submodule ports assign MUX_biasValue_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ; + assign MUX_biasValue_write_1__SEL_2 = + wci_wslv_wci_ctrl_pw_whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF_D_OUT[36:34] == 3'd0 ; assign MUX_controlReg_write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -772,7 +767,7 @@ module mkBiasWorker8B(wciS0_Clk, assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 = wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -808,6 +803,7 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h10971 } ; + assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 = (wsiM_reqFifo_cntr_r == 2'd1) ? @@ -841,7 +837,7 @@ module mkBiasWorker8B(wciS0_Clk, assign wci_wslv_ctlAckReg_1_wget = 1'd1 ; assign wci_wslv_ctlAckReg_1_whas = WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ; assign wci_wci_Es_mCmd_w_whas = 1'd1 ; assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ; @@ -931,7 +927,7 @@ module mkBiasWorker8B(wciS0_Clk, 32'd0 ; assign biasValue_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register controlReg assign controlReg_D_IN = @@ -940,7 +936,7 @@ module mkBiasWorker8B(wciS0_Clk, 32'd0 ; assign controlReg_EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 || - WILL_FIRE_RL_wci_ctrl_EiI ; + MUX_biasValue_write_1__SEL_2 ; // register wci_wslv_cEdge assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ; @@ -963,11 +959,11 @@ module mkBiasWorker8B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; assign wci_wslv_illegalEdge_EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1114,7 +1110,7 @@ module mkBiasWorker8B(wciS0_Clk, // register wsiM_reqFifo_cntr_r assign wsiM_reqFifo_cntr_r_D_IN = WILL_FIRE_RL_wsiM_reqFifo_decCtr ? - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 : + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 : MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ; assign wsiM_reqFifo_cntr_r_EN = WILL_FIRE_RL_wsiM_reqFifo_decCtr || @@ -1304,10 +1300,10 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dfoo5 = wsiM_reqFifo_cntr_r != 2'd2 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd1 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ; assign _dfoo7 = wsiM_reqFifo_cntr_r != 2'd1 || - wsiM_reqFifo_cntr_r_37_MINUS_1___d247 == 2'd0 ; + MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ; assign rdat__h11061 = hasDebugLogic ? { 16'd0, x__h11065 } : 32'd0 ; assign rdat__h11161 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ; assign rdat__h11175 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ; @@ -1317,7 +1313,6 @@ module mkBiasWorker8B(wciS0_Clk, assign rdat__h11211 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; - assign wsiM_reqFifo_cntr_r_37_MINUS_1___d247 = wsiM_reqFifo_cntr_r - 2'd1 ; assign x__h11065 = { wsiS_statusR, wsiM_statusR } ; assign x_data__h10099 = { wsiS_reqFifo_D_OUT[79:48] + biasValue, @@ -1570,10 +1565,10 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1636,7 +1631,7 @@ module mkBiasWorker8B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) @@ -1648,7 +1643,7 @@ module mkBiasWorker8B(wciS0_Clk, if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end // synopsys translate_on diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v index 56a0e9f4..98e8e131 100644 --- a/rtl/mkCTop16B.v +++ b/rtl/mkCTop16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:34:10 EST 2014 +// On Mon Feb 3 15:31:29 EST 2014 // // // Ports: diff --git a/rtl/mkDramServer_v6.v b/rtl/mkDramServer_v6.v index 953ca5a2..7cc6bdb7 100644 --- a/rtl/mkDramServer_v6.v +++ b/rtl/mkDramServer_v6.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:03 EST 2014 +// On Mon Feb 3 15:05:16 EST 2014 // // // Ports: @@ -824,7 +824,6 @@ module mkDramServer_v6(CLK_sys0_clk, // rule scheduling signals wire WILL_FIRE_RL_advance_response, - WILL_FIRE_RL_getRequest, WILL_FIRE_RL_memc_advance_readData, WILL_FIRE_RL_memc_advance_request, WILL_FIRE_RL_memc_advance_write0, @@ -850,7 +849,7 @@ module mkDramServer_v6(CLK_sys0_clk, MUX_lreqF_enq_1__VAL_3; wire [130 : 0] MUX_wmemi_respF_q_0_write_1__VAL_1, MUX_wmemi_respF_q_0_write_1__VAL_2, - MUX_wmemi_respF_q_1_write_1__VAL_2; + MUX_wmemi_respF_q_1_write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, @@ -859,7 +858,7 @@ module mkDramServer_v6(CLK_sys0_clk, wire [7 : 0] MUX_wmemiReadInFlight_value_write_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, MUX_wmemi_respF_cntr_r_write_1__VAL_2; - wire MUX_lreqF_enq_1__SEL_1, + wire MUX_lreqF_enq_1__PSEL_2, MUX_lreqF_enq_1__SEL_2, MUX_lreqF_enq_1__SEL_3, MUX_memc_firstBeat_write_1__SEL_1, @@ -869,9 +868,9 @@ module mkDramServer_v6(CLK_sys0_clk, MUX_rdReg_2_write_1__SEL_1, MUX_rdReg_3_write_1__SEL_1, MUX_splitReadInFlight_write_1__SEL_1, + MUX_splitReadInFlight_write_1__SEL_2, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__SEL_2, - MUX_wci_wslv_illegalEdge_write_1__VAL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -946,6 +945,7 @@ module mkDramServer_v6(CLK_sys0_clk, lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421, wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d464, wmemiReadInFlight_value_07_SLT_16___d390, + wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283, x1__h12825; // value method wciS0_sResp @@ -1307,8 +1307,8 @@ module mkDramServer_v6(CLK_sys0_clk, .DEQ(memc_rdpF_DEQ), .ENQ(memc_rdpF_ENQ), .CLR(memc_rdpF_CLR), - .EMPTY_N(memc_rdpF_EMPTY_N), .D_OUT(memc_rdpF_D_OUT), + .EMPTY_N(memc_rdpF_EMPTY_N), .FULL_N(memc_rdpF_FULL_N)); // submodule memc_reqF @@ -1331,8 +1331,8 @@ module mkDramServer_v6(CLK_sys0_clk, .DEQ(memc_respF_DEQ), .ENQ(memc_respF_ENQ), .CLR(memc_respF_CLR), - .EMPTY_N(memc_respF_EMPTY_N), .D_OUT(memc_respF_D_OUT), + .EMPTY_N(memc_respF_EMPTY_N), .FULL_N(memc_respF_FULL_N)); // submodule memc_rst_stretch_n @@ -1379,8 +1379,8 @@ module mkDramServer_v6(CLK_sys0_clk, .DEQ(splaF_DEQ), .ENQ(splaF_ENQ), .CLR(splaF_CLR), - .EMPTY_N(splaF_EMPTY_N), .D_OUT(splaF_D_OUT), + .EMPTY_N(splaF_EMPTY_N), .FULL_N(splaF_FULL_N)); // submodule wci_uclkUpdateCnt @@ -1520,13 +1520,6 @@ module mkDramServer_v6(CLK_sys0_clk, wmemi_respF_enqueueing_whas && wmemi_respF_cntr_r != 2'd0 && wmemi_respF_enqueueing_whas ; - // rule RL_getRequest - assign WILL_FIRE_RL_getRequest = - wmemi_operateD && wmemi_peerIsReady && wmemi_reqF_EMPTY_N && - IF_wmemi_reqF_first__84_BITS_51_TO_49_85_EQ_1__ETC___d393 && - !wci_wslv_wci_cfwr_pw_whas && - !wci_wslv_wci_cfrd_pw_whas ; - // rule RL_wci_ctrl_IsO assign WILL_FIRE_RL_wci_ctrl_IsO = wci_wslv_wci_ctrl_pw_whas && @@ -1555,10 +1548,13 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_respF_enqueueing_whas ; // inputs to muxes for submodule ports - assign MUX_lreqF_enq_1__SEL_1 = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ; + assign MUX_lreqF_enq_1__PSEL_2 = + wmemi_operateD && wmemi_peerIsReady && wmemi_reqF_EMPTY_N && + IF_wmemi_reqF_first__84_BITS_51_TO_49_85_EQ_1__ETC___d393 && + !wci_wslv_wci_cfwr_pw_whas && + !wci_wslv_wci_cfrd_pw_whas ; assign MUX_lreqF_enq_1__SEL_2 = - WILL_FIRE_RL_getRequest && + MUX_lreqF_enq_1__PSEL_2 && (wmemi_reqF_D_OUT[51:49] == 3'd1 || wmemiReadInFlight_value_07_SLT_16___d390) ; assign MUX_lreqF_enq_1__SEL_3 = @@ -1584,9 +1580,9 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_reqF_D_OUT[39:32] == 8'h8C ; assign MUX_splitReadInFlight_write_1__SEL_1 = WILL_FIRE_RL_advance_response && splitReadInFlight ; + assign MUX_splitReadInFlight_write_1__SEL_2 = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -1612,13 +1608,13 @@ module mkDramServer_v6(CLK_sys0_clk, assign MUX_wci_wslv_respF_x_wire_wset_1__SEL_2 = WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF_D_OUT[51] ; assign MUX_wmemi_respF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 ; - assign MUX_wmemi_respF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemi_respF_both && _dfoo7 ; + assign MUX_wmemi_respF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 ; assign MUX_wmemi_respF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 ; - assign MUX_wmemi_respF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemi_respF_both && _dfoo5 ; + assign MUX_wmemi_respF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 ; assign MUX_lreqF_enq_1__VAL_1 = { 1'd1, x1_addr__h17672, @@ -1635,7 +1631,7 @@ module mkDramServer_v6(CLK_sys0_clk, { !wci_wslv_reqF_D_OUT[51] && wci_wslv_reqF_D_OUT[39:32] != 8'h54, IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_pReg__ETC___d503 } ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -1681,14 +1677,14 @@ module mkDramServer_v6(CLK_sys0_clk, (wmemiReadInFlight_acc_v1_whas ? 8'd1 : 8'd0) + (wmemi_respF_enqueueing_whas ? 8'd255 : 8'd0) ; assign MUX_wmemi_respF_cntr_r_write_1__VAL_2 = wmemi_respF_cntr_r + 2'd1 ; - assign MUX_wmemi_respF_q_0_write_1__VAL_1 = { 3'd3, lrespF_dD_OUT } ; - assign MUX_wmemi_respF_q_0_write_1__VAL_2 = + assign MUX_wmemi_respF_q_0_write_1__VAL_1 = (wmemi_respF_cntr_r == 2'd1) ? - MUX_wmemi_respF_q_0_write_1__VAL_1 : + MUX_wmemi_respF_q_0_write_1__VAL_2 : wmemi_respF_q_1 ; - assign MUX_wmemi_respF_q_1_write_1__VAL_2 = + assign MUX_wmemi_respF_q_0_write_1__VAL_2 = { 3'd3, lrespF_dD_OUT } ; + assign MUX_wmemi_respF_q_1_write_1__VAL_1 = (wmemi_respF_cntr_r == 2'd2) ? - MUX_wmemi_respF_q_0_write_1__VAL_1 : + MUX_wmemi_respF_q_0_write_1__VAL_2 : 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; // inlined wires @@ -1743,15 +1739,14 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemi_wmemiDh_whas = 1'd1 ; assign wmemi_cmdAccept_w_wget = 1'd1 ; assign wmemi_cmdAccept_w_whas = - wmemi_reqF_FULL_N && wmemi_operateD && wmemi_peerIsReady && - wmemi_wmemiReq_wget[51:49] != 3'd0 && - wmemi_reqF_FULL_N ; + wmemi_reqF_FULL_N && + wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 ; assign wmemi_dhAccept_w_wget = 1'd1 ; assign wmemi_dhAccept_w_whas = wmemi_dhF_FULL_N && wmemi_operateD && wmemi_peerIsReady && wmemi_wmemiDh_wget[145] && wmemi_dhF_FULL_N ; - assign wmemi_respF_x_wire_wget = MUX_wmemi_respF_q_0_write_1__VAL_1 ; + assign wmemi_respF_x_wire_wget = MUX_wmemi_respF_q_0_write_1__VAL_2 ; assign wmemi_respF_x_wire_whas = wmemi_respF_enqueueing_whas ; assign wmemi_operateD_1_wget = 1'd1 ; assign wmemi_operateD_1_whas = wci_wslv_cState == 3'd2 ; @@ -1761,7 +1756,7 @@ module mkDramServer_v6(CLK_sys0_clk, assign memInReset_1_whas = 1'd1 ; assign wmemiReadInFlight_acc_v1_wget = 8'd1 ; assign wmemiReadInFlight_acc_v1_whas = - WILL_FIRE_RL_getRequest && wmemi_reqF_D_OUT[51:49] != 3'd1 && + MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] != 3'd1 && wmemiReadInFlight_value_07_SLT_16___d390 ; assign wmemiReadInFlight_acc_v2_wget = 8'd255 ; assign wmemiReadInFlight_acc_v2_whas = wmemi_respF_enqueueing_whas ; @@ -1938,11 +1933,11 @@ module mkDramServer_v6(CLK_sys0_clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; assign wci_wslv_illegalEdge_EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge_write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -2068,11 +2063,16 @@ module mkDramServer_v6(CLK_sys0_clk, // register wmemiRdReq assign wmemiRdReq_D_IN = wmemiRdReq + 32'd1 ; - assign wmemiRdReq_EN = wmemiReadInFlight_acc_v1_whas ; + assign wmemiRdReq_EN = + MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] != 3'd1 && + wmemiReadInFlight_value_07_SLT_16___d390 ; // register wmemiRdResp assign wmemiRdResp_D_IN = wmemiRdResp + 32'd1 ; - assign wmemiRdResp_EN = wmemi_respF_enqueueing_whas ; + assign wmemiRdResp_EN = + lrespF_dEMPTY_N && + lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421 && + (wmemiReadInFlight_value ^ 8'h80) > 8'd128 ; // register wmemiReadInFlight_value assign wmemiReadInFlight_value_D_IN = @@ -2084,7 +2084,7 @@ module mkDramServer_v6(CLK_sys0_clk, // register wmemiWrReq assign wmemiWrReq_D_IN = wmemiWrReq + 32'd1 ; assign wmemiWrReq_EN = - WILL_FIRE_RL_getRequest && wmemi_reqF_D_OUT[51:49] == 3'd1 ; + MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] == 3'd1 ; // register wmemi_errorSticky assign wmemi_errorSticky_D_IN = 1'b0 ; @@ -2129,22 +2129,22 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wmemi_respF_q_0_EN = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemi_respF_both && _dfoo7 || + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemi_respF_decCtr ; // register wmemi_respF_q_1 always@(MUX_wmemi_respF_q_1_write_1__SEL_1 or - MUX_wmemi_respF_q_0_write_1__VAL_1 or + MUX_wmemi_respF_q_1_write_1__VAL_1 or MUX_wmemi_respF_q_1_write_1__SEL_2 or - MUX_wmemi_respF_q_1_write_1__VAL_2 or + MUX_wmemi_respF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemi_respF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemi_respF_q_1_write_1__SEL_1: - wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_0_write_1__VAL_1; + wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_1_write_1__VAL_1; MUX_wmemi_respF_q_1_write_1__SEL_2: - wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_1_write_1__VAL_2; + wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmemi_respF_decCtr: wmemi_respF_q_1_D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: wmemi_respF_q_1_D_IN = @@ -2152,8 +2152,8 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wmemi_respF_q_1_EN = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemi_respF_both && _dfoo5 || + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemi_respF_decCtr ; // register wmemi_statusR @@ -2168,7 +2168,9 @@ module mkDramServer_v6(CLK_sys0_clk, // register wmemi_trafficSticky assign wmemi_trafficSticky_D_IN = 1'd1 ; - assign wmemi_trafficSticky_EN = wmemi_cmdAccept_w_whas ; + assign wmemi_trafficSticky_EN = + wmemi_reqF_FULL_N && + wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 ; // submodule appFull assign appFull_sD_IN = x1__h12825 ; @@ -2280,14 +2282,15 @@ module mkDramServer_v6(CLK_sys0_clk, assign initComplete_sEN = 1'd1 ; // submodule lreqF - always@(MUX_lreqF_enq_1__SEL_1 or + always@(MUX_splitReadInFlight_write_1__SEL_2 or MUX_lreqF_enq_1__VAL_1 or MUX_lreqF_enq_1__SEL_2 or MUX_lreqF_enq_1__VAL_2 or MUX_lreqF_enq_1__SEL_3 or MUX_lreqF_enq_1__VAL_3) begin case (1'b1) // synopsys parallel_case - MUX_lreqF_enq_1__SEL_1: lreqF_sD_IN = MUX_lreqF_enq_1__VAL_1; + MUX_splitReadInFlight_write_1__SEL_2: + lreqF_sD_IN = MUX_lreqF_enq_1__VAL_1; MUX_lreqF_enq_1__SEL_2: lreqF_sD_IN = MUX_lreqF_enq_1__VAL_2; MUX_lreqF_enq_1__SEL_3: lreqF_sD_IN = MUX_lreqF_enq_1__VAL_3; default: lreqF_sD_IN = @@ -2296,7 +2299,7 @@ module mkDramServer_v6(CLK_sys0_clk, end assign lreqF_sENQ = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] || - WILL_FIRE_RL_getRequest && + MUX_lreqF_enq_1__PSEL_2 && (wmemi_reqF_D_OUT[51:49] == 3'd1 || wmemiReadInFlight_value_07_SLT_16___d390) || WILL_FIRE_RL_wci_cfwr && @@ -2390,7 +2393,7 @@ module mkDramServer_v6(CLK_sys0_clk, // submodule splaF assign splaF_D_IN = wci_wslv_reqF_D_OUT[35:34] ; assign splaF_DEQ = MUX_splitReadInFlight_write_1__SEL_1 ; - assign splaF_ENQ = MUX_lreqF_enq_1__SEL_1 ; + assign splaF_ENQ = MUX_splitReadInFlight_write_1__SEL_2 ; assign splaF_CLR = 1'b0 ; // submodule wci_uclkUpdateCnt @@ -2411,13 +2414,13 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemi_dhF_D_IN = wmemi_wmemiDh_wget ; assign wmemi_dhF_ENQ = wmemi_dhAccept_w_whas ; assign wmemi_dhF_DEQ = - WILL_FIRE_RL_getRequest && wmemi_reqF_D_OUT[51:49] == 3'd1 ; + MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] == 3'd1 ; assign wmemi_dhF_CLR = 1'b0 ; // submodule wmemi_reqF assign wmemi_reqF_D_IN = wmemi_wmemiReq_wget ; assign wmemi_reqF_ENQ = wmemi_cmdAccept_w_whas ; - assign wmemi_reqF_DEQ = WILL_FIRE_RL_getRequest ; + assign wmemi_reqF_DEQ = MUX_lreqF_enq_1__PSEL_2 ; assign wmemi_reqF_CLR = 1'b0 ; // remaining internal signals @@ -2544,6 +2547,10 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_respF_cntr_r - 2'd1 ; assign wmemiReadInFlight_value_07_SLT_16___d390 = (wmemiReadInFlight_value ^ 8'h80) < 8'd144 ; + assign wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 = + wmemi_operateD && wmemi_peerIsReady && + wmemi_wmemiReq_wget[51:49] != 3'd0 && + wmemi_reqF_FULL_N ; assign wmemi_respF_cntr_r_47_MINUS_1___d256 = wmemi_respF_cntr_r - 2'd1 ; assign x1__h12825 = !memc_memc_app_rdy ; assign x1_addr__h17672 = { pReg[12:0], wci_wslv_reqF_D_OUT[50:36], 4'd0 } ; diff --git a/rtl/mkFMC150.v b/rtl/mkFMC150.v index de8600d4..34eca860 100644 --- a/rtl/mkFMC150.v +++ b/rtl/mkFMC150.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:13 EST 2014 +// On Mon Feb 3 15:05:19 EST 2014 // // // Ports: diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v index 7728cb5b..6383984c 100644 --- a/rtl/mkFTop_ml605.v +++ b/rtl/mkFTop_ml605.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Jan 27 11:02:54 EST 2014 +// On Mon Feb 3 15:31:34 EST 2014 // // // Ports: @@ -528,9 +528,23 @@ module mkFTop_ml605(sys0_clkp, // inlined wires wire [63 : 0] pciw_pci0_wTrnTxDat_wget; + wire [31 : 0] a4lm_rdData_w_wget; wire [7 : 0] pciw_pcie_irq_wInterruptDo_wget; - wire [1 : 0] infLed_wget; - wire blinkLed_wget, + wire [1 : 0] a4lm_rdResp_w_wget, a4lm_wrResp_w_wget, infLed_wget; + wire a4lm_rdAddrRdy_w_wget, + a4lm_rdAddrRdy_w_whas, + a4lm_rdData_w_whas, + a4lm_rdRespVal_w_wget, + a4lm_rdRespVal_w_whas, + a4lm_rdResp_w_whas, + a4lm_wrAddrRdy_w_wget, + a4lm_wrAddrRdy_w_whas, + a4lm_wrDataRdy_w_wget, + a4lm_wrDataRdy_w_whas, + a4lm_wrRespVal_w_wget, + a4lm_wrRespVal_w_whas, + a4lm_wrResp_w_whas, + blinkLed_wget, pciw_i2pAF_dClear_pw_whas, pciw_i2pAF_deq_happened_whas, pciw_i2pAF_deq_pw_whas, @@ -648,6 +662,29 @@ module mkFTop_ml605(sys0_clkp, reg pciw_pcie_irq_rMSIEnabled; wire pciw_pcie_irq_rMSIEnabled_D_IN, pciw_pcie_irq_rMSIEnabled_EN; + // ports of submodule axbluart + wire [31 : 0] axbluart_s_axi_ARADDR, + axbluart_s_axi_AWADDR, + axbluart_s_axi_RDATA, + axbluart_s_axi_WDATA; + wire [3 : 0] axbluart_s_axi_WSTRB; + wire [2 : 0] axbluart_s_axi_ARPROT, axbluart_s_axi_AWPROT; + wire [1 : 0] axbluart_s_axi_BRESP, axbluart_s_axi_RRESP; + wire axbluart_s_axi_ARREADY, + axbluart_s_axi_ARVALID, + axbluart_s_axi_AWREADY, + axbluart_s_axi_AWVALID, + axbluart_s_axi_BREADY, + axbluart_s_axi_BVALID, + axbluart_s_axi_RREADY, + axbluart_s_axi_RVALID, + axbluart_s_axi_WREADY, + axbluart_s_axi_WVALID, + axbluart_upads_cts_arg, + axbluart_upads_rts, + axbluart_upads_rx_arg, + axbluart_upads_tx; + // ports of submodule cap0 wire [63 : 0] cap0_wtiS0_MData; wire [31 : 0] cap0_wciS0_MAddr, @@ -737,10 +774,6 @@ module mkFTop_ml605(sys0_clkp, ctop_RST_N_wci_m_4, ctop_gps_ppsSyncIn_x, ctop_gps_ppsSyncOut, - ctop_upads_cts_arg, - ctop_upads_rts, - ctop_upads_rx_arg, - ctop_upads_tx, ctop_wci_m_0_MAddrSpace, ctop_wci_m_0_SThreadBusy, ctop_wci_m_1_MAddrSpace, @@ -1053,6 +1086,47 @@ module mkFTop_ml605(sys0_clkp, tcGbe0_wti_m_SReset_n, tcGbe0_wti_m_SThreadBusy; + // ports of submodule wmemiTap + wire [127 : 0] wmemiTap_wmemiM0_MData, + wmemiTap_wmemiM0_SData, + wmemiTap_wmemiS0_MData, + wmemiTap_wmemiS0_SData; + wire [35 : 0] wmemiTap_axiM0_wrData_data, + wmemiTap_wmemiM0_MAddr, + wmemiTap_wmemiS0_MAddr; + wire [34 : 0] wmemiTap_axiM0_rdAddr_data, wmemiTap_axiM0_wrAddr_data; + wire [33 : 0] wmemiTap_axiM0_rdResp_data_value; + wire [15 : 0] wmemiTap_wmemiM0_MDataByteEn, wmemiTap_wmemiS0_MDataByteEn; + wire [11 : 0] wmemiTap_wmemiM0_MBurstLength, wmemiTap_wmemiS0_MBurstLength; + wire [2 : 0] wmemiTap_wmemiM0_MCmd, wmemiTap_wmemiS0_MCmd; + wire [1 : 0] wmemiTap_axiM0_wrResp_data_value, + wmemiTap_wmemiM0_SResp, + wmemiTap_wmemiS0_SResp; + wire wmemiTap_axiM0_rdAddr_ready_value, + wmemiTap_axiM0_rdAddr_valid, + wmemiTap_axiM0_rdResp_ready, + wmemiTap_axiM0_rdResp_valid_value, + wmemiTap_axiM0_wrAddr_ready_value, + wmemiTap_axiM0_wrAddr_valid, + wmemiTap_axiM0_wrData_ready_value, + wmemiTap_axiM0_wrData_valid, + wmemiTap_axiM0_wrResp_ready, + wmemiTap_axiM0_wrResp_valid_value, + wmemiTap_wmemiM0_MDataLast, + wmemiTap_wmemiM0_MDataValid, + wmemiTap_wmemiM0_MReqLast, + wmemiTap_wmemiM0_MReset_n, + wmemiTap_wmemiM0_SCmdAccept, + wmemiTap_wmemiM0_SDataAccept, + wmemiTap_wmemiM0_SRespLast, + wmemiTap_wmemiS0_MDataLast, + wmemiTap_wmemiS0_MDataValid, + wmemiTap_wmemiS0_MReqLast, + wmemiTap_wmemiS0_MReset_n, + wmemiTap_wmemiS0_SCmdAccept, + wmemiTap_wmemiS0_SDataAccept, + wmemiTap_wmemiS0_SRespLast; + // rule scheduling signals wire WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_1_upconv_connect1, WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_1_upconv_connect2, @@ -1075,8 +1149,8 @@ module mkFTop_ml605(sys0_clkp, MUX_pciw_p2iS_write_1__SEL_1; // remaining internal signals - wire [127 : 0] val_data__h6496, wOut_data__h6605; - wire [15 : 0] val_be__h6495, wOut_be__h6604; + wire [127 : 0] val_data__h6497, wOut_data__h6606; + wire [15 : 0] val_be__h6496, wOut_be__h6605; wire pciw_p2iAF_head_wrapped_crossed__4_EQ_pciw_p2i_ETC___d123; // oscillator and gates for output clock p125clk @@ -1233,10 +1307,37 @@ module mkFTop_ml605(sys0_clkp, assign flpDAC_sclkgate = fmc150_padsDAC_sclkgate ; // value method upads_rts - assign upads_rts = ctop_upads_rts ; + assign upads_rts = axbluart_upads_rts ; // value method upads_tx - assign upads_tx = ctop_upads_tx ; + assign upads_tx = axbluart_upads_tx ; + + // submodule axbluart + mkAXBLUART axbluart(.s_axi_aclk(pciw_pci0_pcie_ep_trn2_clk), + .s_axi_aresetn(pciw_p125rst_OUT_RST), + .s_axi_ARADDR(axbluart_s_axi_ARADDR), + .s_axi_ARPROT(axbluart_s_axi_ARPROT), + .s_axi_AWADDR(axbluart_s_axi_AWADDR), + .s_axi_AWPROT(axbluart_s_axi_AWPROT), + .s_axi_WDATA(axbluart_s_axi_WDATA), + .s_axi_WSTRB(axbluart_s_axi_WSTRB), + .upads_cts_arg(axbluart_upads_cts_arg), + .upads_rx_arg(axbluart_upads_rx_arg), + .s_axi_AWVALID(axbluart_s_axi_AWVALID), + .s_axi_WVALID(axbluart_s_axi_WVALID), + .s_axi_BREADY(axbluart_s_axi_BREADY), + .s_axi_ARVALID(axbluart_s_axi_ARVALID), + .s_axi_RREADY(axbluart_s_axi_RREADY), + .s_axi_AWREADY(axbluart_s_axi_AWREADY), + .s_axi_WREADY(axbluart_s_axi_WREADY), + .s_axi_BVALID(axbluart_s_axi_BVALID), + .s_axi_BRESP(axbluart_s_axi_BRESP), + .s_axi_ARREADY(axbluart_s_axi_ARREADY), + .s_axi_RVALID(axbluart_s_axi_RVALID), + .s_axi_RDATA(axbluart_s_axi_RDATA), + .s_axi_RRESP(axbluart_s_axi_RRESP), + .upads_rts(axbluart_upads_rts), + .upads_tx(axbluart_upads_tx)); // submodule cap0 mkWSICaptureWorker4B #(.hasDebugLogic(1'd1)) cap0(.wciS0_Clk(pciw_pci0_pcie_ep_trn2_clk), @@ -1276,8 +1377,6 @@ module mkFTop_ml605(sys0_clkp, .gps_ppsSyncIn_x(ctop_gps_ppsSyncIn_x), .server_request_put(ctop_server_request_put), .switch_x(ctop_switch_x), - .upads_cts_arg(ctop_upads_cts_arg), - .upads_rx_arg(ctop_upads_rx_arg), .wci_m_0_SData(ctop_wci_m_0_SData), .wci_m_0_SFlag(ctop_wci_m_0_SFlag), .wci_m_0_SResp(ctop_wci_m_0_SResp), @@ -1376,8 +1475,6 @@ module mkFTop_ml605(sys0_clkp, .wmemiM0_MDataByteEn(ctop_wmemiM0_MDataByteEn), .wmemiM0_MReset_n(ctop_wmemiM0_MReset_n), .gps_ppsSyncOut(ctop_gps_ppsSyncOut), - .upads_rts(ctop_upads_rts), - .upads_tx(ctop_upads_tx), .RST_N_wci_m_0(ctop_RST_N_wci_m_0), .RST_N_wci_m_1(ctop_RST_N_wci_m_1), .RST_N_wci_m_2(ctop_RST_N_wci_m_2), @@ -1827,6 +1924,53 @@ module mkFTop_ml605(sys0_clkp, .RDY_gpsTime(tcGbe0_RDY_gpsTime), .wti_m_req(tcGbe0_wti_m_req)); + // submodule wmemiTap + mkWmemiTap wmemiTap(.CLK(pciw_pci0_pcie_ep_trn2_clk), + .RST_N(pciw_p125rst_OUT_RST), + .axiM0_rdAddr_ready_value(wmemiTap_axiM0_rdAddr_ready_value), + .axiM0_rdResp_data_value(wmemiTap_axiM0_rdResp_data_value), + .axiM0_rdResp_valid_value(wmemiTap_axiM0_rdResp_valid_value), + .axiM0_wrAddr_ready_value(wmemiTap_axiM0_wrAddr_ready_value), + .axiM0_wrData_ready_value(wmemiTap_axiM0_wrData_ready_value), + .axiM0_wrResp_data_value(wmemiTap_axiM0_wrResp_data_value), + .axiM0_wrResp_valid_value(wmemiTap_axiM0_wrResp_valid_value), + .wmemiM0_SData(wmemiTap_wmemiM0_SData), + .wmemiM0_SResp(wmemiTap_wmemiM0_SResp), + .wmemiS0_MAddr(wmemiTap_wmemiS0_MAddr), + .wmemiS0_MBurstLength(wmemiTap_wmemiS0_MBurstLength), + .wmemiS0_MCmd(wmemiTap_wmemiS0_MCmd), + .wmemiS0_MData(wmemiTap_wmemiS0_MData), + .wmemiS0_MDataByteEn(wmemiTap_wmemiS0_MDataByteEn), + .wmemiS0_MReqLast(wmemiTap_wmemiS0_MReqLast), + .wmemiS0_MDataValid(wmemiTap_wmemiS0_MDataValid), + .wmemiS0_MDataLast(wmemiTap_wmemiS0_MDataLast), + .wmemiS0_MReset_n(wmemiTap_wmemiS0_MReset_n), + .wmemiM0_SRespLast(wmemiTap_wmemiM0_SRespLast), + .wmemiM0_SCmdAccept(wmemiTap_wmemiM0_SCmdAccept), + .wmemiM0_SDataAccept(wmemiTap_wmemiM0_SDataAccept), + .wmemiS0_SResp(wmemiTap_wmemiS0_SResp), + .wmemiS0_SRespLast(wmemiTap_wmemiS0_SRespLast), + .wmemiS0_SData(wmemiTap_wmemiS0_SData), + .wmemiS0_SCmdAccept(wmemiTap_wmemiS0_SCmdAccept), + .wmemiS0_SDataAccept(wmemiTap_wmemiS0_SDataAccept), + .wmemiM0_MCmd(wmemiTap_wmemiM0_MCmd), + .wmemiM0_MReqLast(wmemiTap_wmemiM0_MReqLast), + .wmemiM0_MAddr(wmemiTap_wmemiM0_MAddr), + .wmemiM0_MBurstLength(wmemiTap_wmemiM0_MBurstLength), + .wmemiM0_MDataValid(wmemiTap_wmemiM0_MDataValid), + .wmemiM0_MDataLast(wmemiTap_wmemiM0_MDataLast), + .wmemiM0_MData(wmemiTap_wmemiM0_MData), + .wmemiM0_MDataByteEn(wmemiTap_wmemiM0_MDataByteEn), + .wmemiM0_MReset_n(wmemiTap_wmemiM0_MReset_n), + .axiM0_wrAddr_data(wmemiTap_axiM0_wrAddr_data), + .axiM0_wrAddr_valid(wmemiTap_axiM0_wrAddr_valid), + .axiM0_wrData_data(wmemiTap_axiM0_wrData_data), + .axiM0_wrData_valid(wmemiTap_axiM0_wrData_valid), + .axiM0_wrResp_ready(wmemiTap_axiM0_wrResp_ready), + .axiM0_rdAddr_data(wmemiTap_axiM0_rdAddr_data), + .axiM0_rdAddr_valid(wmemiTap_axiM0_rdAddr_valid), + .axiM0_rdResp_ready(wmemiTap_axiM0_rdResp_ready)); + // rule RL_pciw_pcie_irq_msi_enabled_assert_interrupt assign WILL_FIRE_RL_pciw_pcie_irq_msi_enabled_assert_interrupt = pciw_pcie_irq_fifoAssert_dEMPTY_N && pciw_pcie_irq_rMSIEnabled && @@ -1906,13 +2050,13 @@ module mkFTop_ml605(sys0_clkp, pciw_i2pS[150:136], pciw_i2pS[127:64] } ; assign MUX_pciw_p2iS_write_1__VAL_1 = - { pciw_fP2I_D_OUT[80:72], val_be__h6495, val_data__h6496 } ; + { pciw_fP2I_D_OUT[80:72], val_be__h6496, val_data__h6497 } ; assign MUX_pciw_p2iS_write_1__VAL_2 = { pciw_Prelude_inst_changeSpecialWires_1_rg[80], pciw_fP2I_D_OUT[79], pciw_Prelude_inst_changeSpecialWires_1_rg[78:72], - wOut_be__h6604, - wOut_data__h6605 } ; + wOut_be__h6605, + wOut_data__h6606 } ; // inlined wires assign pciw_pci0_wTrnTxSof_n_wget = !pciw_fI2P_D_OUT[80] ; @@ -1935,6 +2079,22 @@ module mkFTop_ml605(sys0_clkp, assign pciw_pcie_irq_wInterruptDo_wget = pciw_pci0_pcie_ep_cfg_interrupt_do ; assign pciw_pcie_irq_wInterruptDo_whas = 1'd1 ; + assign a4lm_wrAddrRdy_w_wget = 1'd1 ; + assign a4lm_wrAddrRdy_w_whas = axbluart_s_axi_AWREADY ; + assign a4lm_wrDataRdy_w_wget = 1'd1 ; + assign a4lm_wrDataRdy_w_whas = axbluart_s_axi_WREADY ; + assign a4lm_wrRespVal_w_wget = 1'd1 ; + assign a4lm_wrRespVal_w_whas = axbluart_s_axi_BVALID ; + assign a4lm_rdAddrRdy_w_wget = 1'd1 ; + assign a4lm_rdAddrRdy_w_whas = axbluart_s_axi_ARREADY ; + assign a4lm_rdRespVal_w_wget = 1'd1 ; + assign a4lm_rdRespVal_w_whas = axbluart_s_axi_RVALID ; + assign a4lm_wrResp_w_wget = axbluart_s_axi_BRESP ; + assign a4lm_wrResp_w_whas = 1'd1 ; + assign a4lm_rdData_w_wget = axbluart_s_axi_RDATA ; + assign a4lm_rdData_w_whas = 1'd1 ; + assign a4lm_rdResp_w_wget = axbluart_s_axi_RRESP ; + assign a4lm_rdResp_w_whas = 1'd1 ; assign pciw_pci0_pwTrnTx_whas = !pciw_pci0_pcie_ep_trn_tdst_rdy_n && pciw_fI2P_EMPTY_N ; assign pciw_pci0_pwTrnRx_whas = @@ -2082,6 +2242,21 @@ module mkFTop_ml605(sys0_clkp, pciw_pci0_pcie_ep_cfg_interrupt_msienable ; assign pciw_pcie_irq_rMSIEnabled_EN = 1'd1 ; + // submodule axbluart + assign axbluart_s_axi_ARADDR = wmemiTap_axiM0_rdAddr_data[31:0] ; + assign axbluart_s_axi_ARPROT = wmemiTap_axiM0_rdAddr_data[34:32] ; + assign axbluart_s_axi_AWADDR = wmemiTap_axiM0_wrAddr_data[31:0] ; + assign axbluart_s_axi_AWPROT = wmemiTap_axiM0_wrAddr_data[34:32] ; + assign axbluart_s_axi_WDATA = wmemiTap_axiM0_wrData_data[31:0] ; + assign axbluart_s_axi_WSTRB = wmemiTap_axiM0_wrData_data[35:32] ; + assign axbluart_upads_cts_arg = upads_cts_arg ; + assign axbluart_upads_rx_arg = upads_rx_arg ; + assign axbluart_s_axi_AWVALID = wmemiTap_axiM0_wrAddr_valid ; + assign axbluart_s_axi_WVALID = wmemiTap_axiM0_wrData_valid ; + assign axbluart_s_axi_BREADY = wmemiTap_axiM0_wrResp_ready ; + assign axbluart_s_axi_ARVALID = wmemiTap_axiM0_rdAddr_valid ; + assign axbluart_s_axi_RREADY = wmemiTap_axiM0_rdResp_ready ; + // submodule cap0 assign cap0_wciS0_MAddr = ctop_wci_m_3_MAddr ; assign cap0_wciS0_MAddrSpace = ctop_wci_m_3_MAddrSpace ; @@ -2105,8 +2280,6 @@ module mkFTop_ml605(sys0_clkp, assign ctop_gps_ppsSyncIn_x = gps_ppsSyncIn_x ; assign ctop_server_request_put = pciw_p2iS ; assign ctop_switch_x = 3'h0 ; - assign ctop_upads_cts_arg = upads_cts_arg ; - assign ctop_upads_rx_arg = upads_rx_arg ; assign ctop_wci_m_0_SData = fmc150_wciS0_SData ; assign ctop_wci_m_0_SFlag = fmc150_wciS0_SFlag ; assign ctop_wci_m_0_SResp = fmc150_wciS0_SResp ; @@ -2122,8 +2295,8 @@ module mkFTop_ml605(sys0_clkp, assign ctop_wci_m_4_SData = dram0_wciS0_SData ; assign ctop_wci_m_4_SFlag = dram0_wciS0_SFlag ; assign ctop_wci_m_4_SResp = dram0_wciS0_SResp ; - assign ctop_wmemiM0_SData = dram0_wmemiS0_SData ; - assign ctop_wmemiM0_SResp = dram0_wmemiS0_SResp ; + assign ctop_wmemiM0_SData = wmemiTap_wmemiS0_SData ; + assign ctop_wmemiM0_SResp = wmemiTap_wmemiS0_SResp ; assign ctop_wsi_s_adc_MBurstLength = 12'h0 ; assign ctop_wsi_s_adc_MByteEn = 16'h0 ; assign ctop_wsi_s_adc_MCmd = 3'h0 ; @@ -2138,10 +2311,10 @@ module mkFTop_ml605(sys0_clkp, !pciw_i2pAF_sInReset_isInReset && ctop_RDY_server_response_get ; assign ctop_EN_cpServer_request_put = - gbe0_RDY_cpClient_request_get && ctop_RDY_cpServer_request_put ; + ctop_RDY_cpServer_request_put && gbe0_RDY_cpClient_request_get ; assign ctop_EN_cpServer_response_get = - gbe0_RDY_cpClient_response_put && - ctop_RDY_cpServer_response_get ; + ctop_RDY_cpServer_response_get && + gbe0_RDY_cpClient_response_put ; assign ctop_wci_m_0_SThreadBusy = fmc150_wciS0_SThreadBusy ; assign ctop_wci_m_1_SThreadBusy = flash0_wciS0_SThreadBusy ; assign ctop_wci_m_2_SThreadBusy = gbe0_wciS0_SThreadBusy ; @@ -2152,9 +2325,9 @@ module mkFTop_ml605(sys0_clkp, assign ctop_wsi_s_adc_MReset_n = 1'b0 ; assign ctop_wsi_m_dac_SThreadBusy = 1'b0 ; assign ctop_wsi_m_dac_SReset_n = 1'b0 ; - assign ctop_wmemiM0_SRespLast = dram0_wmemiS0_SRespLast ; - assign ctop_wmemiM0_SCmdAccept = dram0_wmemiS0_SCmdAccept ; - assign ctop_wmemiM0_SDataAccept = dram0_wmemiS0_SDataAccept ; + assign ctop_wmemiM0_SRespLast = wmemiTap_wmemiS0_SRespLast ; + assign ctop_wmemiM0_SCmdAccept = wmemiTap_wmemiS0_SCmdAccept ; + assign ctop_wmemiM0_SDataAccept = wmemiTap_wmemiS0_SDataAccept ; // submodule dram0 assign dram0_wciS0_MAddr = ctop_wci_m_4_MAddr ; @@ -2163,15 +2336,15 @@ module mkFTop_ml605(sys0_clkp, assign dram0_wciS0_MCmd = ctop_wci_m_4_MCmd ; assign dram0_wciS0_MData = ctop_wci_m_4_MData ; assign dram0_wciS0_MFlag = ctop_wci_m_4_MFlag ; - assign dram0_wmemiS0_MAddr = ctop_wmemiM0_MAddr ; - assign dram0_wmemiS0_MBurstLength = ctop_wmemiM0_MBurstLength ; - assign dram0_wmemiS0_MCmd = ctop_wmemiM0_MCmd ; - assign dram0_wmemiS0_MData = ctop_wmemiM0_MData ; - assign dram0_wmemiS0_MDataByteEn = ctop_wmemiM0_MDataByteEn ; - assign dram0_wmemiS0_MReqLast = ctop_wmemiM0_MReqLast ; - assign dram0_wmemiS0_MDataValid = ctop_wmemiM0_MDataValid ; - assign dram0_wmemiS0_MDataLast = ctop_wmemiM0_MDataLast ; - assign dram0_wmemiS0_MReset_n = ctop_wmemiM0_MReset_n ; + assign dram0_wmemiS0_MAddr = wmemiTap_wmemiM0_MAddr ; + assign dram0_wmemiS0_MBurstLength = wmemiTap_wmemiM0_MBurstLength ; + assign dram0_wmemiS0_MCmd = wmemiTap_wmemiM0_MCmd ; + assign dram0_wmemiS0_MData = wmemiTap_wmemiM0_MData ; + assign dram0_wmemiS0_MDataByteEn = wmemiTap_wmemiM0_MDataByteEn ; + assign dram0_wmemiS0_MReqLast = wmemiTap_wmemiM0_MReqLast ; + assign dram0_wmemiS0_MDataValid = wmemiTap_wmemiM0_MDataValid ; + assign dram0_wmemiS0_MDataLast = wmemiTap_wmemiM0_MDataLast ; + assign dram0_wmemiS0_MReset_n = wmemiTap_wmemiM0_MReset_n ; // submodule flash0 assign flash0_flash_fwait_i = flash_fwait_i ; @@ -2218,10 +2391,10 @@ module mkFTop_ml605(sys0_clkp, assign gbe0_wsiS0_MBurstPrecise = 1'b0 ; assign gbe0_wsiS0_MReset_n = 1'b0 ; assign gbe0_EN_cpClient_request_get = - gbe0_RDY_cpClient_request_get && ctop_RDY_cpServer_request_put ; + ctop_RDY_cpServer_request_put && gbe0_RDY_cpClient_request_get ; assign gbe0_EN_cpClient_response_put = - gbe0_RDY_cpClient_response_put && - ctop_RDY_cpServer_response_get ; + ctop_RDY_cpServer_response_get && + gbe0_RDY_cpClient_response_put ; // submodule lcd_ctrl assign lcd_ctrl_setLine1_text = 128'h202073656C75522063696D6F74412020 ; @@ -2329,17 +2502,41 @@ module mkFTop_ml605(sys0_clkp, assign tcGbe0_wti_m_SThreadBusy = gbe0_wtiS0_SThreadBusy ; assign tcGbe0_wti_m_SReset_n = gbe0_wtiS0_SReset_n ; + // submodule wmemiTap + assign wmemiTap_axiM0_rdAddr_ready_value = axbluart_s_axi_ARREADY ; + assign wmemiTap_axiM0_rdResp_data_value = + { axbluart_s_axi_RRESP, axbluart_s_axi_RDATA } ; + assign wmemiTap_axiM0_rdResp_valid_value = axbluart_s_axi_RVALID ; + assign wmemiTap_axiM0_wrAddr_ready_value = axbluart_s_axi_AWREADY ; + assign wmemiTap_axiM0_wrData_ready_value = axbluart_s_axi_WREADY ; + assign wmemiTap_axiM0_wrResp_data_value = axbluart_s_axi_BRESP ; + assign wmemiTap_axiM0_wrResp_valid_value = axbluart_s_axi_BVALID ; + assign wmemiTap_wmemiM0_SData = dram0_wmemiS0_SData ; + assign wmemiTap_wmemiM0_SResp = dram0_wmemiS0_SResp ; + assign wmemiTap_wmemiS0_MAddr = ctop_wmemiM0_MAddr ; + assign wmemiTap_wmemiS0_MBurstLength = ctop_wmemiM0_MBurstLength ; + assign wmemiTap_wmemiS0_MCmd = ctop_wmemiM0_MCmd ; + assign wmemiTap_wmemiS0_MData = ctop_wmemiM0_MData ; + assign wmemiTap_wmemiS0_MDataByteEn = ctop_wmemiM0_MDataByteEn ; + assign wmemiTap_wmemiS0_MReqLast = ctop_wmemiM0_MReqLast ; + assign wmemiTap_wmemiS0_MDataValid = ctop_wmemiM0_MDataValid ; + assign wmemiTap_wmemiS0_MDataLast = ctop_wmemiM0_MDataLast ; + assign wmemiTap_wmemiS0_MReset_n = ctop_wmemiM0_MReset_n ; + assign wmemiTap_wmemiM0_SRespLast = dram0_wmemiS0_SRespLast ; + assign wmemiTap_wmemiM0_SCmdAccept = dram0_wmemiS0_SCmdAccept ; + assign wmemiTap_wmemiM0_SDataAccept = dram0_wmemiS0_SDataAccept ; + // remaining internal signals assign pciw_p2iAF_head_wrapped_crossed__4_EQ_pciw_p2i_ETC___d123 = pciw_p2iAF_head_wrapped == pciw_p2iAF_tail_wrapped && !pciw_p2iAF_sInReset_isInReset && pciw_preEdge_CLK_VAL ; - assign val_be__h6495 = { pciw_fP2I_D_OUT[71:64], 8'd0 } ; - assign val_data__h6496 = { pciw_fP2I_D_OUT[63:0], 64'hAAAAAAAAAAAAAAAA } ; - assign wOut_be__h6604 = + assign val_be__h6496 = { pciw_fP2I_D_OUT[71:64], 8'd0 } ; + assign val_data__h6497 = { pciw_fP2I_D_OUT[63:0], 64'hAAAAAAAAAAAAAAAA } ; + assign wOut_be__h6605 = { pciw_Prelude_inst_changeSpecialWires_1_rg[71:64], pciw_fP2I_D_OUT[71:64] } ; - assign wOut_data__h6605 = + assign wOut_data__h6606 = { pciw_Prelude_inst_changeSpecialWires_1_rg[63:0], pciw_fP2I_D_OUT[63:0] } ; diff --git a/rtl/mkFlashController2416.v b/rtl/mkFlashController2416.v index edacd369..31c818ff 100644 --- a/rtl/mkFlashController2416.v +++ b/rtl/mkFlashController2416.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:49 EST 2014 +// On Mon Feb 3 15:00:22 EST 2014 // // // Ports: diff --git a/rtl/mkFlashWorker.v b/rtl/mkFlashWorker.v index ce25db86..ab81b19a 100644 --- a/rtl/mkFlashWorker.v +++ b/rtl/mkFlashWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:08 EST 2014 +// On Mon Feb 3 15:04:39 EST 2014 // // // Ports: @@ -488,14 +488,15 @@ module mkFlashWorker(wciS0_Clk, wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2; wire MUX_flashC_ceReg_write_1__SEL_1, MUX_flashC_oeReg_write_1__SEL_1, + MUX_flashC_reqF_enq_1__SEL_1, MUX_flashC_rseqFsm_start_reg_write_1__SEL_1, MUX_flashC_weReg_write_1__SEL_1, MUX_flashC_wseqFsm_start_reg_write_1__SEL_1, MUX_rdReg_write_1__SEL_1, MUX_splitReadInFlight_write_1__SEL_1, - MUX_splitReadInFlight_write_1__SEL_2, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -843,6 +844,8 @@ module mkFlashWorker(wciS0_Clk, assign MUX_flashC_oeReg_write_1__SEL_1 = WILL_FIRE_RL_flashC_wseqFsm_action_l90c12 || WILL_FIRE_RL_flashC_rseqFsm_action_l64c12 ; + assign MUX_flashC_reqF_enq_1__SEL_1 = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ; assign MUX_flashC_rseqFsm_start_reg_write_1__SEL_1 = WILL_FIRE_RL_flashC_nextRequest && flashC_reqF_D_OUT[40] ; assign MUX_flashC_weReg_write_1__SEL_1 = @@ -854,9 +857,9 @@ module mkFlashWorker(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h10 ; assign MUX_splitReadInFlight_write_1__SEL_1 = WILL_FIRE_RL_advance_response && splitReadInFlight ; - assign MUX_splitReadInFlight_write_1__SEL_2 = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -895,7 +898,7 @@ module mkFlashWorker(wciS0_Clk, assign MUX_flashC_wseqFsm_jj_delay_count_write_1__VAL_1 = { flashC_wseqFsm_jj_delay_count[5:0], 1'd0 } ; assign MUX_rdReg_write_1__VAL_2 = { 16'd0, flashC_respF_D_OUT } ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; @@ -1388,11 +1391,11 @@ module mkFlashWorker(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1499,7 +1502,7 @@ module mkFlashWorker(wciS0_Clk, // submodule flashC_reqF assign flashC_reqF_D_IN = - MUX_splitReadInFlight_write_1__SEL_2 ? + MUX_flashC_reqF_enq_1__SEL_1 ? MUX_flashC_reqF_enq_1__VAL_1 : MUX_flashC_reqF_enq_1__VAL_2 ; assign flashC_reqF_ENQ = diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index d3177a98..df2ac521 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:45 EST 2014 +// On Mon Feb 3 15:00:18 EST 2014 // // // Ports: diff --git a/rtl/mkGbeWorker.v b/rtl/mkGbeWorker.v index ceb6da0e..ce9efdc9 100644 --- a/rtl/mkGbeWorker.v +++ b/rtl/mkGbeWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:18 EST 2014 +// On Mon Feb 3 15:04:46 EST 2014 // // // Ports: diff --git a/rtl/mkICAPWorker.v b/rtl/mkICAPWorker.v index 41510aa4..31d7e564 100644 --- a/rtl/mkICAPWorker.v +++ b/rtl/mkICAPWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:10 EST 2014 +// On Mon Feb 3 15:04:41 EST 2014 // // // Ports: diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v index e1a186fd..290f59b3 100644 --- a/rtl/mkMemiTestWorker.v +++ b/rtl/mkMemiTestWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:21 EST 2014 +// On Mon Feb 3 15:05:00 EST 2014 // // // Ports: diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v index a7b7f2bf..07d9ccbc 100644 --- a/rtl/mkOCApp16B.v +++ b/rtl/mkOCApp16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:33 EST 2014 +// On Mon Feb 3 15:05:12 EST 2014 // // // Ports: diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index b37bbb4f..1892e906 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:33:49 EST 2014 +// On Mon Feb 3 15:31:07 EST 2014 // // // Ports: @@ -24330,7 +24330,7 @@ module mkOCCP(pciDevice, 32'h00000001; 8'h0C: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = - 32'd1391113942; + 32'd1391459380; 8'h10: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = { 17'd0, x__h104311 }; diff --git a/rtl/mkOCDP16B.v b/rtl/mkOCDP16B.v index 5e432983..d9dcc847 100644 --- a/rtl/mkOCDP16B.v +++ b/rtl/mkOCDP16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:29:35 EST 2014 +// On Mon Feb 3 15:07:20 EST 2014 // // // Ports: @@ -1594,6 +1594,7 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq, WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq, WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq, @@ -2265,8 +2266,8 @@ module mkOCDP16B(pciDevice, .DEQ(tlp_inF_DEQ), .ENQ(tlp_inF_ENQ), .CLR(tlp_inF_CLR), - .EMPTY_N(tlp_inF_EMPTY_N), .D_OUT(tlp_inF_D_OUT), + .EMPTY_N(tlp_inF_EMPTY_N), .FULL_N(tlp_inF_FULL_N)); // submodule tlp_outF @@ -2276,8 +2277,8 @@ module mkOCDP16B(pciDevice, .DEQ(tlp_outF_DEQ), .ENQ(tlp_outF_ENQ), .CLR(tlp_outF_CLR), - .EMPTY_N(tlp_outF_EMPTY_N), .D_OUT(tlp_outF_D_OUT), + .EMPTY_N(tlp_outF_EMPTY_N), .FULL_N(tlp_outF_FULL_N)); // submodule tlp_tailEventF @@ -2380,6 +2381,11 @@ module mkOCDP16B(pciDevice, .FULL_N(wmi_wmi_reqF_FULL_N), .EMPTY_N(wmi_wmi_reqF_EMPTY_N)); + // rule RL_bram_2_serverAdapterA_outData_setFirstEnq + assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq = + !bram_2_serverAdapterA_outDataCore_EMPTY_N && + bram_2_serverAdapterA_outData_enqData_whas ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N && @@ -3665,13 +3671,12 @@ module mkOCDP16B(pciDevice, bram_2_serverAdapterA_s1[1] && bram_2_serverAdapterA_s1[0] ; assign bram_2_serverAdapterA_outData_outData_wget = - bram_2_serverAdapterA_outDataCore_EMPTY_N ? - bram_2_serverAdapterA_outDataCore_D_OUT : - bram_2_memory_DOA ; + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ? + bram_2_memory_DOA : + bram_2_serverAdapterA_outDataCore_D_OUT ; assign bram_2_serverAdapterA_outData_outData_whas = - bram_2_serverAdapterA_outDataCore_EMPTY_N || - !bram_2_serverAdapterA_outDataCore_EMPTY_N && - bram_2_serverAdapterA_outData_enqData_whas ; + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq || + bram_2_serverAdapterA_outDataCore_EMPTY_N ; assign bram_2_serverAdapterA_cnt_1_wget = 3'd1 ; assign bram_2_serverAdapterA_cnt_1_whas = (MUX_bram_2_memory_a_put_1__SEL_1 || diff --git a/rtl/mkOCInf16B.v b/rtl/mkOCInf16B.v index ad72f8e8..fb942190 100644 --- a/rtl/mkOCInf16B.v +++ b/rtl/mkOCInf16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:34:06 EST 2014 +// On Mon Feb 3 15:31:24 EST 2014 // // // Ports: diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index 407528fa..75179f6b 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: @@ -128,8 +128,8 @@ module mkPktFork(pfk, .DEQ(fi_DEQ), .ENQ(fi_ENQ), .CLR(fi_CLR), - .EMPTY_N(fi_EMPTY_N), .D_OUT(fi_D_OUT), + .EMPTY_N(fi_EMPTY_N), .FULL_N(fi_FULL_N)); // submodule fo0 @@ -139,8 +139,8 @@ module mkPktFork(pfk, .DEQ(fo0_DEQ), .ENQ(fo0_ENQ), .CLR(fo0_CLR), - .EMPTY_N(fo0_EMPTY_N), .D_OUT(fo0_D_OUT), + .EMPTY_N(fo0_EMPTY_N), .FULL_N(fo0_FULL_N)); // submodule fo1 @@ -150,8 +150,8 @@ module mkPktFork(pfk, .DEQ(fo1_DEQ), .ENQ(fo1_ENQ), .CLR(fo1_CLR), - .EMPTY_N(fo1_EMPTY_N), .D_OUT(fo1_D_OUT), + .EMPTY_N(fo1_EMPTY_N), .FULL_N(fo1_FULL_N)); // rule RL_fo0_advance diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index 57c57caf..ae0a40eb 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: @@ -129,8 +129,8 @@ module mkPktMerge(CLK, .DEQ(fi0_DEQ), .ENQ(fi0_ENQ), .CLR(fi0_CLR), - .EMPTY_N(fi0_EMPTY_N), .D_OUT(fi0_D_OUT), + .EMPTY_N(fi0_EMPTY_N), .FULL_N(fi0_FULL_N)); // submodule fi1 @@ -140,8 +140,8 @@ module mkPktMerge(CLK, .DEQ(fi1_DEQ), .ENQ(fi1_ENQ), .CLR(fi1_CLR), - .EMPTY_N(fi1_EMPTY_N), .D_OUT(fi1_D_OUT), + .EMPTY_N(fi1_EMPTY_N), .FULL_N(fi1_FULL_N)); // submodule fo @@ -151,8 +151,8 @@ module mkPktMerge(CLK, .DEQ(fo_DEQ), .ENQ(fo_ENQ), .CLR(fo_CLR), - .EMPTY_N(fo_EMPTY_N), .D_OUT(fo_D_OUT), + .EMPTY_N(fo_EMPTY_N), .FULL_N(fo_FULL_N)); // rule RL_fi0_advance diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index 0502c515..fbea561b 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:41 EST 2014 +// On Mon Feb 3 15:00:15 EST 2014 // // // Ports: diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index de138fb8..04a415a8 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:43 EST 2014 +// On Mon Feb 3 15:00:16 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index 9530ba6d..0fbc1145 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:24 EST 2014 +// On Mon Feb 3 15:05:03 EST 2014 // // // Ports: @@ -948,7 +948,7 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount_write_1__VAL_1, + wire [31 : 0] MUX_mesgCount_write_1__VAL_2, MUX_thisMesg_write_1__VAL_1, MUX_thisMesg_write_1__VAL_2, MUX_wmi_mFlagF_q_0_write_1__VAL_1, @@ -1539,7 +1539,7 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_fabWordsRemain_write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain_write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount_write_1__VAL_1 = mesgCount + 32'd1 ; + assign MUX_mesgCount_write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgReqAddr_write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ; assign MUX_opcode_write_1__VAL_3 = { 1'd1, wsiS_reqFifo_D_OUT[7:0] } ; @@ -1865,14 +1865,14 @@ module mkSMAdapter16B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount_write_1__SEL_1 or - MUX_mesgCount_write_1__VAL_1 or + MUX_mesgCount_write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount_write_1__SEL_1: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount_D_IN = 32'd0; default: mesgCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index 52829c87..116960e6 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:30 EST 2014 +// On Mon Feb 3 15:05:09 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index 30328901..ed85d210 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:26 EST 2014 +// On Mon Feb 3 15:05:05 EST 2014 // // // Ports: diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index 5c9e167f..6933ad08 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:28 EST 2014 +// On Mon Feb 3 15:05:07 EST 2014 // // // Ports: @@ -946,7 +946,7 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wci_wslv_respF_q_1_write_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount_write_1__VAL_1, + wire [31 : 0] MUX_mesgCount_write_1__VAL_2, MUX_thisMesg_write_1__VAL_1, MUX_thisMesg_write_1__VAL_2, MUX_wmi_mFlagF_q_0_write_1__VAL_1, @@ -1518,7 +1518,7 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_fabWordsRemain_write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain_write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount_write_1__VAL_1 = mesgCount + 32'd1 ; + assign MUX_mesgCount_write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar_write_1__VAL_1 = mesgLengthSoFar + mlInc__h22205 ; assign MUX_mesgReqAddr_write_1__VAL_2 = @@ -1846,14 +1846,14 @@ module mkSMAdapter8B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount_write_1__SEL_1 or - MUX_mesgCount_write_1__VAL_1 or + MUX_mesgCount_write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount_write_1__SEL_1: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount_D_IN = MUX_mesgCount_write_1__VAL_1; + mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount_D_IN = 32'd0; default: mesgCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index c628a386..20e1fb25 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index 62904f66..07014d21 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index 0ad67a94..0b0e8e7a 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: diff --git a/rtl/mkTLPSerializer.v b/rtl/mkTLPSerializer.v index 6911a0f1..90015985 100644 --- a/rtl/mkTLPSerializer.v +++ b/rtl/mkTLPSerializer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:29:26 EST 2014 +// On Mon Feb 3 15:07:11 EST 2014 // // // Ports: diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index 01db759e..a0fd7d91 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:46 EST 2014 +// On Mon Feb 3 15:05:32 EST 2014 // // // Ports: diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index c3ed86cf..e9a36746 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:11 EST 2014 +// On Mon Feb 3 15:04:42 EST 2014 // // // Ports: diff --git a/rtl/mkUUID.v b/rtl/mkUUID.v index 0babf473..eef99703 100644 --- a/rtl/mkUUID.v +++ b/rtl/mkUUID.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:51 EST 2014 +// On Mon Feb 3 15:04:55 EST 2014 // // // Ports: diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index c1eed704..9db5448e 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:21 EST 2014 +// On Mon Feb 3 15:04:49 EST 2014 // // // Ports: @@ -841,7 +841,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways, WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_1_serverAdapterA_outData_setFirstEnq, WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways, WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq, @@ -1275,11 +1274,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd0 && wci_wslv_reqF_D_OUT[63:52] == 12'h400 ; - // rule RL_metaBram_1_serverAdapterA_outData_setFirstEnq - assign WILL_FIRE_RL_metaBram_1_serverAdapterA_outData_setFirstEnq = - !metaBram_1_serverAdapterA_outDataCore_EMPTY_N && - metaBram_1_serverAdapterA_outData_enqData_whas ; - // rule RL_metaBram_1_serverAdapterB_stageReadResponseAlways assign WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[35:34] == 2'd1 && @@ -1335,7 +1329,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq = metaBram_1_serverAdapterB_outDataCore_EMPTY_N && metaBram_1_serverAdapterB_outDataCore_FULL_N && - metaBram_1_serverAdapterB_cnt_2_whas && + metaBram_1_serverAdapterB_outData_deqCalled_whas && metaBram_1_serverAdapterB_outData_enqData_whas ; // rule RL_metaBram_2_serverAdapterB_outData_enqAndDeq @@ -1631,12 +1625,13 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_1_serverAdapterA_s1[1] && metaBram_1_serverAdapterA_s1[0] ; assign metaBram_1_serverAdapterA_outData_outData_wget = - WILL_FIRE_RL_metaBram_1_serverAdapterA_outData_setFirstEnq ? - metaBram_1_memory_DOA : - metaBram_1_serverAdapterA_outDataCore_D_OUT ; + metaBram_1_serverAdapterA_outDataCore_EMPTY_N ? + metaBram_1_serverAdapterA_outDataCore_D_OUT : + metaBram_1_memory_DOA ; assign metaBram_1_serverAdapterA_outData_outData_whas = - WILL_FIRE_RL_metaBram_1_serverAdapterA_outData_setFirstEnq || - metaBram_1_serverAdapterA_outDataCore_EMPTY_N ; + metaBram_1_serverAdapterA_outDataCore_EMPTY_N || + !metaBram_1_serverAdapterA_outDataCore_EMPTY_N && + metaBram_1_serverAdapterA_outData_enqData_whas ; assign metaBram_1_serverAdapterA_cnt_1_wget = 3'd1 ; assign metaBram_1_serverAdapterA_cnt_1_whas = 1'b0 ; assign metaBram_1_serverAdapterA_cnt_2_wget = 3'h0 ; @@ -1665,9 +1660,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ; assign metaBram_1_serverAdapterB_cnt_2_wget = 3'd7 ; assign metaBram_1_serverAdapterB_cnt_2_whas = - MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 && - splaF_D_OUT[1:0] == 2'd1 && - !splaF_D_OUT[2] ; + metaBram_1_serverAdapterB_outData_deqCalled_whas ; assign metaBram_1_serverAdapterB_cnt_3_wget = 3'h0 ; assign metaBram_1_serverAdapterB_cnt_3_whas = 1'b0 ; assign metaBram_1_serverAdapterB_writeWithResp_wget = 2'd0 ; @@ -1835,7 +1828,9 @@ module mkWSICaptureWorker4B(wciS0_Clk, !splaF_D_OUT[2] ; assign metaBram_1_serverAdapterA_outData_deqCalled_whas = 1'b0 ; assign metaBram_1_serverAdapterB_outData_deqCalled_whas = - metaBram_1_serverAdapterB_cnt_2_whas ; + MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 && + splaF_D_OUT[1:0] == 2'd1 && + !splaF_D_OUT[2] ; assign metaBram_2_serverAdapterA_outData_deqCalled_whas = 1'b0 ; assign metaBram_2_serverAdapterB_outData_deqCalled_whas = MUX_wci_wslv_respF_x_wire_wset_1__SEL_3 && @@ -1948,7 +1943,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561 ; assign metaBram_1_serverAdapterB_cnt_EN = WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways || - metaBram_1_serverAdapterB_cnt_2_whas ; + metaBram_1_serverAdapterB_outData_deqCalled_whas ; // register metaBram_1_serverAdapterB_s1 assign metaBram_1_serverAdapterB_s1_D_IN = @@ -2343,12 +2338,12 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_1_serverAdapterB_outDataCore_ENQ = WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq || metaBram_1_serverAdapterB_outDataCore_FULL_N && - !metaBram_1_serverAdapterB_cnt_2_whas && + !metaBram_1_serverAdapterB_outData_deqCalled_whas && metaBram_1_serverAdapterB_outData_enqData_whas ; assign metaBram_1_serverAdapterB_outDataCore_DEQ = WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq || metaBram_1_serverAdapterB_outDataCore_EMPTY_N && - metaBram_1_serverAdapterB_cnt_2_whas && + metaBram_1_serverAdapterB_outData_deqCalled_whas && !metaBram_1_serverAdapterB_outData_enqData_whas ; assign metaBram_1_serverAdapterB_outDataCore_CLR = 1'b0 ; @@ -2494,7 +2489,9 @@ module mkWSICaptureWorker4B(wciS0_Clk, (WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + - (metaBram_1_serverAdapterB_cnt_2_whas ? 3'd7 : 3'd0) ; + (metaBram_1_serverAdapterB_outData_deqCalled_whas ? + 3'd7 : + 3'd0) ; assign metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679 = metaBram_2_serverAdapterB_cnt + (WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ? @@ -2561,26 +2558,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_3_serverAdapterB_outDataCore_EMPTY_N ? metaBram_3_serverAdapterB_outDataCore_D_OUT : metaBram_3_memory_DOB ; - always@(wci_wslv_reqF_D_OUT or - controlReg or - metaCount or - dataCount or - rdat___1__h26833 or - rdat___1__h26917 or - rdat___1__h26972 or rdat___1__h26986 or rdat___1__h26994) - begin - case (wci_wslv_reqF_D_OUT[39:32]) - 8'h0: v__h26736 = controlReg; - 8'h04: v__h26736 = metaCount; - 8'h08: v__h26736 = dataCount; - 8'h0C: v__h26736 = rdat___1__h26833; - 8'h10: v__h26736 = rdat___1__h26917; - 8'h14: v__h26736 = rdat___1__h26972; - 8'h18: v__h26736 = rdat___1__h26986; - 8'h1C: v__h26736 = rdat___1__h26994; - default: v__h26736 = 32'd0; - endcase - end always@(wci_wslv_reqF_D_OUT or metaBram_0_serverAdapterB_cnt or metaBram_1_serverAdapterB_cnt or @@ -2601,6 +2578,26 @@ module mkWSICaptureWorker4B(wciS0_Clk, (metaBram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7; endcase end + always@(wci_wslv_reqF_D_OUT or + controlReg or + metaCount or + dataCount or + rdat___1__h26833 or + rdat___1__h26917 or + rdat___1__h26972 or rdat___1__h26986 or rdat___1__h26994) + begin + case (wci_wslv_reqF_D_OUT[39:32]) + 8'h0: v__h26736 = controlReg; + 8'h04: v__h26736 = metaCount; + 8'h08: v__h26736 = dataCount; + 8'h0C: v__h26736 = rdat___1__h26833; + 8'h10: v__h26736 = rdat___1__h26917; + 8'h14: v__h26736 = rdat___1__h26972; + 8'h18: v__h26736 = rdat___1__h26986; + 8'h1C: v__h26736 = rdat___1__h26994; + default: v__h26736 = 32'd0; + endcase + end always@(wci_wslv_reqF_D_OUT or splaF_FULL_N or CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 or diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index 2b236a34..730cd88c 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:56 EST 2014 +// On Mon Feb 3 15:04:30 EST 2014 // // // Ports: @@ -294,8 +294,8 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initiator_wrkBusy; // inputs to muxes for submodule ports - reg [71 : 0] MUX_initiator_reqF_q_0_write_1__VAL_1; - wire [71 : 0] MUX_initiator_reqF_q_0_write_1__VAL_2, + reg [71 : 0] MUX_initiator_reqF_q_0_write_1__VAL_2; + wire [71 : 0] MUX_initiator_reqF_q_0_write_1__VAL_1, MUX_initiator_reqF_x_wire_wset_1__VAL_1, MUX_initiator_reqF_x_wire_wset_1__VAL_2; wire [33 : 0] MUX_initiator_respF_enq_1__VAL_2; @@ -310,7 +310,7 @@ module mkWciInitiator(CLK, MUX_initiator_lastOpWrite_write_1__SEL_2, MUX_initiator_reqF_cntr_r_write_1__VAL_1, MUX_initiator_reqF_cntr_r_write_1__VAL_2, - MUX_initiator_reqF_q_0_write_1__SEL_1, + MUX_initiator_reqF_q_0_write_1__SEL_2, MUX_initiator_reqPend_write_1__PSEL_3, MUX_initiator_reqPend_write_1__SEL_3, MUX_initiator_reqPend_write_1__SEL_4, @@ -497,7 +497,7 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n ; assign MUX_initiator_lastOpWrite_write_1__SEL_2 = WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n ; - assign MUX_initiator_reqF_q_0_write_1__SEL_1 = + assign MUX_initiator_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_cntr_r ; assign MUX_initiator_reqPend_write_1__PSEL_3 = WILL_FIRE_RL_initFsm_action_l1114c14 || @@ -513,6 +513,10 @@ module mkWciInitiator(CLK, initiator_reqF_cntr_r + 1'd1 ; assign MUX_initiator_reqF_cntr_r_write_1__VAL_2 = initiator_reqF_cntr_r - 1'd1 ; + assign MUX_initiator_reqF_q_0_write_1__VAL_1 = + initiator_reqF_cntr_r ? + MUX_initiator_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(MUX_initiator_lastOpWrite_write_1__SEL_2 or MUX_initiator_reqF_x_wire_wset_1__VAL_1 or MUX_initiator_lastOpWrite_write_1__SEL_1 or @@ -522,23 +526,19 @@ module mkWciInitiator(CLK, begin case (1'b1) // synopsys parallel_case MUX_initiator_lastOpWrite_write_1__SEL_2: - MUX_initiator_reqF_q_0_write_1__VAL_1 = + MUX_initiator_reqF_q_0_write_1__VAL_2 = MUX_initiator_reqF_x_wire_wset_1__VAL_1; MUX_initiator_lastOpWrite_write_1__SEL_1: - MUX_initiator_reqF_q_0_write_1__VAL_1 = + MUX_initiator_reqF_q_0_write_1__VAL_2 = MUX_initiator_reqF_x_wire_wset_1__VAL_2; MUX_initiator_lastControlOp_write_1__SEL_1: - MUX_initiator_reqF_q_0_write_1__VAL_1 = 72'h4F0000000080000000; + MUX_initiator_reqF_q_0_write_1__VAL_2 = 72'h4F0000000080000000; MUX_initiator_lastControlOp_write_1__SEL_2: - MUX_initiator_reqF_q_0_write_1__VAL_1 = 72'h4F0000000480000000; - default: MUX_initiator_reqF_q_0_write_1__VAL_1 = + MUX_initiator_reqF_q_0_write_1__VAL_2 = 72'h4F0000000480000000; + default: MUX_initiator_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_initiator_reqF_q_0_write_1__VAL_2 = - initiator_reqF_cntr_r ? - MUX_initiator_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_initiator_reqF_x_wire_wset_1__VAL_1 = { 8'd63, x__h25157, 32'h80000042 } ; assign MUX_initiator_reqF_x_wire_wset_1__VAL_2 = @@ -555,7 +555,7 @@ module mkWciInitiator(CLK, 32'd0 ; // inlined wires - assign initiator_reqF_x_wire_wget = MUX_initiator_reqF_q_0_write_1__VAL_1 ; + assign initiator_reqF_x_wire_wget = MUX_initiator_reqF_q_0_write_1__VAL_2 ; assign initiator_reqF_x_wire_whas = WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n || WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n || @@ -764,16 +764,16 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initiator_reqF_decCtr ; // register initiator_reqF_q_0 - always@(MUX_initiator_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_initiator_reqF_both or MUX_initiator_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_initiator_reqF_both or + MUX_initiator_reqF_q_0_write_1__SEL_2 or MUX_initiator_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_initiator_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_initiator_reqF_q_0_write_1__SEL_1: - initiator_reqF_q_0_D_IN = MUX_initiator_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_initiator_reqF_both: + initiator_reqF_q_0_D_IN = MUX_initiator_reqF_q_0_write_1__VAL_1; + MUX_initiator_reqF_q_0_write_1__SEL_2: initiator_reqF_q_0_D_IN = MUX_initiator_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_initiator_reqF_decCtr: initiator_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -782,8 +782,8 @@ module mkWciInitiator(CLK, endcase end assign initiator_reqF_q_0_EN = - WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_cntr_r || WILL_FIRE_RL_initiator_reqF_both || + WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_cntr_r || WILL_FIRE_RL_initiator_reqF_decCtr ; // register initiator_reqPend diff --git a/rtl/mkWciMonitor.v b/rtl/mkWciMonitor.v index 688e34ef..a351eb35 100644 --- a/rtl/mkWciMonitor.v +++ b/rtl/mkWciMonitor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:58 EST 2014 +// On Mon Feb 3 15:04:32 EST 2014 // // // Ports: diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index b018265e..f0a080d0 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:50:56 EST 2014 +// On Mon Feb 3 15:04:30 EST 2014 // // // Ports: @@ -214,8 +214,8 @@ module mkWciTarget(wciS0_Clk, WILL_FIRE_RL_target_respF_incCtr; // inputs to muxes for submodule ports - reg [33 : 0] MUX_target_respF_q_0_write_1__VAL_1; - wire [33 : 0] MUX_target_respF_q_0_write_1__VAL_2, + reg [33 : 0] MUX_target_respF_q_0_write_1__VAL_2; + wire [33 : 0] MUX_target_respF_q_0_write_1__VAL_1, MUX_target_respF_q_1_write_1__VAL_1, MUX_target_respF_x_wire_wset_1__VAL_1, MUX_target_respF_x_wire_wset_1__VAL_2; @@ -326,9 +326,9 @@ module mkWciTarget(wciS0_Clk, target_reqF_D_OUT[36:34] == 3'd6 || target_reqF_D_OUT[36:34] == 3'd7) ; assign MUX_target_respF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd0 ; - assign MUX_target_respF_q_0_write_1__SEL_2 = WILL_FIRE_RL_target_respF_both && _dfoo3 ; + assign MUX_target_respF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd0 ; assign MUX_target_respF_q_1_write_1__SEL_1 = WILL_FIRE_RL_target_respF_both && _dfoo1 ; assign MUX_target_respF_q_1_write_1__SEL_2 = @@ -338,6 +338,10 @@ module mkWciTarget(wciS0_Clk, target_reqF_D_OUT[36:34] != 3'd5 && target_reqF_D_OUT[36:34] != 3'd6 ; assign MUX_target_respF_cntr_r_write_1__VAL_2 = target_respF_cntr_r + 2'd1 ; + assign MUX_target_respF_q_0_write_1__VAL_1 = + (target_respF_cntr_r == 2'd1) ? + MUX_target_respF_q_0_write_1__VAL_2 : + target_respF_q_1 ; always@(WILL_FIRE_RL_target_ctl_op_complete or MUX_target_respF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_target_cfrd or @@ -345,24 +349,20 @@ module mkWciTarget(wciS0_Clk, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_target_ctl_op_complete: - MUX_target_respF_q_0_write_1__VAL_1 = + MUX_target_respF_q_0_write_1__VAL_2 = MUX_target_respF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_target_cfrd: - MUX_target_respF_q_0_write_1__VAL_1 = + MUX_target_respF_q_0_write_1__VAL_2 = MUX_target_respF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_target_cfwr: - MUX_target_respF_q_0_write_1__VAL_1 = 34'h1C0DE4201; - default: MUX_target_respF_q_0_write_1__VAL_1 = + MUX_target_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_target_respF_q_0_write_1__VAL_2 = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign MUX_target_respF_q_0_write_1__VAL_2 = - (target_respF_cntr_r == 2'd1) ? - MUX_target_respF_q_0_write_1__VAL_1 : - target_respF_q_1 ; assign MUX_target_respF_q_1_write_1__VAL_1 = (target_respF_cntr_r == 2'd2) ? - MUX_target_respF_q_0_write_1__VAL_1 : + MUX_target_respF_q_0_write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_target_respF_x_wire_wset_1__VAL_1 = target_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; @@ -377,7 +377,7 @@ module mkWciTarget(wciS0_Clk, wciS0_MAddr, wciS0_MData } ; assign target_wciReq_whas = 1'd1 ; - assign target_respF_x_wire_wget = MUX_target_respF_q_0_write_1__VAL_1 ; + assign target_respF_x_wire_wget = MUX_target_respF_q_0_write_1__VAL_2 ; assign target_respF_x_wire_whas = WILL_FIRE_RL_target_ctl_op_complete || WILL_FIRE_RL_target_cfrd || @@ -529,23 +529,23 @@ module mkWciTarget(wciS0_Clk, endcase end assign target_respF_q_0_EN = + WILL_FIRE_RL_target_respF_both && _dfoo3 || WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd0 || - WILL_FIRE_RL_target_respF_both && _dfoo3 || WILL_FIRE_RL_target_respF_decCtr ; // register target_respF_q_1 always@(MUX_target_respF_q_1_write_1__SEL_1 or MUX_target_respF_q_1_write_1__VAL_1 or MUX_target_respF_q_1_write_1__SEL_2 or - MUX_target_respF_q_0_write_1__VAL_1 or + MUX_target_respF_q_0_write_1__VAL_2 or WILL_FIRE_RL_target_respF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_target_respF_q_1_write_1__SEL_1: target_respF_q_1_D_IN = MUX_target_respF_q_1_write_1__VAL_1; MUX_target_respF_q_1_write_1__SEL_2: - target_respF_q_1_D_IN = MUX_target_respF_q_0_write_1__VAL_1; + target_respF_q_1_D_IN = MUX_target_respF_q_0_write_1__VAL_2; WILL_FIRE_RL_target_respF_decCtr: target_respF_q_1_D_IN = 34'h0AAAAAAAA; default: target_respF_q_1_D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase diff --git a/rtl/mkWmemiTap.v b/rtl/mkWmemiTap.v index 6dc386c9..c391a228 100644 --- a/rtl/mkWmemiTap.v +++ b/rtl/mkWmemiTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 15:27:16 EST 2014 +// On Mon Feb 3 15:04:54 EST 2014 // // // Ports: @@ -609,12 +609,12 @@ module mkWmemiTap(CLK, MUX_wmemiM_dhF_q_1_write_1__VAL_2; wire [130 : 0] MUX_wmemiS_respF_q_0_write_1__VAL_1, MUX_wmemiS_respF_q_0_write_1__VAL_2, - MUX_wmemiS_respF_q_1_write_1__VAL_2, + MUX_wmemiS_respF_q_1_write_1__VAL_1, MUX_wmemiS_respF_x_wire_wset_1__VAL_1, MUX_wmemiS_respF_x_wire_wset_1__VAL_2; wire [51 : 0] MUX_wmemiM_reqF_q_0_write_1__VAL_1, MUX_wmemiM_reqF_q_0_write_1__VAL_2, - MUX_wmemiM_reqF_q_1_write_1__VAL_2; + MUX_wmemiM_reqF_q_1_write_1__VAL_1; wire [35 : 0] MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_1, MUX_a4l_a4wrData_fifof_q_0_write_1__VAL_2, MUX_a4l_a4wrData_fifof_q_1_write_1__VAL_2; @@ -962,21 +962,21 @@ module mkWmemiTap(CLK, assign MUX_wmemiM_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemiM_dhF_both && _dfoo9 ; assign MUX_wmemiM_reqF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 ; - assign MUX_wmemiM_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemiM_reqF_both && _dfoo7 ; + assign MUX_wmemiM_reqF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 ; assign MUX_wmemiM_reqF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 ; - assign MUX_wmemiM_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemiM_reqF_both && _dfoo5 ; + assign MUX_wmemiM_reqF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 ; assign MUX_wmemiS_respF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd0 ; - assign MUX_wmemiS_respF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemiS_respF_both && _dfoo3 ; + assign MUX_wmemiS_respF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd0 ; assign MUX_wmemiS_respF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd1 ; - assign MUX_wmemiS_respF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemiS_respF_both && _dfoo1 ; + assign MUX_wmemiS_respF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd1 ; assign MUX_a4l_a4rdAddr_fifof_cntr_r_write_1__VAL_2 = a4l_a4rdAddr_fifof_cntr_r + 2'd1 ; assign MUX_a4l_a4rdAddr_fifof_q_0_write_1__VAL_1 = @@ -1024,31 +1024,31 @@ module mkWmemiTap(CLK, 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign MUX_wmemiM_reqF_cntr_r_write_1__VAL_2 = wmemiM_reqF_cntr_r + 2'd1 ; assign MUX_wmemiM_reqF_q_0_write_1__VAL_1 = + (wmemiM_reqF_cntr_r == 2'd1) ? + MUX_wmemiM_reqF_q_0_write_1__VAL_2 : + wmemiM_reqF_q_1 ; + assign MUX_wmemiM_reqF_q_0_write_1__VAL_2 = { (wmemiS_reqF_D_OUT[51:49] == 3'd1) ? wmemiS_reqF_D_OUT[51:49] : 3'd2, 1'd1, wmemiS_reqF_D_OUT[47:0] } ; - assign MUX_wmemiM_reqF_q_0_write_1__VAL_2 = - (wmemiM_reqF_cntr_r == 2'd1) ? - MUX_wmemiM_reqF_q_0_write_1__VAL_1 : - wmemiM_reqF_q_1 ; - assign MUX_wmemiM_reqF_q_1_write_1__VAL_2 = + assign MUX_wmemiM_reqF_q_1_write_1__VAL_1 = (wmemiM_reqF_cntr_r == 2'd2) ? - MUX_wmemiM_reqF_q_0_write_1__VAL_1 : + MUX_wmemiM_reqF_q_0_write_1__VAL_2 : 52'h0AAAAAAAAAAAA ; assign MUX_wmemiS_respF_cntr_r_write_1__VAL_2 = wmemiS_respF_cntr_r + 2'd1 ; assign MUX_wmemiS_respF_q_0_write_1__VAL_1 = + (wmemiS_respF_cntr_r == 2'd1) ? + MUX_wmemiS_respF_q_0_write_1__VAL_2 : + wmemiS_respF_q_1 ; + assign MUX_wmemiS_respF_q_0_write_1__VAL_2 = WILL_FIRE_RL_wmemi_response ? MUX_wmemiS_respF_x_wire_wset_1__VAL_1 : MUX_wmemiS_respF_x_wire_wset_1__VAL_2 ; - assign MUX_wmemiS_respF_q_0_write_1__VAL_2 = - (wmemiS_respF_cntr_r == 2'd1) ? - MUX_wmemiS_respF_q_0_write_1__VAL_1 : - wmemiS_respF_q_1 ; - assign MUX_wmemiS_respF_q_1_write_1__VAL_2 = + assign MUX_wmemiS_respF_q_1_write_1__VAL_1 = (wmemiS_respF_cntr_r == 2'd2) ? - MUX_wmemiS_respF_q_0_write_1__VAL_1 : + MUX_wmemiS_respF_q_0_write_1__VAL_2 : 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; assign MUX_wmemiS_respF_x_wire_wset_1__VAL_1 = { 2'd1, wmemiM_respF_D_OUT[128:0] } ; @@ -1079,14 +1079,14 @@ module mkWmemiTap(CLK, wmemiS_dhF_FULL_N && wmemiS_operateD && wmemiS_peerIsReady && wmemiS_wmemiDh_wget[145] && wmemiS_dhF_FULL_N ; - assign wmemiS_respF_x_wire_wget = MUX_wmemiS_respF_q_0_write_1__VAL_1 ; + assign wmemiS_respF_x_wire_wget = MUX_wmemiS_respF_q_0_write_1__VAL_2 ; assign wmemiS_respF_x_wire_whas = WILL_FIRE_RL_wmemi_response || WILL_FIRE_RL_axi_read_response ; assign wmemiS_operateD_1_wget = 1'd1 ; assign wmemiS_operateD_1_whas = 1'd1 ; assign wmemiS_peerIsReady_1_wget = 1'd1 ; assign wmemiS_peerIsReady_1_whas = wmemiS0_MReset_n ; - assign wmemiM_reqF_x_wire_wget = MUX_wmemiM_reqF_q_0_write_1__VAL_1 ; + assign wmemiM_reqF_x_wire_wget = MUX_wmemiM_reqF_q_0_write_1__VAL_2 ; assign wmemiM_reqF_x_wire_whas = wmemiM_reqF_enqueueing_whas ; assign wmemiM_dhF_x_wire_wget = MUX_wmemiM_dhF_q_0_write_1__VAL_1 ; assign wmemiM_dhF_x_wire_whas = wmemiM_dhF_enqueueing_whas ; @@ -1457,22 +1457,22 @@ module mkWmemiTap(CLK, endcase end assign wmemiM_reqF_q_0_EN = - WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemiM_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemiM_reqF_decCtr ; // register wmemiM_reqF_q_1 always@(MUX_wmemiM_reqF_q_1_write_1__SEL_1 or - MUX_wmemiM_reqF_q_0_write_1__VAL_1 or + MUX_wmemiM_reqF_q_1_write_1__VAL_1 or MUX_wmemiM_reqF_q_1_write_1__SEL_2 or - MUX_wmemiM_reqF_q_1_write_1__VAL_2 or + MUX_wmemiM_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemiM_reqF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemiM_reqF_q_1_write_1__SEL_1: - wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_0_write_1__VAL_1; + wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_1_write_1__VAL_1; MUX_wmemiM_reqF_q_1_write_1__SEL_2: - wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_1_write_1__VAL_2; + wmemiM_reqF_q_1_D_IN = MUX_wmemiM_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmemiM_reqF_decCtr: wmemiM_reqF_q_1_D_IN = 52'h0AAAAAAAAAAAA; default: wmemiM_reqF_q_1_D_IN = @@ -1480,8 +1480,8 @@ module mkWmemiTap(CLK, endcase end assign wmemiM_reqF_q_1_EN = - WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemiM_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmemiM_reqF_incCtr && wmemiM_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemiM_reqF_decCtr ; // register wmemiM_statusR @@ -1542,23 +1542,23 @@ module mkWmemiTap(CLK, endcase end assign wmemiS_respF_q_0_EN = + WILL_FIRE_RL_wmemiS_respF_both && _dfoo3 || WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd0 || - WILL_FIRE_RL_wmemiS_respF_both && _dfoo3 || WILL_FIRE_RL_wmemiS_respF_decCtr ; // register wmemiS_respF_q_1 always@(MUX_wmemiS_respF_q_1_write_1__SEL_1 or - MUX_wmemiS_respF_q_0_write_1__VAL_1 or + MUX_wmemiS_respF_q_1_write_1__VAL_1 or MUX_wmemiS_respF_q_1_write_1__SEL_2 or - MUX_wmemiS_respF_q_1_write_1__VAL_2 or + MUX_wmemiS_respF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemiS_respF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemiS_respF_q_1_write_1__SEL_1: - wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_0_write_1__VAL_1; + wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_1_write_1__VAL_1; MUX_wmemiS_respF_q_1_write_1__SEL_2: - wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_1_write_1__VAL_2; + wmemiS_respF_q_1_D_IN = MUX_wmemiS_respF_q_0_write_1__VAL_2; WILL_FIRE_RL_wmemiS_respF_decCtr: wmemiS_respF_q_1_D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: wmemiS_respF_q_1_D_IN = @@ -1566,9 +1566,9 @@ module mkWmemiTap(CLK, endcase end assign wmemiS_respF_q_1_EN = + WILL_FIRE_RL_wmemiS_respF_both && _dfoo1 || WILL_FIRE_RL_wmemiS_respF_incCtr && wmemiS_respF_cntr_r == 2'd1 || - WILL_FIRE_RL_wmemiS_respF_both && _dfoo1 || WILL_FIRE_RL_wmemiS_respF_decCtr ; // register wmemiS_statusR diff --git a/rtl/mkWsiAdapter16B4B.v b/rtl/mkWsiAdapter16B4B.v index bd56eb6c..af4a016a 100644 --- a/rtl/mkWsiAdapter16B4B.v +++ b/rtl/mkWsiAdapter16B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:23 EST 2014 +// On Mon Feb 3 15:04:52 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter32B4B.v b/rtl/mkWsiAdapter32B4B.v index 3178cd24..28661f5f 100644 --- a/rtl/mkWsiAdapter32B4B.v +++ b/rtl/mkWsiAdapter32B4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:24 EST 2014 +// On Mon Feb 3 15:04:53 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B16B.v b/rtl/mkWsiAdapter4B16B.v index 91524875..4598d7e9 100644 --- a/rtl/mkWsiAdapter4B16B.v +++ b/rtl/mkWsiAdapter4B16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:23 EST 2014 +// On Mon Feb 3 15:04:51 EST 2014 // // // Ports: diff --git a/rtl/mkWsiAdapter4B32B.v b/rtl/mkWsiAdapter4B32B.v index f00abd91..6739d731 100644 --- a/rtl/mkWsiAdapter4B32B.v +++ b/rtl/mkWsiAdapter4B32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Thu Jan 30 14:51:24 EST 2014 +// On Mon Feb 3 15:04:52 EST 2014 // // // Ports: diff --git a/scripts/buildhdl/fpgaTop-ml605.prj b/scripts/buildhdl/fpgaTop-ml605.prj index 3de3c699..33db3dee 100644 --- a/scripts/buildhdl/fpgaTop-ml605.prj +++ b/scripts/buildhdl/fpgaTop-ml605.prj @@ -110,6 +110,8 @@ verilog work "../../rtl/mkWciMonitor.v" verilog work "../../rtl/mkFMC150.v" verilog work "../../rtl/mkBLUART.v" +verilog work "../../rtl/mkAXBLUART.v" +verilog work "../../rtl/mkWmemiTap.v" verilog work "../../rtl/mkLCDController.v" verilog work "../../rtl/mkFTop_ml605.v"