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Add VHDL support via GHDL call Build docs artifact with Verific #4: Commit ce95ec1 pushed by akashlevy
September 5, 2024 20:24 1d 3h 4m 23s main
main
September 5, 2024 20:24 1d 3h 4m 23s
Reduce verbosity Build docs artifact with Verific #3: Commit bebdb2f pushed by akashlevy
September 5, 2024 07:56 1d 12h 25m 56s main
main
September 5, 2024 07:56 1d 12h 25m 56s
Add splitcells and splitnets Build docs artifact with Verific #2: Commit 42dc3f6 pushed by akashlevy
September 5, 2024 04:54 1d 15h 27m 18s main
main
September 5, 2024 04:54 1d 15h 27m 18s
Merge branch 'YosysHQ:main' into main Build docs artifact with Verific #1: Commit 120f69e pushed by akashlevy
September 4, 2024 07:02 5h 10m 47s main
main
September 4, 2024 07:02 5h 10m 47s