From 60e598b9c8ab715b9c26ba999759a65e476c55c6 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Fri, 17 May 2024 04:46:28 -0700 Subject: [PATCH] Define SYNTHESIS earlier and in both, support ignored module specification --- frontends/verific/verific.cc | 16 +++++++++++----- verific | 2 +- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5256cf9f8a4..72ddbed3857 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3394,8 +3394,13 @@ struct VerificPass : public Pass { unsigned verilog_mode = veri_file::SYSTEM_VERILOG; const char* arg = args[argidx].c_str(); + // Define macros + hdl_file_sort::DefineMacro("SYNTHESIS"); + veri_file::DefineMacro("SYNTHESIS"); + // Ignore translate_off statements hdl_file_sort::SetIgnoreTranslateOff(0); + veri_file::SetIgnoreTranslateOff(0); // Treat .v as SystemVerilog too (overriding default behavior to treat it as VERILOG_2000) hdl_file_sort::RemoveFileExt(".v"); @@ -3468,6 +3473,12 @@ struct VerificPass : public Pass { log("AUTO-DISCOVER: registered file %s from .f file processing\n", file_name); } delete file_names; + } else if (args[argidx] == "-i") { + const char *ignore_module = args[++argidx].c_str(); + log("AUTO-DISCOVER: ignoring module %s\n", ignore_module); + veri_file::AddToIgnoredModuleNames(ignore_module); + veri_file::AddToIgnoredParsedModuleNames(ignore_module); + hdl_file_sort::RegisterIgnoreUnitName(ignore_module); } else { veri_file::AddIncludeDir(args[argidx].c_str()); if (!hdl_file_sort::RegisterDir(args[argidx].c_str())) { @@ -3478,11 +3489,6 @@ struct VerificPass : public Pass { } } - // Define macros - hdl_file_sort::DefineMacro("YOSYS"); - hdl_file_sort::DefineMacro("VERIFIC"); - hdl_file_sort::DefineMacro("SYNTHESIS"); - // Analyze discovered/sorted files if (!analyze_function(veri_file::MFCU)) { verific_error_msg.clear(); diff --git a/verific b/verific index 28f79dbcfa0..9f13ecc2e1f 160000 --- a/verific +++ b/verific @@ -1 +1 @@ -Subproject commit 28f79dbcfa0d0a96a9fe02f7ed075df7f48682a6 +Subproject commit 9f13ecc2e1f265ee03a3548d11c68e290e7ec4bf