From 7d980337e52cac2795b1f2d7121ccf2607d41853 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Mon, 12 Feb 2024 16:45:30 +0100
Subject: [PATCH] Bring VexRiscvLitexSmpClusterOpenSbi sim back to a functional
 state

---
 .../demo/smp/VexRiscvSmpLitexCluster.scala    | 46 ++++++++++++-------
 1 file changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 9a8aefe8..30c4c0ad 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -252,12 +252,13 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
 ////addAttribute("""mark_debug = "true"""")
 object VexRiscvLitexSmpClusterOpenSbi extends App{
   import spinal.core.sim._
+  Handle.loadHandleAsync = true
 
   val simConfig = SimConfig
-  simConfig.withWave
+  simConfig.withFstWave
   simConfig.allOptimisation
 
-  val cpuCount = 2
+  val cpuCount = 1
 
   def parameter = VexRiscvLitexSmpClusterParameter(
     cluster = VexRiscvSmpClusterParameter(
@@ -265,14 +266,15 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
         vexRiscvConfig(
           hartId = hartId,
           ioRange =  address => address(31 downto 28) === 0xF,
-          resetVector = 0x80000000l
+          resetVector = 0x40f00000l,
+          rvc = true
         )
       },
       withExclusiveAndInvalidation = true,
       jtagHeaderIgnoreWidth = 0
     ),
     liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
-    liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
+    liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
     coherentDma = false,
     wishboneMemory = false,
     cpuPerFpu = 4,
@@ -305,12 +307,24 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
   
   simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
     dut.body.debugCd.inputClockDomain.get.forkStimulus(10)
+    fork{
+      sleep(20)
+      dut.body.debugCd.inputClockDomain.clockToggle()
+      sleep(20)
+      dut.body.debugCd.inputClockDomain.clockToggle()
+    }
 
     val ram = SparseMemory()
-    ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
-    ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
-    ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
-    ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
+    val dist = "/media/data2/proj/upstream/nuttex/test1/dist"
+//    ram.write(0x80000000l, Seq(0xb7, 0x0f, 0x00, 0x40, 0xe7, 0x80, 0x0f,0x00).map(_.toByte).toArray)  //Seq(0x80000fb7, 0x000f80e7)
+    ram.loadBin(0xC00000, dist + "/romfs.img")
+    ram.loadBin(0x0000000, dist + "/nuttx.bin")
+    ram.loadBin(0xf00000, dist + "/opensbi.bin")
+
+//    ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
+//    ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
+//    ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
+//    ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
 
 
     dut.body.iBridge.dram.simSlave(ram, dut.body.debugCd.inputClockDomain)
@@ -328,13 +342,13 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
       }
     }
 
-    fork{
-      while(true) {
-        disableSimWave()
-        sleep(100000 * 10)
-        enableSimWave()
-        sleep(  100 * 10)
-      }
-    }
+//    fork{
+//      while(true) {
+//        disableSimWave()
+//        sleep(100000 * 10)
+//        enableSimWave()
+//        sleep(  100 * 10)
+//      }
+//    }
   }
 }
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