From 8c191a282458c09bcff48e67caff5a7c5661abd0 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 17 Jun 2024 10:04:12 +0200 Subject: [PATCH] Fix #412 tightly coupled HAS_SIDE_EFFECT fix --- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index ef59b490..16bb7e7b 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -473,7 +473,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, cache.io.cpu.memory.mmuRsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite) if(tightlyGen){ - when(input(MEMORY_TIGHTLY).orR){ + when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){ cache.io.cpu.memory.isValid := False input(HAS_SIDE_EFFECT) := False } @@ -585,7 +585,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, insert(MEMORY_LOAD_DATA) := rspShifted if(tightlyGen){ - when(input(MEMORY_TIGHTLY).orR){ + when(input(MEMORY_ENABLE) && input(MEMORY_TIGHTLY).orR){ cache.io.cpu.writeBack.isValid := False exceptionBus.valid := False redoBranch.valid := False