diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 72ae96f398..1cec07ca24 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 184679 + gates: 185674 diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 355531d453..d9241c3843 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -7,6 +7,7 @@ version: 2 submodules: include: - docs/riscv-isa/riscv-isa-manual + recursive: true build: os: "ubuntu-20.04" @@ -26,7 +27,7 @@ build: - npm install docs/riscv-isa/riscv-isa-manual/dependencies - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile pre_build: - - make -C docs prepare + - PATH=$PWD/node_modules/.bin:$PATH make -C docs prepare # Build from the docs directory with Sphinx sphinx: diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 724dfed904..acb6986c47 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -2424,7 +2424,7 @@ module csr_regfile unique case (conv_csr_addr.address) riscv::CSR_MIP: - csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT); + csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); // in supervisor mode we also need to check whether we delegated this bit riscv::CSR_SIP: begin if (CVA6Cfg.RVS) begin diff --git a/core/cva6.sv b/core/cva6.sv index d395b4f5ca..e898f50108 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1731,6 +1731,7 @@ module cva6 .wdata_i (wdata_commit_id), .csr_i(rvfi_csr), + .irq_i(irq_i), .rvfi_probes_o(rvfi_probes_o) diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 5e06e26295..cf23813c29 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -51,6 +51,7 @@ module cva6_rvfi_probes input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i, input rvfi_probes_csr_t csr_i, + input logic [1:0] irq_i, output rvfi_probes_t rvfi_probes_o ); @@ -109,6 +110,7 @@ module cva6_rvfi_probes instr.wdata = wdata_i; csr = csr_i; + csr.mip_q = csr_i.mip_q | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); end diff --git a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc index 4290a1372e..cfdfdf8607 100644 --- a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc +++ b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc @@ -61,57 +61,71 @@ Supported Parameters The following table presents CVXIF parameters supported by CVA6. -[cols=",,",options="header",] +[cols=",a,a",options="header",] |============================================= |Signal |Value |Description -|*X_NUM_RS* |int: 2 or 3 (configurable) a| +|*X_NUM_RS* | +int: 2 or 3 (configurable) + + +* CV32A60X: 2 +* CV32A65X: 2 +| [verse] -- Number of register file read ports that can be used by the eXtension interface -- - | -|*X_ID_WIDTH* |int: 3 a| +|*X_ID_WIDTH* | +int: 1 to 32 + + +* CV32A60X: 2 +* CV32A65X: 3 +| [verse] -- Identification width for the eXtension interface -- - | -|*X_MEM_WIDTH* |n/a (feature not supported) a| +|*X_MEM_WIDTH* |n/a (feature not supported) | [verse] -- Memory access width for loads/stores via the eXtension interface -- - | -|*X_RFR_WIDTH* |int: `XLEN` (32 or 64) a| +|*X_RFR_WIDTH* | +int: `XLEN` (32 or 64) + + +* CV32A60X: 32 +* CV32A65X: 32 +| [verse] -- Register file read access width for the eXtension interface -- - | -|*X_RFW_WIDTH* |int: `XLEN` (32 or 64) a| +|*X_RFW_WIDTH* | +int: `XLEN` (32 or 64) + + +* CV32A60X: 32 +* CV32A65X: 32 +| [verse] -- Register file write access width for the eXtension interface -- - | -|*X_MISA* |logic[31:0]: 0x0000_0000 a| +|*X_MISA* |logic[31:0]: 0x0000_0000 | [verse] -- MISA extensions implemented on the eXtension interface -- - | |============================================= [[cv-x-if-enabling]] diff --git a/docs/requirements.txt b/docs/requirements.txt index a77aa8cf7d..d9cbc647a1 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -3,3 +3,9 @@ sphinx-rtd-theme recommonmark sphinxcontrib-svg2pdfconverter sphinx_github_changelog + +# for gen_from_riscv_config +mako +mdutils +pyyaml +rstcloth diff --git a/docs/riscv-isa/riscv-isa-manual b/docs/riscv-isa/riscv-isa-manual index 2c07aa2bcc..4f277ff8ea 160000 --- a/docs/riscv-isa/riscv-isa-manual +++ b/docs/riscv-isa/riscv-isa-manual @@ -1 +1 @@ -Subproject commit 2c07aa2bcc02fd5fb2e53e42a32dc62a3eb0aa62 +Subproject commit 4f277ff8ea8c0fc9394dfccd1da0ace34b1aef68 diff --git a/docs/riscv-isa/src/colophon.adoc b/docs/riscv-isa/src/colophon.adoc index d05ee78be3..d5d1e07c45 100644 --- a/docs/riscv-isa/src/colophon.adoc +++ b/docs/riscv-isa/src/colophon.adoc @@ -7,7 +7,7 @@ This document describes the RISC-V unprivileged architecture tailored for OpenHW Group {ohg-config}. -[.big]*_Preface to Document Version 20241017_* +[.big]*_Preface to Document Version 20241101_* This document describes the RISC-V unprivileged architecture. diff --git a/docs/riscv-isa/src/machine.adoc b/docs/riscv-isa/src/machine.adoc index ceb8e904a0..1f647106c7 100644 --- a/docs/riscv-isa/src/machine.adoc +++ b/docs/riscv-isa/src/machine.adoc @@ -226,10 +226,17 @@ supervisor modes respectively. The "X" bit will be set if there are any non-standard extensions. -When "B" bit is 1, the implementation supports the instructions provided by the -Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the +When the "B" bit is 1, the implementation supports the instructions provided by the +Zba, Zbb, and Zbs extensions. When the "B" bit is 0, it indicates that the implementation may not support one or more of the Zba, Zbb, or Zbs extensions. +When the "M" bit is 1, the implementation supports all multiply and +division instructions defined by the M extension. When the "M" bit +is 0, it indicates that the implementation may not support those +instructions. However if the Zmmul extension is supported then +the multiply instructions it specifies are supported irrespective +of the value of the "M" bit. + ifeval::[{note} == true] [NOTE] ==== @@ -1554,7 +1561,7 @@ additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead. The SD bit is read-only and is set when either the FS, VS, or XS bits -encode a Dirty state (i.e., SD=((FS==11) OR (XS==11) OR (VS==11))). This +encode a Dirty state (i.e., `SD=(FS==0b11 OR XS==0b11 OR VS==0b11)`). This allows privileged code to quickly determine when no additional context save is required beyond the integer register set and `pc`. @@ -3865,7 +3872,9 @@ and I/O regions may be accessed with either _relaxed_ or _strong_ ordering. Accesses to an I/O region with relaxed ordering are generally observed by other harts and bus mastering devices in a manner similar to the ordering of accesses to an RVWMO memory region, as discussed in -Section A.4.2 in Volume I of this specification. By contrast, accesses +the I/O Ordering section in the RVWMO Explanatory Material appendix +of Volume I of this specification. +By contrast, accesses to an I/O region with strong ordering are generally observed by other harts and bus mastering devices in program order. diff --git a/docs/riscv-isa/src/mm-formal.adoc b/docs/riscv-isa/src/mm-formal.adoc new file mode 100644 index 0000000000..200edb8feb --- /dev/null +++ b/docs/riscv-isa/src/mm-formal.adoc @@ -0,0 +1,7 @@ +[appendix] +== Formal Memory Model Specifications, Version 0.1 +[[mm-formal]] + +ifeval::["{ohg-config}" == "CV32A65X"] +{ohg-config}: No RVWMO memory model. +endif::[] diff --git a/docs/riscv-isa/src/priv-preface.adoc b/docs/riscv-isa/src/priv-preface.adoc index c971911fb3..38dc7ce812 100644 --- a/docs/riscv-isa/src/priv-preface.adoc +++ b/docs/riscv-isa/src/priv-preface.adoc @@ -6,6 +6,98 @@ This document describes the RISC-V privileged architecture tailored for OpenHW Group {ohg-config}. +[.big]*_Preface to Version 20241101_* + +This document describes the RISC-V privileged architecture. This +release, version 20241101, contains the following versions of the RISC-V ISA +modules: + +[%autowidth,float="center",align="center",cols="^,<,^",options="header",] +|=== +|Module |Version |Status +|_Machine ISA_ + +*Smstateen Extension* + +*Smcsrind/Sscsrind Extension* + +*Smepmp Extension* + +*Smcntrpmf Extension* + +*Smrnmi Extension* + +*Smcdeleg Extension* + +*Smdbltrp Extension* + +_Supervisor ISA_ + +*Svade Extension* + +*Svnapot Extension* + +*Svpbmt Extension* + +*Svinval Extension* + +*Svadu Extension* + +*Sstc Extension* + +*Sscofpmf Extension* + +*Ssdbltrp Extension* + +*Ssqosid Extension* + +*Hypervisor ISA* + +*Shlcofideleg Extension* + +*Svvptc Extension* + +|_1.14_ + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +_1.14_ + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +|_Draft_ + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +_Draft_ + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* +|=== + +The following changes have been made since version 1.13 of the Machine and +Supervisor ISAs, which, while not strictly backwards compatible, are not +anticipated to cause software portability problems in practice: + +* (None yet) + +Additionally, the following compatible changes have been +made to the Machine and Supervisor ISAs since version 1.13: + +* Defined the `mstateen0` P1P14 field. + +Finally, the following clarifications and document improvements have been made +since the last document release: + +* (None yet) + [.big]*_Preface to Version 20241017_* This document describes the RISC-V privileged architecture. This diff --git a/docs/riscv-isa/src/riscv-privileged.adoc b/docs/riscv-isa/src/riscv-privileged.adoc index bc8d53217e..07b28a33be 100644 --- a/docs/riscv-isa/src/riscv-privileged.adoc +++ b/docs/riscv-isa/src/riscv-privileged.adoc @@ -4,8 +4,8 @@ include::config.adoc[] = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture include::../docs-resources/global-config.adoc[] :description: Volume II - Privileged Architecture -:revnumber: 20241017 -:revremark: This document is in Ratified state. +:revnumber: 20241101 +//:revremark: This document is in Ratified state. //development: assume everything can change //stable: assume everything could change //frozen: of you implement this version you assume the risk that something might change because of the public review cycle but we expect little to no change. @@ -22,7 +22,7 @@ include::../docs-resources/global-config.adoc[] // Settings: :experimental: :reproducible: -:imagesoutdir: images +:imagesoutdir: {docdir}/../build/images-out :bibtex-file: src/resources/riscv-spec.bib :bibtex-order: alphabetical :bibtex-style: apa @@ -100,6 +100,7 @@ include::smcntrpmf.adoc[] include::rnmi.adoc[] include::smcdeleg.adoc[] include::smdbltrp.adoc[] +include::smctr.adoc[] include::supervisor.adoc[] include::sstc.adoc[] include::sscofpmf.adoc[] diff --git a/docs/riscv-isa/src/riscv-unprivileged.adoc b/docs/riscv-isa/src/riscv-unprivileged.adoc index c9c5bb8861..01e7c37708 100644 --- a/docs/riscv-isa/src/riscv-unprivileged.adoc +++ b/docs/riscv-isa/src/riscv-unprivileged.adoc @@ -4,7 +4,7 @@ include::config.adoc[] = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture include::../docs-resources/global-config.adoc[] :description: Unprivileged Architecture -:revnumber: 20241017 +:revnumber: 20241101 //:revremark: Pre-release version :colophon: :preface-title: Preamble @@ -19,7 +19,7 @@ include::../docs-resources/global-config.adoc[] // Settings: :experimental: :reproducible: -:imagesoutdir: images +:imagesoutdir: {docdir}/../build/images-out :bibtex-file: src/resources/riscv-spec.bib :bibtex-order: alphabetical :bibtex-style: apa diff --git a/docs/riscv-isa/src/rv64.adoc b/docs/riscv-isa/src/rv64.adoc index 38c52e66c7..06d844396c 100644 --- a/docs/riscv-isa/src/rv64.adoc +++ b/docs/riscv-isa/src/rv64.adoc @@ -205,6 +205,10 @@ no standard HINTs will ever be defined in this subspace. (_rs2_=_x4_) NTL.S1 + (_rs2_=_x5_) NTL.ALL +|SLLI |_rd_=`x0`, _rs1_=`x0`, _shamt_=31 |1|Semihosting entry marker + +|SRAI |_rd_=`x0`, _rs1_=`x0`, _shamt_=7 |1|Semihosting exit marker + |SUB |_rd_=_x0_ |latexmath:[$2^{10}$] .16+.^| _Designated for future standard use_ |AND |_rd_=_x0_ |latexmath:[$2^{10}$] @@ -243,11 +247,11 @@ no standard HINTs will ever be defined in this subspace. |SLTIU |_rd_=_x0_ |latexmath:[$2^{17}$] -|SLLI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SLLI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠31 |latexmath:[$2^{11}-1$] -|SRLI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SRLI |_rd_=`x0` |latexmath:[$2^{11}$] -|SRAI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SRAI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠7 |latexmath:[$2^{11}-1$] |SLLIW |_rd_=_x0_ |latexmath:[$2^{10}$] diff --git a/docs/riscv-isa/src/scalar-crypto.adoc b/docs/riscv-isa/src/scalar-crypto.adoc index a62f39cac9..32f1bd4633 100644 --- a/docs/riscv-isa/src/scalar-crypto.adoc +++ b/docs/riscv-isa/src/scalar-crypto.adoc @@ -1,4 +1,4 @@ -[[scalar-crypto]] +[[crypto_scalar_instructions]] == Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 ifeval::[{RVZk} == false] diff --git a/docs/riscv-isa/src/smctr.adoc b/docs/riscv-isa/src/smctr.adoc new file mode 100644 index 0000000000..36407608d3 --- /dev/null +++ b/docs/riscv-isa/src/smctr.adoc @@ -0,0 +1,7 @@ +[[smctr]] + +== "Smctr" Control Transfer Records Extension, Version 1.0 + +ifeval::[{RVZsmctr} == false] +{ohg-config}: This extension is not supported. +endif::[] diff --git a/docs/riscv-isa/src/supervisor.adoc b/docs/riscv-isa/src/supervisor.adoc index 697cbf541f..cbb545405c 100644 --- a/docs/riscv-isa/src/supervisor.adoc +++ b/docs/riscv-isa/src/supervisor.adoc @@ -45,7 +45,7 @@ supervisor-level CSR descriptions. endif::[] [[sstatus]] -==== Supervisor Status (`sstatus`) Register +==== Supervisor Status (`sstatus`) Register ifdef::archi-default[] The `sstatus` register is an SXLEN-bit read/write register formatted as @@ -360,7 +360,7 @@ ifndef::archi-default,RVZssdbltrp-true[] SDT field is read-only 0. endif::[] -==== Supervisor Trap Vector Base Address (`stvec`) Register +==== Supervisor Trap Vector Base Address (`stvec`) Register The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a @@ -382,7 +382,7 @@ field. |Value |Name |Description |0 + 1 + -≥2 +≥2 |Direct + Vectored |All exceptions set `pc` to BASE. + @@ -401,7 +401,7 @@ supervisor-mode timer interrupt (see <>) causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may impose a stricter alignment constraint on BASE. -==== Supervisor Interrupt (`sip` and `sie`) Registers +==== Supervisor Interrupt (`sip` and `sie`) Registers The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding @@ -528,7 +528,7 @@ the counter values. The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`. -==== Counter-Enable (`scounteren`) Register +==== Counter-Enable (`scounteren`) Register .Counter-enable (`scounteren`) register include::images/bytefield/scounteren.edn[] @@ -560,13 +560,15 @@ access a counter if the corresponding bits in `scounteren` and ==== endif::[] -==== Supervisor Scratch (`sscratch`) Register +==== Supervisor Scratch (`sscratch`) Register The `sscratch` CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, `sscratch` is used to hold a pointer to the hart-local supervisor context while the hart is executing -user code. At the beginning of a trap handler, `sscratch` is swapped -with a user register to provide an initial working register. +user code. +At the beginning of a trap handler, software normally uses a CSRRW +instruction to swap `sscratch` with an integer register to obtain an +initial working register. .Supervisor Scratch Register include::images/bytefield/sscratch.edn[] @@ -600,7 +602,7 @@ though it may be explicitly written by software. include::images/bytefield/epcreg.edn[] [[scause]] -==== Supervisor Cause (`scause`) Register +==== Supervisor Cause (`scause`) Register The `scause` CSR is an SXLEN-bit read-write register formatted as shown in <>. When a trap is taken into @@ -654,7 +656,7 @@ Supervisor external interrupt + _Reserved_ + Counter-overflow interrupt + _Reserved_ + -_Designated for platform use_ +_Designated for platform use_ |0 + 0 + @@ -721,7 +723,7 @@ _Reserved_ + _Designated for custom use_ + _Reserved_ + _Designated for custom use_ + -_Reserved_ +_Reserved_ |=== ==== Supervisor Trap Value (`stval`) Register @@ -795,7 +797,7 @@ ifndef::archi-default,MTvalEn-true[] endif::[] [[sec:senvcfg]] -==== Supervisor Environment Configuration (`senvcfg`) Register +==== Supervisor Environment Configuration (`senvcfg`) Register The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in <>, that controls certain @@ -1736,14 +1738,24 @@ A virtual address _va_ is translated into a physical address _pa_ as follows: . Let _a_ be ``satp``.__ppn__×PAGESIZE, and let __i__=LEVELS-1. (For Sv32, PAGESIZE=2^12^ and LEVELS=2.) The `satp` register must be _active_, i.e., the effective privilege mode must be S-mode or U-mode. + . Let _pte_ be the value of the PTE at address __a__+__va__.__vpn__[__i__]×PTESIZE. (For Sv32, PTESIZE=4.) If accessing _pte_ violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type. + . If _pte_._v_=0, or if _pte_._r_=0 and _pte_._w_=1, or if any bits or encodings that are reserved for future standard use are set within _pte_, stop and raise a page-fault exception corresponding to the original access type. + . Otherwise, the PTE is valid. If __pte__.__r__=1 or __pte__.__x__=1, go to step 5. Otherwise, this PTE is a pointer to the next level of the page table. Let __i=i__-1. If __i__<0, stop and raise a page-fault exception corresponding to the original access type. Otherwise, let __a__=__pte__.__ppn__×PAGESIZE and go to step 2. -. A leaf PTE has been found. Determine if the requested memory access is -allowed by the _pte_._r_, _pte_._w_, _pte_._x_, and _pte_._u_ bits, given the current privilege mode and the value of the SUM and MXR fields of the `mstatus` register. If not, stop and raise a page-fault exception corresponding to the original access type. -. If _i>0_ and _pte_._ppn_[__i__-1:0] ≠ 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type. + +. A leaf PTE has been reached. If _i>0_ and _pte_._ppn_[__i__-1:0] ≠ 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type. + +. Determine if the requested memory access is allowed by the _pte_._u_ bit, given the current privilege mode and the value of the SUM and MXR fields of the *mstatus* register. If not, stop and raise a page-fault exception corresponding to the original access type. + +. Determine if the requested memory access is allowed by the _pte_._r_, _pte_._w_, and _pte_._x_ bits, given the Shadow Stack Memory Protection rules. If not, stop and raise an access-fault exception. + +. Determine if the requested memory access is allowed by the _pte_._r_, _pte_._w_, and _pte_._x_ bits. If not, stop and raise a page-fault exception corresponding to the original access type. + . If _pte_._a_=0, or if the original memory access is a store and _pte_._d_=0: + * If the Svade extension is implemented, stop and raise a page-fault exception corresponding to the original access type. * If a store to _pte_ would violate a PMA or PMP check, raise an access-fault exception corresponding to the original access @@ -1753,6 +1765,7 @@ type. ** If the values match, set _pte_._a_ to 1 and, if the original memory access is a store, also set _pte_._d_ to 1. ** If the comparison fails, return to step 2. + . The translation is successful. The translated physical address is given as follows: * _pa.pgoff_ = _va.pgoff_. @@ -2224,7 +2237,7 @@ __vpn__[__i__][__pte__.__napot_bits__-1:0]. If the encoding in _pte_ is reserved <>, then a page-fault exception must be raised. * Implicit reads of NAPOT page table entries may create address-translation cache entries mapping -_a_ + _j_×PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] +_a_ + _j_×PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] is replaced by _vpn[i][pte.napot_bits_-1:0], for any or all _j_ such that __j__ >> __napot_bits__ = __vpn__[__i__] >> __napot_bits__, all for the address space identified in _satp_ as loaded by step 1. endif::[] @@ -2322,7 +2335,7 @@ __ 1 + 2 + ... -|=== +|=== In such a case, an implementation may or may not support all options. The discoverability mechanism for this extension would be extended to @@ -2625,8 +2638,7 @@ coherent with store instructions that modify PTEs. ==== endif::[] -//// -[[sec:ssqosid]] +[[ssqosid]] == "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 Quality of Service (QoS) is defined as the minimal end-to-end performance @@ -2708,11 +2720,11 @@ modes of software execution on that hart by default, but this behavior may be overridden by future extensions. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also -requires the bit 55 in `mstateen0` introduced by Priv 1.14 to be implemented. If -bit 55 of `mstateen0` is 0, attempts to access `srmcfg` in privilege modes less -privileged than M-mode raise an illegal-instruction exception. If bit 55 of -`mstateen0` is 1 or if extension Smstateen is not implemented, attempts to -access `srmcfg` when `V=1` raise a virtual-instruction exception. +requires the P1P14 bit in `mstateen0` to be implemented. +If P1P14 of `mstateen0` is 0, attempts to access `srmcfg` in privilege modes +less privileged than M-mode raise an illegal-instruction exception. +If P1P14 bit of `mstateen0` is 1 or if extension Smstateen is not implemented, +attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception. [NOTE] ==== @@ -2748,6 +2760,4 @@ the new context, it switches to the new VM's `srmcfg`. The supervisor can also use a separate configuration for execution not to be attributed to either contexts. ==== -//// - endif::[] diff --git a/docs/scripts/spec_builder.py b/docs/scripts/spec_builder.py index b76e0fd753..31c47ea86c 100755 --- a/docs/scripts/spec_builder.py +++ b/docs/scripts/spec_builder.py @@ -58,6 +58,7 @@ 'RVZicbo': False, 'RVZicfilp': False, 'RVZpm': False, + 'RVZsmctr': False, 'RVZsmepmp': False, 'RVZsmmpm': False, 'RVZsmrnmi': False, diff --git a/verif/core-v-verif b/verif/core-v-verif index 19b5a3f94d..60e57248c4 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 19b5a3f94d9b091701f020146072dd214b93d34d +Subproject commit 60e57248c48b0f8f90cf52af20aecc5c16e9d6d8