From 7450448c9d57ad74a9ea06cef7e3613f1f81778f Mon Sep 17 00:00:00 2001
From: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Date: Tue, 14 Jan 2025 17:31:43 +0100
Subject: [PATCH] CleanUp: Remove latch in cva6_fifo_v3 added in #2592

---
 core/cva6_fifo_v3.sv | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv
index d1d7e21162..cf7bb16ea2 100644
--- a/core/cva6_fifo_v3.sv
+++ b/core/cva6_fifo_v3.sv
@@ -77,13 +77,20 @@ module cva6_fifo_v3 #(
     read_pointer_n  = read_pointer_q;
     write_pointer_n = write_pointer_q;
     status_cnt_n    = status_cnt_q;
-    data_ft_n = data_ft_q;
-    first_word_n = first_word_q;
+    if (FPGA_EN && FPGA_ALTERA) data_ft_n = data_ft_q;
+    if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q;
     if (FPGA_EN) begin
       fifo_ram_we            = '0;
       fifo_ram_write_address = '0;
       fifo_ram_wdata         = '0;
-      data_o                 = (DEPTH == 0) ? data_i : (first_word_q ? data_ft_q : fifo_ram_rdata);
+      if (DEPTH == 0) begin
+        data_o = data_i;
+      end else begin
+        if (FPGA_ALTERA)
+          data_o = first_word_q ? data_ft_q : fifo_ram_rdata;
+        else
+          data_o = fifo_ram_rdata;
+      end
     end else begin
       data_o     = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
       mem_n      = mem_q;
@@ -96,7 +103,7 @@ module cva6_fifo_v3 #(
         fifo_ram_we = 1'b1;
         fifo_ram_write_address = write_pointer_q;
         fifo_ram_wdata = data_i;
-        first_word_n = FPGA_ALTERA && first_word_q && pop_i;
+        if (FPGA_ALTERA) first_word_n = first_word_q && pop_i;
       end else begin
         // push the data onto the queue
         mem_n[write_pointer_q] = data_i;
@@ -113,7 +120,7 @@ module cva6_fifo_v3 #(
 
     if (pop_i && ~empty_o) begin
       data_ft_n = data_i;
-      first_word_n = FPGA_EN && FPGA_ALTERA && first_word_q && push_i;
+      if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q && push_i;
       // read from the queue is a default assignment
       // but increment the read pointer...
       if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0;
@@ -151,8 +158,8 @@ module cva6_fifo_v3 #(
       read_pointer_q  <= '0;
       write_pointer_q <= '0;
       status_cnt_q    <= '0;
-      first_word_q <= '0;
-      data_ft_q <= '0;
+      if (FPGA_ALTERA) first_word_q <= '0;
+      if (FPGA_ALTERA) data_ft_q <= '0;
     end else begin
       if (flush_i) begin
         read_pointer_q  <= '0;