From 10e2d65b9ada72b62f4abc9b1f4100418c9d6705 Mon Sep 17 00:00:00 2001
From: Martin Schoeberl <martin@jopdesign.com>
Date: Tue, 5 Nov 2024 15:11:47 -0800
Subject: [PATCH] Chisel instead of Verilog

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 69c42910..f12b8d88 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 
 ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+# Tiny Tapeout Chisel Project Template
 
 - [Read the documentation for project](docs/info.md)