From d78e1ffa8af1cfdae4c778e72b0462a1926e5437 Mon Sep 17 00:00:00 2001 From: Andreu Carminati Date: Mon, 3 Feb 2025 16:06:01 +0000 Subject: [PATCH] [AIE2P] Select VLD FIFO pseudo instructions --- .../AIE/aie2p/AIE2PInstructionSelector.cpp | 26 +++--- .../GlobalIsel/inst-select-fifo-loads.mir | 84 +++++++++---------- llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll | 40 ++++----- 3 files changed, 75 insertions(+), 75 deletions(-) diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp index 36b1199c4c22..f33696eea8be 100644 --- a/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp +++ b/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp @@ -2550,31 +2550,31 @@ bool AIE2PInstructionSelector::selectG_STORE(MachineInstr &I, unsigned getLoadFifoOpcode(MachineInstr &I) { switch (cast(I).getIntrinsicID()) { case Intrinsic::aie2p_fifo_ld_fill: - return AIE2P::VLDB_FILL_512; + return AIE2P::VLD_FILL_512_pseudo; case Intrinsic::aie2p_fifo_ld_pop_unaligned: - return AIE2P::VLDB_POP_512_normal_pop; + return AIE2P::VLD_POP_512_normal_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_1d_unaligned: - return AIE2P::VLDB_POP_512_fifo_1d_pop; + return AIE2P::VLD_POP_512_fifo_1d_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_544_1d_bfp16: - return AIE2P::VLDB_POP_544_fifo_1d_pop; + return AIE2P::VLD_POP_544_fifo_1d_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_576_1d_bfp16: - return AIE2P::VLDB_POP_576_fifo_1d_pop; + return AIE2P::VLD_POP_576_fifo_1d_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_544_bfp16: - return AIE2P::VLDB_POP_544_normal_pop; + return AIE2P::VLD_POP_544_normal_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_576_bfp16: - return AIE2P::VLDB_POP_576_normal_pop; + return AIE2P::VLD_POP_576_normal_pop_pseudo; case Intrinsic::aie2p_fifo_ld_pop_2d_unaligned: - return AIE2P::VLDB_POP_512_2D; + return AIE2P::VLD_POP_512_2D_pseudo; case Intrinsic::aie2p_fifo_ld_pop_3d_unaligned: - return AIE2P::VLDB_POP_512_3D; + return AIE2P::VLD_POP_512_3D_pseudo; case Intrinsic::aie2p_fifo_ld_pop_544_2d_bfp16: - return AIE2P::VLDB_POP_544_2D; + return AIE2P::VLD_POP_544_2D_pseudo; case Intrinsic::aie2p_fifo_ld_pop_576_2d_bfp16: - return AIE2P::VLDB_POP_576_2D; + return AIE2P::VLD_POP_576_2D_pseudo; case Intrinsic::aie2p_fifo_ld_pop_544_3d_bfp16: - return AIE2P::VLDB_POP_544_3D; + return AIE2P::VLD_POP_544_3D_pseudo; case Intrinsic::aie2p_fifo_ld_pop_576_3d_bfp16: - return AIE2P::VLDB_POP_576_3D; + return AIE2P::VLD_POP_576_3D_pseudo; } llvm_unreachable("unreachable: Failed to get sparse load opcode"); return AIE2P::INSTRUCTION_LIST_END; diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir index 8a02b3526913..1b83173ac19f 100644 --- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir +++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir @@ -19,8 +19,8 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_FILL_512_:%[0-9]+]]:eps, [[VLDB_FILL_512_1:%[0-9]+]]:eldfiforeg, [[VLDB_FILL_512_2:%[0-9]+]]:erf2 = VLDB_FILL_512 [[DEF]], [[DEF1]], [[DEF2]] - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_FILL_512_]], implicit [[VLDB_FILL_512_1]], implicit [[VLDB_FILL_512_2]] + ; CHECK-NEXT: [[VLD_FILL_512_pseudo:%[0-9]+]]:eps, [[VLD_FILL_512_pseudo1:%[0-9]+]]:eldfiforeg, [[VLD_FILL_512_pseudo2:%[0-9]+]]:erf2 = VLD_FILL_512_pseudo [[DEF]], [[DEF1]], [[DEF2]] + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_FILL_512_pseudo]], implicit [[VLD_FILL_512_pseudo1]], implicit [[VLD_FILL_512_pseudo2]] %2:modregbank(s20) = G_IMPLICIT_DEF %4:ptrregbank(p0) = G_IMPLICIT_DEF %5:fiforegbank(<32 x s32>) = G_IMPLICIT_DEF @@ -41,8 +41,8 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_512_normal_pop:%[0-9]+]]:vec512, [[VLDB_POP_512_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_512_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_512_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_512_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_512_normal_pop]], implicit [[VLDB_POP_512_normal_pop1]], implicit [[VLDB_POP_512_normal_pop2]], implicit [[VLDB_POP_512_normal_pop3]] + ; CHECK-NEXT: [[VLD_POP_512_normal_pop_pseudo:%[0-9]+]]:vec512, [[VLD_POP_512_normal_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_512_normal_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_512_normal_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_512_normal_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_512_normal_pop_pseudo]], implicit [[VLD_POP_512_normal_pop_pseudo1]], implicit [[VLD_POP_512_normal_pop_pseudo2]], implicit [[VLD_POP_512_normal_pop_pseudo3]] %3:modregbank(s20) = G_IMPLICIT_DEF %5:ptrregbank(p0) = G_IMPLICIT_DEF %6:fiforegbank(<32 x s32>) = G_IMPLICIT_DEF @@ -63,10 +63,10 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_544_normal_pop:%[0-9]+]]:mexb, [[VLDB_POP_544_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_544_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_544_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_544_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_544_normal_pop]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_544_normal_pop]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_544_normal_pop1]], implicit [[VLDB_POP_544_normal_pop2]], implicit [[VLDB_POP_544_normal_pop3]], implicit [[COPY]], implicit [[COPY1]] + ; CHECK-NEXT: [[VLD_POP_544_normal_pop_pseudo:%[0-9]+]]:vec576, [[VLD_POP_544_normal_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_544_normal_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_544_normal_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_544_normal_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_544_normal_pop_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_544_normal_pop_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_544_normal_pop_pseudo1]], implicit [[VLD_POP_544_normal_pop_pseudo2]], implicit [[VLD_POP_544_normal_pop_pseudo3]], implicit [[COPY]], implicit [[COPY1]] %14:vregbank(<64 x s8>) = G_IMPLICIT_DEF %15:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %6:ptrregbank(p0) = G_IMPLICIT_DEF @@ -88,10 +88,10 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_576_normal_pop:%[0-9]+]]:mexb, [[VLDB_POP_576_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_576_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_576_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_576_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_576_normal_pop]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_576_normal_pop]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_576_normal_pop1]], implicit [[VLDB_POP_576_normal_pop2]], implicit [[VLDB_POP_576_normal_pop3]], implicit [[COPY]], implicit [[COPY1]] + ; CHECK-NEXT: [[VLD_POP_576_normal_pop_pseudo:%[0-9]+]]:vec576, [[VLD_POP_576_normal_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_576_normal_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_576_normal_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_576_normal_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_576_normal_pop_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_576_normal_pop_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_576_normal_pop_pseudo1]], implicit [[VLD_POP_576_normal_pop_pseudo2]], implicit [[VLD_POP_576_normal_pop_pseudo3]], implicit [[COPY]], implicit [[COPY1]] %14:vregbank(<64 x s8>) = G_IMPLICIT_DEF %15:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %6:ptrregbank(p0) = G_IMPLICIT_DEF @@ -114,8 +114,8 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_512_fifo_1d_pop:%[0-9]+]]:vec512, [[VLDB_POP_512_fifo_1d_pop1:%[0-9]+]]:eps, [[VLDB_POP_512_fifo_1d_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_512_fifo_1d_pop3:%[0-9]+]]:erf2 = VLDB_POP_512_fifo_1d_pop [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_512_fifo_1d_pop]], implicit [[VLDB_POP_512_fifo_1d_pop1]], implicit [[VLDB_POP_512_fifo_1d_pop2]], implicit [[VLDB_POP_512_fifo_1d_pop3]] + ; CHECK-NEXT: [[VLD_POP_512_fifo_1d_pop_pseudo:%[0-9]+]]:vec512, [[VLD_POP_512_fifo_1d_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_512_fifo_1d_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_512_fifo_1d_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_512_fifo_1d_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_512_fifo_1d_pop_pseudo]], implicit [[VLD_POP_512_fifo_1d_pop_pseudo1]], implicit [[VLD_POP_512_fifo_1d_pop_pseudo2]], implicit [[VLD_POP_512_fifo_1d_pop_pseudo3]] %6:ptrregbank(p0) = G_IMPLICIT_DEF %7:fiforegbank(<32 x s32>) = G_IMPLICIT_DEF %8:gprregbank(s32) = G_IMPLICIT_DEF @@ -137,10 +137,10 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_544_fifo_1d_pop:%[0-9]+]]:mexb, [[VLDB_POP_544_fifo_1d_pop1:%[0-9]+]]:eps, [[VLDB_POP_544_fifo_1d_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_544_fifo_1d_pop3:%[0-9]+]]:erf2 = VLDB_POP_544_fifo_1d_pop [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_544_fifo_1d_pop]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_544_fifo_1d_pop]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_544_fifo_1d_pop1]], implicit [[VLDB_POP_544_fifo_1d_pop2]], implicit [[VLDB_POP_544_fifo_1d_pop3]], implicit [[COPY]], implicit [[COPY1]] + ; CHECK-NEXT: [[VLD_POP_544_fifo_1d_pop_pseudo:%[0-9]+]]:vec576, [[VLD_POP_544_fifo_1d_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_544_fifo_1d_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_544_fifo_1d_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_544_fifo_1d_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_544_fifo_1d_pop_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_544_fifo_1d_pop_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_544_fifo_1d_pop_pseudo1]], implicit [[VLD_POP_544_fifo_1d_pop_pseudo2]], implicit [[VLD_POP_544_fifo_1d_pop_pseudo3]], implicit [[COPY]], implicit [[COPY1]] %16:vregbank(<64 x s8>) = G_IMPLICIT_DEF %17:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %7:ptrregbank(p0) = G_IMPLICIT_DEF @@ -165,10 +165,10 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF - ; CHECK-NEXT: [[VLDB_POP_576_fifo_1d_pop:%[0-9]+]]:mexb, [[VLDB_POP_576_fifo_1d_pop1:%[0-9]+]]:eps, [[VLDB_POP_576_fifo_1d_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_576_fifo_1d_pop3:%[0-9]+]]:erf2 = VLDB_POP_576_fifo_1d_pop [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_576_fifo_1d_pop]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_576_fifo_1d_pop]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_576_fifo_1d_pop1]], implicit [[VLDB_POP_576_fifo_1d_pop2]], implicit [[VLDB_POP_576_fifo_1d_pop3]], implicit [[COPY]], implicit [[COPY1]] + ; CHECK-NEXT: [[VLD_POP_576_fifo_1d_pop_pseudo:%[0-9]+]]:vec576, [[VLD_POP_576_fifo_1d_pop_pseudo1:%[0-9]+]]:eps, [[VLD_POP_576_fifo_1d_pop_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_576_fifo_1d_pop_pseudo3:%[0-9]+]]:erf2 = VLD_POP_576_fifo_1d_pop_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_576_fifo_1d_pop_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_576_fifo_1d_pop_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_576_fifo_1d_pop_pseudo1]], implicit [[VLD_POP_576_fifo_1d_pop_pseudo2]], implicit [[VLD_POP_576_fifo_1d_pop_pseudo3]], implicit [[COPY]], implicit [[COPY1]] %16:vregbank(<64 x s8>) = G_IMPLICIT_DEF %17:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %7:ptrregbank(p0) = G_IMPLICIT_DEF @@ -196,8 +196,8 @@ body: | ; CHECK-NEXT: [[DEF5:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:ed = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_512_2D:%[0-9]+]]:vec512, [[VLDB_POP_512_2D1:%[0-9]+]]:eps, [[VLDB_POP_512_2D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_512_2D3:%[0-9]+]]:erf2, [[VLDB_POP_512_2D4:%[0-9]+]]:edc = VLDB_POP_512_2D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_512_2D]], implicit [[VLDB_POP_512_2D1]], implicit [[VLDB_POP_512_2D2]], implicit [[VLDB_POP_512_2D3]], implicit [[VLDB_POP_512_2D4]] + ; CHECK-NEXT: [[VLD_POP_512_2D_pseudo:%[0-9]+]]:vec512, [[VLD_POP_512_2D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_512_2D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_512_2D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_512_2D_pseudo4:%[0-9]+]]:edc = VLD_POP_512_2D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_512_2D_pseudo]], implicit [[VLD_POP_512_2D_pseudo1]], implicit [[VLD_POP_512_2D_pseudo2]], implicit [[VLD_POP_512_2D_pseudo3]], implicit [[VLD_POP_512_2D_pseudo4]] %9:ptrregbank(p0) = G_IMPLICIT_DEF %10:fiforegbank(<32 x s32>) = G_IMPLICIT_DEF %11:gprregbank(s32) = G_IMPLICIT_DEF @@ -227,10 +227,10 @@ body: | ; CHECK-NEXT: [[DEF5:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:ed = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_544_2D:%[0-9]+]]:mexb, [[VLDB_POP_544_2D1:%[0-9]+]]:eps, [[VLDB_POP_544_2D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_544_2D3:%[0-9]+]]:erf2, [[VLDB_POP_544_2D4:%[0-9]+]]:edc = VLDB_POP_544_2D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_544_2D]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_544_2D]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLDB_POP_544_2D1]], implicit [[VLDB_POP_544_2D2]], implicit [[VLDB_POP_544_2D3]], implicit [[VLDB_POP_544_2D4]] + ; CHECK-NEXT: [[VLD_POP_544_2D_pseudo:%[0-9]+]]:vec576, [[VLD_POP_544_2D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_544_2D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_544_2D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_544_2D_pseudo4:%[0-9]+]]:edc = VLD_POP_544_2D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_544_2D_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_544_2D_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLD_POP_544_2D_pseudo1]], implicit [[VLD_POP_544_2D_pseudo2]], implicit [[VLD_POP_544_2D_pseudo3]], implicit [[VLD_POP_544_2D_pseudo4]] %24:vregbank(<64 x s8>) = G_IMPLICIT_DEF %25:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %10:ptrregbank(p0) = G_IMPLICIT_DEF @@ -262,10 +262,10 @@ body: | ; CHECK-NEXT: [[DEF5:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF6:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:ed = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_576_2D:%[0-9]+]]:mexb, [[VLDB_POP_576_2D1:%[0-9]+]]:eps, [[VLDB_POP_576_2D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_576_2D3:%[0-9]+]]:erf2, [[VLDB_POP_576_2D4:%[0-9]+]]:edc = VLDB_POP_576_2D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_576_2D]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_576_2D]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLDB_POP_576_2D1]], implicit [[VLDB_POP_576_2D2]], implicit [[VLDB_POP_576_2D3]], implicit [[VLDB_POP_576_2D4]] + ; CHECK-NEXT: [[VLD_POP_576_2D_pseudo:%[0-9]+]]:vec576, [[VLD_POP_576_2D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_576_2D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_576_2D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_576_2D_pseudo4:%[0-9]+]]:edc = VLD_POP_576_2D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_576_2D_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_576_2D_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLD_POP_576_2D_pseudo1]], implicit [[VLD_POP_576_2D_pseudo2]], implicit [[VLD_POP_576_2D_pseudo3]], implicit [[VLD_POP_576_2D_pseudo4]] %24:vregbank(<64 x s8>) = G_IMPLICIT_DEF %25:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %10:ptrregbank(p0) = G_IMPLICIT_DEF @@ -300,8 +300,8 @@ body: | ; CHECK-NEXT: [[DEF8:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF9:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:eds = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count, [[DEF7]], %subreg.sub_hi_dim_then_sub_dim_size, [[DEF9]], %subreg.sub_hi_dim_then_sub_dim_stride, [[DEF8]], %subreg.sub_hi_dim_then_sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_512_3D:%[0-9]+]]:vec512, [[VLDB_POP_512_3D1:%[0-9]+]]:eps, [[VLDB_POP_512_3D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_512_3D3:%[0-9]+]]:erf2, [[VLDB_POP_512_3D4:%[0-9]+]]:edcl, [[VLDB_POP_512_3D5:%[0-9]+]]:edch = VLDB_POP_512_3D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLDB_POP_512_3D]], implicit [[VLDB_POP_512_3D1]], implicit [[VLDB_POP_512_3D2]], implicit [[VLDB_POP_512_3D3]], implicit [[VLDB_POP_512_3D4]], implicit [[VLDB_POP_512_3D5]] + ; CHECK-NEXT: [[VLD_POP_512_3D_pseudo:%[0-9]+]]:vec512, [[VLD_POP_512_3D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_512_3D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_512_3D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_512_3D_pseudo4:%[0-9]+]]:edcl, [[VLD_POP_512_3D_pseudo5:%[0-9]+]]:edch = VLD_POP_512_3D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VLD_POP_512_3D_pseudo]], implicit [[VLD_POP_512_3D_pseudo1]], implicit [[VLD_POP_512_3D_pseudo2]], implicit [[VLD_POP_512_3D_pseudo3]], implicit [[VLD_POP_512_3D_pseudo4]], implicit [[VLD_POP_512_3D_pseudo5]] %12:ptrregbank(p0) = G_IMPLICIT_DEF %13:fiforegbank(<32 x s32>) = G_IMPLICIT_DEF %14:gprregbank(s32) = G_IMPLICIT_DEF @@ -336,10 +336,10 @@ body: | ; CHECK-NEXT: [[DEF8:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF9:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:eds = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count, [[DEF7]], %subreg.sub_hi_dim_then_sub_dim_size, [[DEF9]], %subreg.sub_hi_dim_then_sub_dim_stride, [[DEF8]], %subreg.sub_hi_dim_then_sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_544_3D:%[0-9]+]]:mexb, [[VLDB_POP_544_3D1:%[0-9]+]]:eps, [[VLDB_POP_544_3D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_544_3D3:%[0-9]+]]:erf2, [[VLDB_POP_544_3D4:%[0-9]+]]:edcl, [[VLDB_POP_544_3D5:%[0-9]+]]:edch = VLDB_POP_544_3D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_544_3D]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_544_3D]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[DEF9]], implicit [[VLDB_POP_544_3D1]], implicit [[VLDB_POP_544_3D2]], implicit [[VLDB_POP_544_3D3]], implicit [[VLDB_POP_544_3D4]], implicit [[VLDB_POP_544_3D5]] + ; CHECK-NEXT: [[VLD_POP_544_3D_pseudo:%[0-9]+]]:vec576, [[VLD_POP_544_3D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_544_3D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_544_3D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_544_3D_pseudo4:%[0-9]+]]:edcl, [[VLD_POP_544_3D_pseudo5:%[0-9]+]]:edch = VLD_POP_544_3D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_544_3D_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_544_3D_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[DEF9]], implicit [[VLD_POP_544_3D_pseudo1]], implicit [[VLD_POP_544_3D_pseudo2]], implicit [[VLD_POP_544_3D_pseudo3]], implicit [[VLD_POP_544_3D_pseudo4]], implicit [[VLD_POP_544_3D_pseudo5]] %32:vregbank(<64 x s8>) = G_IMPLICIT_DEF %33:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %13:ptrregbank(p0) = G_IMPLICIT_DEF @@ -376,10 +376,10 @@ body: | ; CHECK-NEXT: [[DEF8:%[0-9]+]]:edc = IMPLICIT_DEF ; CHECK-NEXT: [[DEF9:%[0-9]+]]:edj = IMPLICIT_DEF ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:eds = REG_SEQUENCE [[DEF3]], %subreg.sub_mod, [[DEF4]], %subreg.sub_dim_size, [[DEF6]], %subreg.sub_dim_stride, [[DEF5]], %subreg.sub_dim_count, [[DEF7]], %subreg.sub_hi_dim_then_sub_dim_size, [[DEF9]], %subreg.sub_hi_dim_then_sub_dim_stride, [[DEF8]], %subreg.sub_hi_dim_then_sub_dim_count - ; CHECK-NEXT: [[VLDB_POP_576_3D:%[0-9]+]]:mexb, [[VLDB_POP_576_3D1:%[0-9]+]]:eps, [[VLDB_POP_576_3D2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_576_3D3:%[0-9]+]]:erf2, [[VLDB_POP_576_3D4:%[0-9]+]]:edcl, [[VLDB_POP_576_3D5:%[0-9]+]]:edch = VLDB_POP_576_3D [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLDB_POP_576_3D]].sub_bfp16_x - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLDB_POP_576_3D]].sub_bfp16_e - ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLDB_POP_576_3D1]], implicit [[VLDB_POP_576_3D2]], implicit [[VLDB_POP_576_3D3]], implicit [[VLDB_POP_576_3D4]], implicit [[VLDB_POP_576_3D5]] + ; CHECK-NEXT: [[VLD_POP_576_3D_pseudo:%[0-9]+]]:vec576, [[VLD_POP_576_3D_pseudo1:%[0-9]+]]:eps, [[VLD_POP_576_3D_pseudo2:%[0-9]+]]:eldfiforeg, [[VLD_POP_576_3D_pseudo3:%[0-9]+]]:erf2, [[VLD_POP_576_3D_pseudo4:%[0-9]+]]:edcl, [[VLD_POP_576_3D_pseudo5:%[0-9]+]]:edch = VLD_POP_576_3D_pseudo [[DEF]], [[DEF1]], [[DEF2]], [[REG_SEQUENCE]], implicit-def $srfifo_uf + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY [[VLD_POP_576_3D_pseudo]].sub_bfp16_x + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:expvec64 = COPY [[VLD_POP_576_3D_pseudo]].sub_bfp16_e + ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY]], implicit [[COPY1]], implicit [[VLD_POP_576_3D_pseudo1]], implicit [[VLD_POP_576_3D_pseudo2]], implicit [[VLD_POP_576_3D_pseudo3]], implicit [[VLD_POP_576_3D_pseudo4]], implicit [[VLD_POP_576_3D_pseudo5]] %32:vregbank(<64 x s8>) = G_IMPLICIT_DEF %33:gprregbank(<8 x s8>) = G_IMPLICIT_DEF %13:ptrregbank(p0) = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll b/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll index e7f98db34fbb..5614eebfea32 100644 --- a/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll +++ b/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll @@ -20,7 +20,7 @@ define dso_local void @_Z17test_fifo_ld_fillRPDv64_DB8_R12fifo_state_t(ptr nocap ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64] ; CHECK-NEXT: vldb.fill.512 [p0, lf0, r24] @@ -32,7 +32,7 @@ define dso_local void @_Z17test_fifo_ld_fillRPDv64_DB8_R12fifo_state_t(ptr nocap ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -58,7 +58,7 @@ define dso_local noundef <64 x i8> @_Z16test_fifo_ld_popRPDv64_DB8_R12fifo_state ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64] ; CHECK-NEXT: vldb.pop.512 x0, [p0, lf0, r24] @@ -70,7 +70,7 @@ define dso_local noundef <64 x i8> @_Z16test_fifo_ld_popRPDv64_DB8_R12fifo_state ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -97,7 +97,7 @@ define dso_local noundef <64 x i8> @_Z24test_fifo_ld_pop_1d_byteRPDv64_DB8_R12fi ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov m0, r0 ; CHECK-NEXT: vldb.pop.512 x0, [p0, lf0, r24, m0] @@ -109,7 +109,7 @@ define dso_local noundef <64 x i8> @_Z24test_fifo_ld_pop_1d_byteRPDv64_DB8_R12fi ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -138,7 +138,7 @@ define dso_local noundef <64 x i8> @_Z24test_fifo_ld_pop_2d_byteRPDv64_DB8_R12fi ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: mov m0, r0 -; CHECK-NEXT: mov p3, p0 +; CHECK-NEXT: mov p4, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0]; mov dn0, r1 ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov dj0, r2 ; CHECK-NEXT: vldb.pop.512.2d x0, [p0, lf0, r24, d0] @@ -150,7 +150,7 @@ define dso_local noundef <64 x i8> @_Z24test_fifo_ld_pop_2d_byteRPDv64_DB8_R12fi ; CHECK-NEXT: st r24, [p1, dj1] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p4, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -242,7 +242,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z16test_fifo_ld_popRP22v64bfp16ebs8_unal ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64] ; CHECK-NEXT: vldb.pop.576 ex0, [p0, lf0, r24] @@ -254,7 +254,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z16test_fifo_ld_popRP22v64bfp16ebs8_unal ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -284,7 +284,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z24test_fifo_ld_pop_1d_byteRP22v64bfp16e ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov m0, r0 ; CHECK-NEXT: vldb.pop.576 ex0, [p0, lf0, r24, m0] @@ -296,7 +296,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z24test_fifo_ld_pop_1d_byteRP22v64bfp16e ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -328,7 +328,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z24test_fifo_ld_pop_2d_byteRP22v64bfp16e ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: mov m0, r0 -; CHECK-NEXT: mov p3, p0 +; CHECK-NEXT: mov p4, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0]; mov dn0, r1 ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov dj0, r2 ; CHECK-NEXT: vldb.pop.576.2d ex0, [p0, lf0, r24, d0] @@ -340,7 +340,7 @@ define dso_local %struct.v64bfp16ebs8 @_Z24test_fifo_ld_pop_2d_byteRP22v64bfp16e ; CHECK-NEXT: st r24, [p1, dj1] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p4, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -438,7 +438,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z16test_fifo_ld_popRP23v64bfp16ebs16_un ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64] ; CHECK-NEXT: vldb.pop.544 ex0, [p0, lf0, r24] @@ -450,7 +450,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z16test_fifo_ld_popRP23v64bfp16ebs16_un ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -480,7 +480,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z24test_fifo_ld_pop_1d_byteRP23v64bfp16 ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -; CHECK-NEXT: mov p2, p0 +; CHECK-NEXT: mov p3, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0] ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov m0, r0 ; CHECK-NEXT: vldb.pop.544 ex0, [p0, lf0, r24, m0] @@ -492,7 +492,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z24test_fifo_ld_pop_1d_byteRP23v64bfp16 ; CHECK-NEXT: st r24, [p1, dj0] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p2, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128 @@ -524,7 +524,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z24test_fifo_ld_pop_2d_byteRP23v64bfp16 ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: mov m0, r0 -; CHECK-NEXT: mov p3, p0 +; CHECK-NEXT: mov p4, p0 ; CHECK-NEXT: vlda lfl0, [p1, #0]; mov dn0, r1 ; CHECK-NEXT: vlda lfh0, [p1, #64]; mov dj0, r2 ; CHECK-NEXT: vldb.pop.544.2d ex0, [p0, lf0, r24, d0] @@ -536,7 +536,7 @@ define dso_local %struct.v64bfp16ebs16 @_Z24test_fifo_ld_pop_2d_byteRP23v64bfp16 ; CHECK-NEXT: st r24, [p1, dj1] // Delay Slot 5 ; CHECK-NEXT: vst lfl0, [p1, #0] // Delay Slot 4 ; CHECK-NEXT: vst lfh0, [p1, #64] // Delay Slot 3 -; CHECK-NEXT: st p0, [p3, #0] // Delay Slot 2 +; CHECK-NEXT: st p0, [p4, #0] // Delay Slot 2 ; CHECK-NEXT: nop // Delay Slot 1 entry: %pos1.i = getelementptr inbounds i8, ptr %s, i20 128