diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py
index bc779dc14f..cbfb5edcd3 100644
--- a/python/compiler/aiecc/cl_arguments.py
+++ b/python/compiler/aiecc/cl_arguments.py
@@ -138,6 +138,13 @@ def parse_args(args=None):
         action="store_false",
         help="Disable linking of AIE code",
     )
+    parser.add_argument(
+        "--basic-alloc-scheme",
+        dest="basic_alloc_scheme",
+        default=False,
+        action="store_true",
+        help="Use basic memory allocation scheme for AIE buffer address assignment",
+    )
     parser.add_argument(
         "--aie-generate-airbin",
         dest="airbin",
@@ -264,13 +271,6 @@ def parse_args(args=None):
         default="0x901",
         help="Kernel id in xclbin file",
     )
-    parser.add_argument(
-        "--basic-alloc-scheme",
-        dest="basic_alloc_scheme",
-        default=False,
-        action="store_const",
-        help="Use basic memory allocation scheme for AIE buffer address assignment",
-    )
 
     opts = parser.parse_args(args)
     return opts
diff --git a/test/aiecc/simple.mlir b/test/aiecc/simple.mlir
index 1e6be5c811..31d7c0c3b6 100644
--- a/test/aiecc/simple.mlir
+++ b/test/aiecc/simple.mlir
@@ -8,12 +8,12 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: %PYTHON aiecc.py --compile --xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
-// RUN: %PYTHON aiecc.py --compile --no-xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
-// RUN: %PYTHON aiecc.py --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
-// RUN: %PYTHON aiecc.py --no-unified --compile --no-link --xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
-// RUN: %PYTHON aiecc.py --no-unified --compile --no-link --no-xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
-// RUN: %PYTHON aiecc.py --no-unified --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --compile --xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --compile --no-xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --compile --no-link --xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --compile --no-link --no-xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
 
 // Note that llc determines the architecture from the llvm IR.
 
diff --git a/test/aiecc/simple_aie2.mlir b/test/aiecc/simple_aie2.mlir
index 1cc60b464a..4968b950ce 100644
--- a/test/aiecc/simple_aie2.mlir
+++ b/test/aiecc/simple_aie2.mlir
@@ -8,12 +8,12 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: %PYTHON aiecc.py --compile --xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
-// RUN: %PYTHON aiecc.py --compile --no-xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
-// RUN: %PYTHON aiecc.py --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
-// RUN: %PYTHON aiecc.py --no-unified --compile --no-link --xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
-// RUN: %PYTHON aiecc.py --no-unified --compile --no-link --no-xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
-// RUN: %PYTHON aiecc.py --no-unified --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --compile --xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --compile --no-xchesscc --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --compile --no-link --xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=XCHESSCC
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --compile --no-link --no-xchesscc -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=PEANO
+// RUN: %PYTHON aiecc.py --basic-alloc-scheme --no-unified --no-compile --no-link -nv %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% -L%aie_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf | FileCheck %s --check-prefix=NOCOMPILE
 
 // Note that llc determines the architecture from the llvm IR.
 // XCHESSCC-NOT: {{^[^ ]*llc}}
diff --git a/test/dialect/AIE/badbuffer-ve2802.mlir b/test/dialect/AIE/badbuffer-ve2802.mlir
index 686a2ee19c..41f5e4f46d 100644
--- a/test/dialect/AIE/badbuffer-ve2802.mlir
+++ b/test/dialect/AIE/badbuffer-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // Row 2 is a memtile, not a coretile.
 // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 2 is accessed from an unreachable tile in Column 1 and Row 3
 
diff --git a/test/dialect/AIE/badbuffer.mlir b/test/dialect/AIE/badbuffer.mlir
index 2f593e459f..8917a2d361 100644
--- a/test/dialect/AIE/badbuffer.mlir
+++ b/test/dialect/AIE/badbuffer.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 1 is accessed from an unreachable tile in Column 4 and Row 4
 
 module @test {
diff --git a/test/dialect/AIE/badconnect.mlir b/test/dialect/AIE/badconnect.mlir
index 1c89f08af7..8527fec614 100644
--- a/test/dialect/AIE/badconnect.mlir
+++ b/test/dialect/AIE/badconnect.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}} 'aie.connect' op source index cannot be less than zero
 
 module {
diff --git a/test/dialect/AIE/badcore.mlir b/test/dialect/AIE/badcore.mlir
index 0e282f94e2..1993b40081 100644
--- a/test/dialect/AIE/badcore.mlir
+++ b/test/dialect/AIE/badcore.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile
 
 module @test {
diff --git a/test/dialect/AIE/badcore2.mlir b/test/dialect/AIE/badcore2.mlir
index 7505327981..20d6b2e92a 100644
--- a/test/dialect/AIE/badcore2.mlir
+++ b/test/dialect/AIE/badcore2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile
 
 module @test {
diff --git a/test/dialect/AIE/badlock-vc1902.mlir b/test/dialect/AIE/badlock-vc1902.mlir
index 780b3fccc7..0b871e892e 100644
--- a/test/dialect/AIE/badlock-vc1902.mlir
+++ b/test/dialect/AIE/badlock-vc1902.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 15)
 module @test {
   %t1 = aie.tile(1, 1)
diff --git a/test/dialect/AIE/badlock-ve2802.mlir b/test/dialect/AIE/badlock-ve2802.mlir
index 657570ad0f..90e8109cfe 100644
--- a/test/dialect/AIE/badlock-ve2802.mlir
+++ b/test/dialect/AIE/badlock-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 63)
 module @test {
   aie.device(xcve2802) {
diff --git a/test/dialect/AIE/badlockdma.mlir b/test/dialect/AIE/badlockdma.mlir
index 9e79e66559..38b08dd795 100644
--- a/test/dialect/AIE/badlockdma.mlir
+++ b/test/dialect/AIE/badlockdma.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op in Column 4 and Row 4 is accessed from an unreachable tile in Column 1 and Row 1
 module @test {
   %t1 = aie.tile(1, 1)
diff --git a/test/dialect/AIE/badlockfunc.mlir b/test/dialect/AIE/badlockfunc.mlir
index df345d3498..06ca188bb7 100644
--- a/test/dialect/AIE/badlockfunc.mlir
+++ b/test/dialect/AIE/badlockfunc.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op is accessed outside of a tile
 module @test {
   %t1 = aie.tile(1, 1)
diff --git a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir
index 79eead4431..22115e3e51 100644
--- a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir
+++ b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.buffer' op in Column 3 and Row 1 is accessed from an unreachable tile in Column 1 and Row 1
 
 // memtiles can only access neighboring memtiles
diff --git a/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir b/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir
index d4c9eaa330..69c0bc54dc 100644
--- a/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir
+++ b/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir
@@ -9,7 +9,7 @@
 //===----------------------------------------------------------------------===//
 
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.connect' op source bundle FIFO not supported
 
 module {
diff --git a/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir b/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir
index 0540fcd7ca..a7f71c9d61 100644
--- a/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir
+++ b/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir
@@ -9,7 +9,7 @@
 //===----------------------------------------------------------------------===//
 
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.connect' op source bundle DMA not supported
 
 module {
diff --git a/test/dialect/AIE/badtile-ve2802.mlir b/test/dialect/AIE/badtile-ve2802.mlir
index 4cd7856bf9..1ed7dc4bc2 100644
--- a/test/dialect/AIE/badtile-ve2802.mlir
+++ b/test/dialect/AIE/badtile-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (38)
 
 module @test {
diff --git a/test/dialect/AIE/badtile.mlir b/test/dialect/AIE/badtile.mlir
index 1b96f7ae56..0888b6f1e5 100644
--- a/test/dialect/AIE/badtile.mlir
+++ b/test/dialect/AIE/badtile.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op attribute 'col' failed to satisfy constraint: 32-bit signless integer attribute whose minimum value is 0
 
 module @test {
diff --git a/test/dialect/AIE/badtile2.mlir b/test/dialect/AIE/badtile2.mlir
index 2c2aa27116..fae09db62c 100644
--- a/test/dialect/AIE/badtile2.mlir
+++ b/test/dialect/AIE/badtile2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (50)
 
 module @test {
diff --git a/test/dialect/AIE/badtiledma.mlir b/test/dialect/AIE/badtiledma.mlir
index cb41a6114b..22ca8bdc71 100644
--- a/test/dialect/AIE/badtiledma.mlir
+++ b/test/dialect/AIE/badtiledma.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.use_lock' op used in a DMA block that have multiple locks.
 
 module @test {
diff --git a/test/dialect/AIE/badtiledma2.mlir b/test/dialect/AIE/badtiledma2.mlir
index d15d1d7879..9ffed81fc9 100644
--- a/test/dialect/AIE/badtiledma2.mlir
+++ b/test/dialect/AIE/badtiledma2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.dma_bd' op Core tile DMAs can only access a buffer in the same tile.
 
 module @test {
diff --git a/test/dialect/AIE/badtiledma3.mlir b/test/dialect/AIE/badtiledma3.mlir
index 5af6a3cfc6..bab4484672 100644
--- a/test/dialect/AIE/badtiledma3.mlir
+++ b/test/dialect/AIE/badtiledma3.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py %s 2>&1 | FileCheck %s
+// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.use_lock' op can only access a lock in the same tile
 
 module @test {