diff --git a/include/aie/Dialect/AIE/IR/AIE.td b/include/aie/Dialect/AIE/IR/AIE.td index 408a778861..e645001720 100644 --- a/include/aie/Dialect/AIE/IR/AIE.td +++ b/include/aie/Dialect/AIE/IR/AIE.td @@ -40,6 +40,7 @@ switch is referred to as `switchbox` to avoid confusion with the }]; let useDefaultTypePrinterParser = 1; + let useDefaultAttributePrinterParser = 1; let useFoldAPI = kEmitFoldAdaptorFolder; } @@ -797,6 +798,20 @@ def AIE_DMABDPACKETOp: AIE_Op<"dmaBdPacket", []> { } +def AIE_DimTupleAttr : AttrDef { + let mnemonic = "DimTuple"; + let summary = + "Tuple encoding the stride and wrap of one dimension in an " + "AIE2 n-dimensional buffer descriptor"; + let parameters = (ins + "uint32_t" : $stepsize, + "uint16_t" : $wrap + ); + let assemblyFormat = "`<` $stepsize `,` $wrap `>`"; +} + +def AIE_DimTupleArrayAttr : ArrayOfAttr; + def AIE_DMABDOp: AIE_Op<"dmaBd", []> { let summary = "Declare a dma block descriptor op"; let description = [{ @@ -823,17 +838,44 @@ def AIE_DMABDOp: AIE_Op<"dmaBd", []> { ``` A DMA channel in a Memory Module can process one block descriptor after another by chaining them. There are 16 block descriptors per Memory Module. They are shared by four DMA channels. + + On AIE-ML devices, an optional argument can be used to specify an array of + step sizes and wraps to move data in more advanced patterns. Strides and + wraps are specified as tuples ``, and up to three dimensions + can be specified (or up to four dimensions on memtiles). + + The first element of the array gives the _highest-dimension_ stride and + wrap, the last element of the array gives the lowest-dimension. + + Example: + + ``` + AIE.dmaBd(<%buf : memref<128xi32>, 0, 128>, 0, [<16, 8>, <1, 2>, <2, 8>]) + ``` + + This corresponds to alternating between even and odd elements of the + buffer/stream every 8 elements, like so, equivalent to nested loops like so: + + ``` + for(int i = 0; i < 8 /* wrap[0] */; i += 16 /* stepsize[0] */) + for(int j = 0; j < 2 /* wrap[1] */; j += 1 /* stepsize[1] */) + for(int k = 0; k < 8 /* wrap[2] */; k += 2 /* stepsize[2] */) + // access/store element at/to index (i + j + k) + ``` }]; let arguments = ( ins AnyMemRef:$buffer, I32Attr:$offset, I32Attr:$len, - ConfinedAttr, IntMaxValue<1>]>:$AB // 0: A, 1: B + ConfinedAttr, IntMaxValue<1>]>:$AB, // 0: A, 1: B + OptionalAttr:$dimensions ); + let hasVerifier = 1; + let assemblyFormat = [{ - `(` `<` $buffer `:` type($buffer) `,` $offset `,` $len `>` `,` $AB `)` attr-dict + `(` `<` $buffer `:` type($buffer) `,` $offset `,` $len `>` `,` $AB (`,` $dimensions^ )? `)` attr-dict }]; let extraClassDeclaration = [{ @@ -843,15 +885,14 @@ def AIE_DMABDOp: AIE_Op<"dmaBd", []> { bool isB() { return (getAB() == 1); } }]; - // let builders = [ - // OpBuilder<(ins "Value":$buffer, "int":$offset, "int":$len, "int":$AB), [{ - // build($_builder, $_state, - // buffer, - // $_builder.getI32IntegerAttr(offset), - // $_builder.getI32IntegerAttr(len), - // $_builder.getI32IntegerAttr(AB)); - // }]> - // ]; + let builders = [ + OpBuilder<(ins "Value":$buffer, "int":$offset, "int":$len, "int":$AB), [{ + odsState.addOperands(buffer); + odsState.addAttribute(getOffsetAttrName(odsState.name), $_builder.getI32IntegerAttr(offset)); + odsState.addAttribute(getLenAttrName(odsState.name), $_builder.getI32IntegerAttr(len)); + odsState.addAttribute(getABAttrName(odsState.name), $_builder.getI32IntegerAttr(AB)); + }]> + ]; } def AIE_DMAStartOp: AIE_Op<"dmaStart", [ParentOneOf<["MemOp", "MemTileDMAOp", "func::FuncOp", "ShimDMAOp"]>, Terminator]>, diff --git a/include/aie/Dialect/AIE/IR/AIEDialect.h b/include/aie/Dialect/AIE/IR/AIEDialect.h index 0195ac649d..090db93b4a 100644 --- a/include/aie/Dialect/AIE/IR/AIEDialect.h +++ b/include/aie/Dialect/AIE/IR/AIEDialect.h @@ -65,67 +65,27 @@ class TileOp; /// Include the generated interface declarations. #include "aie/Dialect/AIE/IR/AIEInterfaces.h.inc" +// Include dialect declarations such as parseAttributes, parseType +#include "aie/Dialect/AIE/IR/AIEDialect.h.inc" + namespace xilinx { namespace AIE { void registerAIETranslations(); -// FIXME: use this -//#include "AIEDialect.h.inc" - -// The Dialect -class AIEDialect : public mlir::Dialect { -public: - explicit AIEDialect(mlir::MLIRContext *ctx); - static StringRef getDialectNamespace() { return "AIE"; } - - /// Parse a type registered to this dialect. Overridding this method is - /// required for dialects that have custom types. - /// Technically this is only needed to be able to round-trip to textual IR. - mlir::Type parseType(DialectAsmParser &parser) const override; - - /// Print a type registered to this dialect. Overridding this method is - /// only required for dialects that have custom types. - /// Technically this is only needed to be able to round-trip to textual IR. - void printType(mlir::Type type, DialectAsmPrinter &os) const override; -}; +} // namespace AIE +} // namespace xilinx //////////////////////////////////////////////////////////////////////////////// /////////////////////// Custom Types for the Dialect /////////////////////////// //////////////////////////////////////////////////////////////////////////////// -// namespace detail { -// struct AIEListTypeStorage; -// } - -// /// LLVM-style RTTI: one entry per subclass to allow dyn_cast/isa. -// enum AIETypeKind { -// // The enum starts at the range reserved for this dialect. -// AIE_TYPE = mlir::Type::FIRST_PRIVATE_EXPERIMENTAL_0_TYPE, -// AIE_LIST, -// }; - -// /// Type for Toy arrays. -// /// In MLIR Types are reference to immutable and uniqued objects owned by the -// /// MLIRContext. As such `AIEListType` only wraps a pointer to an uniqued -// /// instance of `AIEListTypeStorage` (defined in our implementation file) and -// /// provides the public facade API to interact with the type. -// class AIEListType : public mlir::Type::TypeBase -// { -// public: -// using Base::Base; - -// /// Return the type of individual elements in the array. -// mlir::Type getElementType(); - -// /// Get the unique instance of this Type from the context. -// static AIEListType get(mlir::Type elementType); - -// /// Support method to enable LLVM-style RTTI type casting. -// static bool kindof(unsigned kind) { return kind == AIETypeKind::AIE_LIST; } -// }; +// Include generated TableGen-generated type definitions +#define GET_TYPEDEF_CLASSES 1 +#include "aie/Dialect/AIE/IR/AIETypes.h.inc" +namespace xilinx { +namespace AIE { namespace detail { struct AIEObjectFifoTypeStorage; } @@ -172,11 +132,24 @@ class AIEObjectFifoSubviewType mlir::Type getElementType(); }; +} // namespace AIE +} // namespace xilinx + +//////////////////////////////////////////////////////////////////////////////// +// Custom Attributes /////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +#define GET_ATTRDEF_CLASSES +#include "aie/Dialect/AIE/IR/AIEAttrDefs.h.inc" + //////////////////////////////////////////////////////////////////////////////// //////////////////// Custom Operations for the Dialect ///////////////////////// //////////////////////////////////////////////////////////////////////////////// -//#include "AIEOpInterfaces.h.inc" +namespace xilinx { +namespace AIE { + +// #include "AIEOpInterfaces.h.inc" typedef std::pair Port; typedef std::pair Connect; diff --git a/include/aie/Dialect/AIE/IR/CMakeLists.txt b/include/aie/Dialect/AIE/IR/CMakeLists.txt index 0013e5edb2..9d41eb9040 100644 --- a/include/aie/Dialect/AIE/IR/CMakeLists.txt +++ b/include/aie/Dialect/AIE/IR/CMakeLists.txt @@ -8,6 +8,11 @@ add_mlir_dialect(AIE AIE) add_mlir_doc(AIE AIEDialect ./ -gen-dialect-doc) +set(LLVM_TARGET_DEFINITIONS AIE.td) +mlir_tablegen(AIEAttrDefs.h.inc -gen-attrdef-decls -attrdefs-dialect=AIE) +mlir_tablegen(AIEAttrDefs.cpp.inc -gen-attrdef-defs -attrdefs-dialect=AIE) +add_public_tablegen_target(MLIRAIEAttrDefsIncGen) + set(LLVM_TARGET_DEFINITIONS AIE.td) mlir_tablegen(AIEEnums.h.inc -gen-enum-decls) mlir_tablegen(AIEEnums.cpp.inc -gen-enum-defs) @@ -17,9 +22,3 @@ set(LLVM_TARGET_DEFINITIONS AIEInterfaces.td) mlir_tablegen(AIEInterfaces.h.inc -gen-op-interface-decls) mlir_tablegen(AIEInterfaces.cpp.inc -gen-op-interface-defs) add_public_tablegen_target(MLIRAIEInterfacesIncGen) - -# set(LLVM_TARGET_DEFINITIONS AIE.td) -# mlir_tablegen(LLVMConversions.inc -gen-llvmir-conversions) -# mlir_tablegen(LLVMConversionEnumsToLLVM.inc -gen-enum-to-llvmir-conversions) -# mlir_tablegen(LLVMConversionEnumsFromLLVM.inc -gen-enum-from-llvmir-conversions) -# add_public_tablegen_target(MLIRLLVMConversionsIncGen) diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp index ab96a5d730..c25702abbc 100644 --- a/lib/Dialect/AIE/IR/AIEDialect.cpp +++ b/lib/Dialect/AIE/IR/AIEDialect.cpp @@ -16,9 +16,14 @@ #include "mlir/Transforms/InliningUtils.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/TypeSwitch.h" using namespace mlir; +// Add TableGen'erated dialect definitions (including constructor) +// We implement the initialize() function further below +#include "aie/Dialect/AIE/IR/AIEDialect.cpp.inc" + namespace { struct AIEInlinerInterface : public DialectInlinerInterface { @@ -330,11 +335,16 @@ void AIEDialect::printType(mlir::Type type, } } -// FIXME: use Tablegen'd dialect class -AIEDialect::AIEDialect(mlir::MLIRContext *ctx) - : mlir::Dialect("AIE", ctx, ::mlir::TypeID::get()) { - // addTypes(); +void AIEDialect::initialize() { + addTypes< +#define GET_TYPE_LIST +#include "aie/Dialect/AIE/IR/AIETypes.cpp.inc" + >(); addTypes(); + addAttributes< +#define GET_ATTRDEF_LIST +#include "aie/Dialect/AIE/IR/AIEAttrDefs.cpp.inc" + >(); addOperations< #define GET_OP_LIST #include "aie/Dialect/AIE/IR/AIE.cpp.inc" @@ -624,9 +634,7 @@ const xilinx::AIE::AIETargetModel &xilinx::AIE::DeviceOp::getTargetModel() { return VC1902model; } -LogicalResult xilinx::AIE::DeviceOp::verify() { - return success(); -} +LogicalResult xilinx::AIE::DeviceOp::verify() { return success(); } LogicalResult xilinx::AIE::TileOp::verify() { const auto &target_model = getTargetModel(*this); @@ -987,6 +995,64 @@ LogicalResult xilinx::AIE::MemTileDMAOp::verify() { return success(); } +// DMABDOp +LogicalResult xilinx::AIE::DMABDOp::verify() { + // The following checks only apply if non-default strides/wraps are defined. + if (getDimensions()) { + ::mlir::MemRefType buffer = getBuffer().getType(); + // We are restrictive about the type of the memref used as the input address + // to the DMABD when used with multi-dimensional strides/wraps. Since the + // BD will use the memref as a base address and copy from it in 32 bit + // chunks, while assuming the layout of the memref is contiguous, we + // disallow anything whose elemental size is not 32 bits, or where we + // cannot verify that the layout is contiguous. + if (!buffer.getElementType().isInteger(32) || buffer.getRank() > 1 || + !buffer.getLayout().isIdentity()) { + return emitOpError() << "Specifying transfer step sizes and wraps is only" + " supported for one-dimensional memrefs of 32 bit" + " integer elements."; + } + uint64_t memref_size = 1; // in bytes + uint64_t max_idx = 0; + for (int64_t memref_dim : buffer.getShape()) { + memref_size *= 4 * memref_dim; + } + llvm::ArrayRef dims = *getDimensions(); + size_t max_n_dims = 3; + if (isa_and_nonnull((*this)->getParentOp())) { + max_n_dims = 4; + } + if (dims.size() > max_n_dims) { + return emitOpError() << "Cannot give more than " + << std::to_string(max_n_dims) + << " dimensions for step sizes and wraps in this " + " tile (got " + << std::to_string(dims.size()) << " dimensions)."; + } + for (xilinx::AIE::DimTupleAttr dim : dims) { + max_idx += dim.getStepsize() * (dim.getWrap() - 1); + if (0 == dim.getStepsize()) { + return emitOpError() + << "Invalid step size; must be a positive integer."; + } + if (dim.getStepsize() > memref_size) { + return emitOpError() + << "Step size " << std::to_string(dim.getStepsize() * 4) << " " + << "bytes exceeds memref size " << std::to_string(memref_size); + } + } + if (memref_size <= 4 * max_idx) { + return emitOpError() << "Specified stepsize(s) and wrap(s) result in out " + "of bounds access in buffer, for index " + << std::to_string(max_idx) << ", accessing at " + << std::to_string(4 * max_idx) + << " byte offset in memref of length " + << std::to_string(memref_size) << "."; + } + } + return success(); +} + xilinx::AIE::TileOp xilinx::AIE::MemTileDMAOp::getTileOp() { return cast(getTile().getDefiningOp()); } @@ -1206,3 +1272,7 @@ bool TileOp::isShimPLTile() { bool TileOp::isShimNOCorPLTile() { return isShimNOCTile() || isShimPLTile(); } } // namespace AIE } // namespace xilinx + +// Include implementations for custom attributes +#define GET_ATTRDEF_CLASSES +#include "aie/Dialect/AIE/IR/AIEAttrDefs.cpp.inc" diff --git a/lib/Dialect/AIE/IR/CMakeLists.txt b/lib/Dialect/AIE/IR/CMakeLists.txt index eb6106f361..c0009034c3 100644 --- a/lib/Dialect/AIE/IR/CMakeLists.txt +++ b/lib/Dialect/AIE/IR/CMakeLists.txt @@ -13,6 +13,7 @@ add_mlir_dialect_library(AIE DEPENDS MLIRAIEIncGen + MLIRAIEAttrDefsIncGen MLIRAIEEnumsIncGen MLIRAIEInterfacesIncGen diff --git a/lib/Dialect/AIEX/IR/CMakeLists.txt b/lib/Dialect/AIEX/IR/CMakeLists.txt index 6ab93b50f7..f4168f9a36 100644 --- a/lib/Dialect/AIEX/IR/CMakeLists.txt +++ b/lib/Dialect/AIEX/IR/CMakeLists.txt @@ -15,6 +15,7 @@ add_mlir_dialect_library(AIEX MLIRAIEXEnumsIncGen LINK_LIBS PUBLIC + AIE MLIRIR MLIRSupport ) diff --git a/lib/Targets/AIETargetXAIEV2.cpp b/lib/Targets/AIETargetXAIEV2.cpp index a2063a46db..1f31ac51fa 100644 --- a/lib/Targets/AIETargetXAIEV2.cpp +++ b/lib/Targets/AIETargetXAIEV2.cpp @@ -37,6 +37,38 @@ using namespace xilinx::AIEX; namespace xilinx { namespace AIE { +// This string is output at the top of the lowered C code. +const char xaie_c_file_header[] = R"code( +// This file was auto-generated by aiecc.py --aie-generate-xaie. + +#ifndef MLIR_AIE_QUIET +#define __mlir_aie_verbose(x) x +#else +#define __mlir_aie_verbose(x) +#endif + +// The following is a wrapper for the common "if(call() != 0) return 1" pattern. +// Use this only in functions that return int. If the call this wrapper is used +// on does not succeed, the expanded code will exit out of the function +// containing this macro with an error code. +#define __mlir_aie_try(x) do { \ + AieRC ret = (x); \ + if(ret != XAIE_OK) { \ + return x; \ + } \ +} while(0) + +static XAie_DmaDimDesc *__mlir_aie_alloc_dim_desc(size_t ndims) { + XAie_DmaDimDesc *ret = NULL; + ret = (XAie_DmaDimDesc *)calloc(sizeof(XAie_DmaDimDesc), ndims); + if(NULL == ret) { + __mlir_aie_verbose(fprintf(stderr, "Allocating DmaDimDesc failed.\n")); + } + return ret; +} + +)code"; + /* static std::string shimDMAInstStr(StringRef col, StringRef index) { std::string str; @@ -75,6 +107,17 @@ static std::string tileDMAInstRefStr(int col, int row, int bdNum) { return tileDMAInstRefStr(std::to_string(col), std::to_string(row), std::to_string(bdNum)); } +static std::string tileDMATensorStr(StringRef col, StringRef row, + StringRef bdNum) { + std::string str; + llvm::raw_string_ostream rss(str); + rss << "dma_tile_" << col << "_" << row << "_bd_" << bdNum << "_tensor"; + return str; +} +static std::string tileDMATensorStr(int col, int row, int bdNum) { + return tileDMATensorStr(std::to_string(col), std::to_string(row), + std::to_string(bdNum)); +} static std::string tileLockStr(StringRef id, StringRef val) { std::string str; llvm::raw_string_ostream rss(str); @@ -123,6 +166,8 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, StringRef bufA = "0"; StringRef bufB = "0"; StringRef AbMode = disable; + int ndims = 0; + ArrayRef dims; // StringRef FifoMode = disable; // FIXME: when to enable FIFO mode? for (auto op : block.template getOps()) { foundBd = true; @@ -144,6 +189,16 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, bufB = "XAIEDMA_TILE_BD_ADDRB"; hasB = true; } + if (op.getDimensions()) { + dims = *op.getDimensions(); + ndims = dims.size(); + } + } + + if (0 != ndims && AIEArch::AIE2 != target_model.getTargetArch()) { + return memOp.emitOpError("DMA contains at least one multi-dimensional " + "buffer descriptor. This is currently only " + "supported for AIE-ML devices."); } if (hasA && hasB) { @@ -196,14 +251,14 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, // which we assume is unique. This is strictly not enforced but in // practice, this is true output << "XAie_DmaDesc " << tileDMAInstStr(col, row, bdNum) << ";\n"; - output << "XAie_DmaDescInit(" << deviceInstRef << ", " + output << "__mlir_aie_try(XAie_DmaDescInit(" << deviceInstRef << ", " << tileDMAInstRefStr(col, row, bdNum) << ", " - << tileLocStr(col, row) << ");\n"; + << tileLocStr(col, row) << "));\n"; if (hasAcq || hasRel) { - output << "XAie_DmaSetLock(" << tileDMAInstRefStr(col, row, bdNum) - << ", " + output << "__mlir_aie_try(XAie_DmaSetLock(" + << tileDMAInstRefStr(col, row, bdNum) << ", " << "XAie_LockInit(" << acqLockID << "," << acqValue << ")," - << "XAie_LockInit(" << relLockID << "," << relValue << "));\n"; + << "XAie_LockInit(" << relLockID << "," << relValue << ")));\n"; if (!hasAcq) output << tileDMAInstStr(col, row, bdNum) << ".LockDesc.LockAcqEn = " << disable << ";\n"; @@ -212,24 +267,55 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, << ".LockDesc.LockRelEn = " << disable << ";\n"; } - if (target_model.isShimNOCTile(col, row)) { - output << "XAie_DmaSetAddrLen(" << tileDMAInstRefStr(col, row, bdNum) - << ", /* addrA */ " - << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_" - << bdNum << "(), " - << " /* len */ " << lenA << " * " << bytesA << ");\n"; - output << "XAie_DmaSetAxi(" << tileDMAInstRefStr(col, row, bdNum) - << ", " - << "/* smid */ 0, " - << "/* burstlen */ 4, " - << "/* QoS */ 0, " - << "/* Cache */ 0, " - << "/* Secure */ " << enable << ");\n"; + if (0 == ndims) { + if (target_model.isShimNOCTile(col, row)) { + output << "__mlir_aie_try(XAie_DmaSetAddrLen(" + << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " + << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_" + << bdNum << "(), " + << " /* len */ " << lenA << " * " << bytesA << "));\n"; + output << "__mlir_aie_try(XAie_DmaSetAxi(" + << tileDMAInstRefStr(col, row, bdNum) << ", " + << "/* smid */ 0, " + << "/* burstlen */ 4, " + << "/* QoS */ 0, " + << "/* Cache */ 0, " + << "/* Secure */ " << enable << "));\n"; + } else { + output << "__mlir_aie_try(XAie_DmaSetAddrLen(" + << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " + << "0x" << llvm::utohexstr(BaseAddrA + offsetA) << ", " + << " /* len */ " << lenA << " * " << bytesA << "));\n"; + } } else { - output << "XAie_DmaSetAddrLen(" << tileDMAInstRefStr(col, row, bdNum) - << ", /* addrA */ " + std::string tensor = tileDMATensorStr(col, row, bdNum); + output << "XAie_DmaTensor " << tensor << " = {};\n"; + output << tensor << ".NumDim = " << std::to_string(ndims) << ";\n"; + output << tensor + << ".Dim =" + "__mlir_aie_alloc_dim_desc(" + << std::to_string(ndims) << ");\n"; + output << "if(NULL == " << tensor << ".Dim){\n" + << " return 1;\n" + << "}\n"; + for (int i = 0; i < ndims; i++) { + // Pass down dimensions in reverse order; in the MLIR, this allows us + // to specify step sizes/wraps in the same order as we would access a + // multi-dim C array, with the highest dimension first. + int j = ndims - i - 1; + // Assume AIE-ML architecture; we assert this above + output << tensor << ".Dim[" << std::to_string(j) << "].AieMlDimDesc" + << " = { /* StepSize */ " + << std::to_string(dims[i].getStepsize()) << ", /* Wrap */ " + << std::to_string(dims[i].getWrap()) << "};\n"; + } + output << "__mlir_aie_try(XAie_DmaSetMultiDimAddr(" + << tileDMAInstRefStr(col, row, bdNum) << ", " + << "&" << tensor << ", " << "0x" << llvm::utohexstr(BaseAddrA + offsetA) << ", " - << " /* len */ " << lenA << " * " << bytesA << ");\n"; + << " /* len */ " << lenA << " * " << bytesA << "));\n"; + // TODO: Probably need special handling for NOC + // TODO: Might need to adjust step sizes / wraps by -1 } if (block.getNumSuccessors() > 0) { @@ -241,21 +327,22 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, enableNextBd = 0; int nextBdNum = blockMap[nextBlock]; - output << "XAie_DmaSetNextBd(" << tileDMAInstRefStr(col, row, bdNum) - << ", " + output << "__mlir_aie_try(XAie_DmaSetNextBd(" + << tileDMAInstRefStr(col, row, bdNum) << ", " << " /* nextbd */ " << nextBdNum << ", " - << " /* enableNextBd */ " << enableNextBd << ");\n"; + << " /* enableNextBd */ " << enableNextBd << "));\n"; } if (foundBdPacket) { - output << "XAie_DmaSetPkt(" << tileDMAInstRefStr(col, row, bdNum) - << ", " << packetStr(packetID, packetType) << ");\n"; + output << "__mlir_aie_try(XAie_DmaSetPkt(" + << tileDMAInstRefStr(col, row, bdNum) << ", " + << packetStr(packetID, packetType) << "));\n"; } - output << "XAie_DmaEnableBd(" << tileDMAInstRefStr(col, row, bdNum) - << ");\n"; - output << "XAie_DmaWriteBd(" << deviceInstRef << ", " + output << "__mlir_aie_try(XAie_DmaEnableBd(" + << tileDMAInstRefStr(col, row, bdNum) << "));\n"; + output << "__mlir_aie_try(XAie_DmaWriteBd(" << deviceInstRef << ", " << tileDMAInstRefStr(col, row, bdNum) << ", " << tileLocStr(col, row) << ", " - << " /* bd */ " << bdNum << ");\n"; + << " /* bd */ " << bdNum << "));\n"; } } @@ -266,19 +353,19 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, llvm::StringRef dmaDir = stringifyDMAChannelDir(op.getChannelDir()); int chNum = op.getChannelIndex(); - output << "XAie_DmaChannelPushBdToQueue(" << deviceInstRef << ", " - << tileLocStr(col, row) << ", " + output << "__mlir_aie_try(XAie_DmaChannelPushBdToQueue(" << deviceInstRef + << ", " << tileLocStr(col, row) << ", " << "/* ChNum */" << chNum << ", " // TODO hack until physical dialect changes << "/* dmaDir */ DMA_" << dmaDir << ", " - << "/* BdNum */" << bdNum << ");\n"; - output << "XAie_DmaChannelEnable(" << deviceInstRef << ", " + << "/* BdNum */" << bdNum << "));\n"; + output << "__mlir_aie_try(XAie_DmaChannelEnable(" << deviceInstRef << ", " << tileLocStr(col, row) << ", " << "/* ChNum */ " << chNum << ", " // TODO hack until physical dialect changes - << "/* dmaDir */ DMA_" << dmaDir << ");\n"; + << "/* dmaDir */ DMA_" << dmaDir << "));\n"; } } return success(); @@ -310,6 +397,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { //--------------------------------------------------------------------------- // mlir_aie_init_libxaie //--------------------------------------------------------------------------- + output << xaie_c_file_header; output << "aie_libxaie_ctx_t* mlir_aie_init_libxaie() {\n"; output << " aie_libxaie_ctx_t *ctx = (aie_libxaie_ctx_t " "*)malloc(sizeof(aie_libxaie_ctx_t));\n"; @@ -364,7 +452,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { //--------------------------------------------------------------------------- // mlir_aie_configure_cores //--------------------------------------------------------------------------- - output << "void mlir_aie_configure_cores(" << ctx_p << ") {\n"; + output << "int mlir_aie_configure_cores(" << ctx_p << ") {\n"; // Reset each core. Load the corresponding ELF file, if necessary. for (auto tileOp : targetOp.getOps()) { int col = tileOp.colIndex(); @@ -373,15 +461,15 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { // Resets no needed with V2 kernel driver } else { // Resets no needed with V2 kernel driver - output << "XAie_CoreReset(" << deviceInstRef << ", " - << tileLocStr(col, row) << ");\n"; - output << "XAie_CoreDisable(" << deviceInstRef << ", " - << tileLocStr(col, row) << ");\n"; + output << "__mlir_aie_try(XAie_CoreReset(" << deviceInstRef << ", " + << tileLocStr(col, row) << "));\n"; + output << "__mlir_aie_try(XAie_CoreDisable(" << deviceInstRef << ", " + << tileLocStr(col, row) << "));\n"; // Release locks int numLocks = target_model.getNumLocks(col, row); output << "for (int l = 0; l < " << numLocks << "; ++l)\n" - << " XAie_LockRelease(" << deviceInstRef << ", " - << tileLocStr(col, row) << ", XAie_LockInit(l, 0x0), 0);\n"; + << " __mlir_aie_try(XAie_LockRelease(" << deviceInstRef << ", " + << tileLocStr(col, row) << ", XAie_LockInit(l, 0x0), 0));\n"; if (auto coreOp = tileOp.getCoreOp()) { std::string fileName; if (auto fileAttr = coreOp->getAttrOfType("elf_file")) { @@ -395,38 +483,40 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { << tileLocStr(col, row) << ", " << "(const char*)\"" << fileName << "\",0);\n"; output << "if (RC != XAIE_OK)\n" - << " printf(\"Failed to load elf for Core[%d,%d], ret is " - "%d\\n\", " + << " __mlir_aie_verbose(fprintf(stderr, \"Failed to load elf " + "for Core[%d,%d], ret is %d\\n\", " << std::to_string(col) << ", " << std::to_string(row) - << ", RC);\n" + << ", RC));\n" << "assert(RC == XAIE_OK);\n" << "}\n"; } } } + output << "return XAIE_OK;\n"; output << "} // mlir_aie_configure_cores\n\n"; //--------------------------------------------------------------------------- // mlir_aie_start_cores //--------------------------------------------------------------------------- - output << "void mlir_aie_start_cores(" << ctx_p << ") {\n"; + output << "int mlir_aie_start_cores(" << ctx_p << ") {\n"; // Start execution of all the cores. for (auto tileOp : targetOp.getOps()) { int col = tileOp.colIndex(); int row = tileOp.rowIndex(); if (!tileOp.isShimTile() && !tileOp.isMemTile()) { - output << "XAie_CoreUnreset(" << deviceInstRef << ", " - << tileLocStr(col, row) << ");\n"; - output << "XAie_CoreEnable(" << deviceInstRef << ", " - << tileLocStr(col, row) << ");\n"; + output << "__mlir_aie_try(XAie_CoreUnreset(" << deviceInstRef << ", " + << tileLocStr(col, row) << "));\n"; + output << "__mlir_aie_try(XAie_CoreEnable(" << deviceInstRef << ", " + << tileLocStr(col, row) << "));\n"; } } + output << "return XAIE_OK;\n"; output << "} // mlir_aie_start_cores\n\n"; //--------------------------------------------------------------------------- // mlir_aie_configure_dmas //--------------------------------------------------------------------------- - output << "void mlir_aie_configure_dmas(" << ctx_p << ") {\n"; + output << "int mlir_aie_configure_dmas(" << ctx_p << ") {\n"; // DMA configuration // AieRC XAie_DmaDescInit(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc, @@ -510,6 +600,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { if (result.failed()) return result; } + + output << "return XAIE_OK;\n"; output << "} // mlir_aie_configure_dmas\n\n"; for (auto op : targetOp.getOps()) { @@ -564,18 +656,19 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { } } - output << "void mlir_aie_configure_shimdma_" << col << row << "(" << ctx_p + output << "int mlir_aie_configure_shimdma_" << col << row << "(" << ctx_p << ") {\n"; auto result = generateDMAConfig(op, output, target_model, NL, blockMap); if (result.failed()) return result; + output << "return XAIE_OK;\n"; output << "} // mlir_aie_configure_shimdma\n\n"; } //--------------------------------------------------------------------------- // mlir_aie_initialize_locks //--------------------------------------------------------------------------- - output << "void mlir_aie_initialize_locks(" << ctx_p << ") {\n"; + output << "int mlir_aie_initialize_locks(" << ctx_p << ") {\n"; // Lock configuration for (auto lock : targetOp.getOps()) { TileOp tile = lock.getTileOp(); @@ -584,17 +677,18 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { int lockID = lock.getLockIDValue(); auto init = lock.getInit(); if (init) { - output << "XAie_LockSetValue(" << deviceInstRef << ", " + output << "__mlir_aie_try(XAie_LockSetValue(" << deviceInstRef << ", " << tileLocStr(col, row) << ", " - << "XAie_LockInit(" << lockID << ", " << *init << "));\n"; + << "XAie_LockInit(" << lockID << ", " << *init << ")));\n"; } } + output << "return XAIE_OK;\n"; output << "} // mlir_aie_initialize_locks\n"; //--------------------------------------------------------------------------- // mlir_aie_configure_switchboxes //--------------------------------------------------------------------------- - output << "void mlir_aie_configure_switchboxes(" << ctx_p << ") {\n"; + output << "int mlir_aie_configure_switchboxes(" << ctx_p << ") {\n"; output << " int x, y;\n"; // StreamSwitch (switchbox) configuration @@ -645,12 +739,12 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { } for (auto connectOp : b.getOps()) { - output << "XAie_StrmConnCctEnable(" << deviceInstRef << ", " - << tileLocStr("x", "y") << ", " + output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef + << ", " << tileLocStr("x", "y") << ", " << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", " << connectOp.sourceIndex() << ", " << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " - << connectOp.destIndex() << ");\n"; + << connectOp.destIndex() << "));\n"; } for (auto connectOp : b.getOps()) { @@ -664,8 +758,8 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { } bool isdma = (connectOp.getDestBundle() == WireBundle::DMA); - output << "XAie_StrmPktSwMstrPortEnable(" << deviceInstRef << ", " - << tileLocStr("x", "y") << ", " + output << "__mlir_aie_try(XAie_StrmPktSwMstrPortEnable(" << deviceInstRef + << ", " << tileLocStr("x", "y") << ", " << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " << connectOp.destIndex() << ", " << "/* drop_header */ " @@ -674,7 +768,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { << ", " << "/* arbiter */ " << arbiter << ", " << "/* MSelEn */ " - << "0x" << llvm::utohexstr(mask) << ");\n"; + << "0x" << llvm::utohexstr(mask) << "));\n"; } for (auto connectOp : b.getOps()) { @@ -684,14 +778,14 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { AMSelOp amselOp = dyn_cast(slotOp.getAmsel().getDefiningOp()); int arbiter = amselOp.arbiterIndex(); int msel = amselOp.getMselValue(); - output << "XAie_StrmPktSwSlavePortEnable(" << deviceInstRef << ", " - << tileLocStr("x", "y") << ", " + output << "__mlir_aie_try(XAie_StrmPktSwSlavePortEnable(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " << stringifyWireBundle(connectOp.getSourceBundle()).upper() - << ", " << connectOp.sourceIndex() << ");\n"; + << ", " << connectOp.sourceIndex() << "));\n"; // TODO Need to better define packet id,type used here - output << "XAie_StrmPktSwSlaveSlotEnable(" << deviceInstRef << ", " - << tileLocStr("x", "y") << ", " + output << "__mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", " << connectOp.sourceIndex() << ", " << "/* slot */ " << slot << ", " @@ -700,7 +794,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { << "/* mask */ " << "0x" << llvm::utohexstr(slotOp.maskInt()) << ", " << "/* msel */ " << msel << ", " - << "/* arbiter */ " << arbiter << ");\n"; + << "/* arbiter */ " << arbiter << "));\n"; slot++; } } @@ -732,21 +826,21 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { if (connectOp.getSourceBundle() == WireBundle::North) { // demux! output - << "XAie_EnableAieToShimDmaStrmPort(" << deviceInstRef << ", " - << tileLocStr("x", "y") + << "__mlir_aie_try(XAie_EnableAieToShimDmaStrmPort(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " // << // stringifyWireBundle(connectOp.sourceBundle()).upper() - << connectOp.sourceIndex() << ");\n"; + << connectOp.sourceIndex() << "));\n"; } else if (connectOp.getDestBundle() == WireBundle::North) { // mux output - << "XAie_EnableShimDmaToAieStrmPort(" << deviceInstRef << ", " - << tileLocStr("x", "y") + << "__mlir_aie_try(XAie_EnableShimDmaToAieStrmPort(" + << deviceInstRef << ", " << tileLocStr("x", "y") << ", " // << // stringifyWireBundle(connectOp.sourceBundle()).upper() - << connectOp.destIndex() << ");\n"; + << connectOp.destIndex() << "));\n"; } } } @@ -759,15 +853,16 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << "// Shim Switch column " << col << "\n"; } for (auto connectOp : b.getOps()) { - output << "XAie_StrmConnCctEnable(" << deviceInstRef << ", " - << tileLocStr(col, 0) << ", " + output << "__mlir_aie_try(XAie_StrmConnCctEnable(" << deviceInstRef + << ", " << tileLocStr(col, 0) << ", " << stringifyWireBundle(connectOp.getSourceBundle()).upper() << ", " << connectOp.sourceIndex() << ", " << stringifyWireBundle(connectOp.getDestBundle()).upper() << ", " - << connectOp.destIndex() << ");\n"; + << connectOp.destIndex() << "));\n"; } } + output << "return XAIE_OK;\n"; output << "} // mlir_aie_configure_switchboxes\n\n"; //--------------------------------------------------------------------------- @@ -820,7 +915,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << " return c.f;\n"; } output << "}\n"; - output << "void mlir_aie_write_buffer_" << bufName << "(" << ctx_p + output << "int mlir_aie_write_buffer_" << bufName << "(" << ctx_p << ", int index, " << typestr << " value) {\n"; if (et.isInteger(32)) output << " int32_t int_value = value;\n"; @@ -829,8 +924,9 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << " caster c; c.f = value;\n"; output << " int32_t int_value = c.i;\n"; } - output << "u32 rc = XAie_DataMemWrWord(" << deviceInstRef << ", " + output << "AieRC rc = XAie_DataMemWrWord(" << deviceInstRef << ", " << loc << ", " << bufName << "_offset + (index*4), int_value);\n"; + output << "return rc;\n"; output << "}\n"; }; diff --git a/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir b/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir new file mode 100644 index 0000000000..eca3e4516d --- /dev/null +++ b/test/Targets/AIEGenerateXAIE/aie2_nd_DMA.mlir @@ -0,0 +1,69 @@ +//===- aie2_nd_DMA.mlir ----------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// (c) Copyright 2023 Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-translate --aie-generate-xaie %s | FileCheck %s + +// CHECK: dma_tile_2_1_bd_0_tensor.NumDim = 4; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim =__mlir_aie_alloc_dim_desc(4); +// CHECK: if(NULL == dma_tile_2_1_bd_0_tensor.Dim){ +// CHECK: return 1; +// CHECK: } +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[3].AieMlDimDesc = { /* StepSize */ 1, /* Wrap */ 2}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[2].AieMlDimDesc = { /* StepSize */ 2, /* Wrap */ 3}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[1].AieMlDimDesc = { /* StepSize */ 4, /* Wrap */ 2}; +// CHECK: dma_tile_2_1_bd_0_tensor.Dim[0].AieMlDimDesc = { /* StepSize */ 1, /* Wrap */ 1}; +// CHECK: __mlir_aie_try(XAie_DmaSetMultiDimAddr(&(dma_tile21_bd0), &dma_tile_2_1_bd_0_tensor, 0x82000, /* len */ 128 * 4)); + +module @aie_module { + AIE.device(xcve2302) { + %t01 = AIE.tile(2, 1) + %buf01_0 = AIE.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> + %buf01_1 = AIE.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> + + %trhesholdValue = arith.constant 100 : i16 + + %l01_0 = AIE.lock(%t01, 0) { init = 1 : i32 } + %l01_1 = AIE.lock(%t01, 1) + %l01_2 = AIE.lock(%t01, 2) { init = 1 : i32 } + %l01_3 = AIE.lock(%t01, 3) + + %m01 = AIE.memTileDMA(%t01) { + %srcDma = AIE.dmaStart(S2MM, 0, ^bd0, ^dma0) + ^dma0: + %memSrcDma = AIE.dmaStart(MM2S, 1, ^bd1, ^dma1) + ^dma1: + %memDstDma = AIE.dmaStart(S2MM, 1, ^bd2, ^dma2) + ^dma2: + %dstDma = AIE.dmaStart(MM2S, 0, ^bd3, ^end) + ^bd0: + AIE.useLock(%l01_0, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf01_0 : memref<16xi32>, 0, 128>, 0, [<1, 2>, <2, 3>, <4, 2>, <1, 1>]) + AIE.useLock(%l01_1, "Release", 1) + AIE.nextBd ^bd0 + ^bd1: + AIE.useLock(%l01_1, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf01_0 : memref<16xi32>, 0, 16>, 0) + AIE.useLock(%l01_0, "Release", 1) + AIE.nextBd ^bd1 + ^bd2: + AIE.useLock(%l01_2, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf01_1 : memref<16xi32>, 0, 16>, 0) + AIE.useLock(%l01_3, "Release", 1) + AIE.nextBd ^bd2 + ^bd3: + AIE.useLock(%l01_3, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf01_1 : memref<16xi32>, 0, 16>, 0) + AIE.useLock(%l01_2, "Release", 1) + AIE.nextBd ^bd3 + ^end: + AIE.end + } + } +} diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir index e299698f9a..4b32fe9d93 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA.mlir @@ -11,14 +11,14 @@ // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit(4,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM)); module @aie_module { AIE.device(xcve2802) { diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir index c7170612fa..e3a6901c52 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA2.mlir @@ -11,15 +11,15 @@ // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit({{.*}},0)); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(3,-1),XAie_LockInit({{.*}},0))); // CHECK: [[bd0]].LockDesc.LockRelEn = XAIE_DISABLE; -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM)); module @aie_module { AIE.device(xcve2802) { diff --git a/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir b/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir index 54f482cc84..44e2a92ec7 100644 --- a/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir +++ b/test/Targets/AIEGenerateXAIE/aie2_tileDMA3.mlir @@ -11,15 +11,15 @@ // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit({{.*}},0),XAie_LockInit(4,1)); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit({{.*}},0),XAie_LockInit(4,1))); // CHECK: [[bd0]].LockDesc.LockAcqEn = XAIE_DISABLE; -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x720, /* len */ 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), /* nextbd */ 0, /* enableNextBd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(7,3), /* bd */ 0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */0, /* dmaDir */ DMA_S2MM, /* BdNum */0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(7,3), /* ChNum */ 0, /* dmaDir */ DMA_S2MM)); module @aie_module { AIE.device(xcve2802) { diff --git a/test/Targets/AIEGenerateXAIE/memTileDMA.mlir b/test/Targets/AIEGenerateXAIE/memTileDMA.mlir index 3e9236993c..6837453892 100644 --- a/test/Targets/AIEGenerateXAIE/memTileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/memTileDMA.mlir @@ -13,28 +13,28 @@ // AIE.end is not the last block. // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x82000, /* len */ 16 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1), {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), /* addrA */ 0x82000, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,1), {{.*}} 0)); // CHECK: XAie_DmaDesc [[bd24:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd24]]), /* addrA */ 0x82000, /* len */ 16 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd24]]), {{.*}} 24, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1), {{.*}} 24); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd24]]), /* addrA */ 0x82000, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd24]]), {{.*}} 24, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd24]]), XAie_TileLoc(2,1), {{.*}} 24)); // CHECK: XAie_DmaDesc [[bd25:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd25]]), /* addrA */ 0x80720, /* len */ 16 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd25]]), {{.*}} 25, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1), {{.*}} 25); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd25]]), /* addrA */ 0x80720, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd25]]), {{.*}} 25, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd25]]), XAie_TileLoc(2,1), {{.*}} 25)); // CHECK: XAie_DmaDesc [[bd1:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80720, /* len */ 16 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1), {{.*}} 1); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), /* addrA */ 0x80720, /* len */ 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,1), {{.*}} 1)); module @aie_module { diff --git a/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir b/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir index 1610dda9b7..8782d9c2f2 100644 --- a/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir +++ b/test/Targets/AIEGenerateXAIE/packet_drop_header.mlir @@ -13,20 +13,20 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 7; // CHECK: y = 0; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4, {{.*}} 0, {{.*}} XAie_PacketInit(3,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4, {{.*}} 0, {{.*}} XAie_PacketInit(3,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // CHECK: x = 7; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} XAIE_SS_PKT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(3,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} XAIE_SS_PKT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(3,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // // This tests the switchbox configuration lowering for packet switched routing diff --git a/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir b/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir index 231fd7d8f8..91d88c27c0 100644 --- a/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir +++ b/test/Targets/AIEGenerateXAIE/packet_shim_header.mlir @@ -12,22 +12,22 @@ // CHECK: mlir_aie_configure_shimdma_70 // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaSetPkt(&([[bd0]]), XAie_PacketInit(10,6)); +// CHECK: __mlir_aie_try(XAie_DmaSetPkt(&([[bd0]]), XAie_PacketInit(10,6))); // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 7; // CHECK: y = 0; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 3); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 3, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 3)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 3, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // CHECK: x = 7; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} XAIE_SS_PKT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, {{.*}} XAIE_SS_PKT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, {{.*}} 0, {{.*}} XAie_PacketInit(10,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // CHECK: x = 7; // CHECK: y = 0; -// CHECK: XAie_EnableShimDmaToAieStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 3); +// CHECK: __mlir_aie_try(XAie_EnableShimDmaToAieStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 3)); // // This tests the shim DMA BD configuration lowering for packet switched routing diff --git a/test/Targets/AIEGenerateXAIE/plio_shim.mlir b/test/Targets/AIEGenerateXAIE/plio_shim.mlir index 601ac981be..c9b348bc66 100644 --- a/test/Targets/AIEGenerateXAIE/plio_shim.mlir +++ b/test/Targets/AIEGenerateXAIE/plio_shim.mlir @@ -19,12 +19,12 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 4; // CHECK: y = 0; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4, NORTH, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 4, NORTH, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2)); // CHECK: x = 4; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, NORTH, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 0); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), SOUTH, 0, NORTH, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 0)); module { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/plio_shimmux.mlir b/test/Targets/AIEGenerateXAIE/plio_shimmux.mlir index b83f4f9d21..f0a553cfbf 100644 --- a/test/Targets/AIEGenerateXAIE/plio_shimmux.mlir +++ b/test/Targets/AIEGenerateXAIE/plio_shimmux.mlir @@ -20,13 +20,13 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 2; // CHECK: y = 0; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2)); // CHECK: x = 2; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 0); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 0)); // CHECK: x = 2; // CHECK: y = 0; -// CHECK: XAie_EnableAieToShimDmaStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 2); +// CHECK: __mlir_aie_try(XAie_EnableAieToShimDmaStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 2)); module { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/shim.mlir b/test/Targets/AIEGenerateXAIE/shim.mlir index 66ec7f3d2f..375a8cb0f5 100644 --- a/test/Targets/AIEGenerateXAIE/shim.mlir +++ b/test/Targets/AIEGenerateXAIE/shim.mlir @@ -12,30 +12,30 @@ // CHECK: mlir_aie_configure_shimdma_20 // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_0(), {{.*}} 16 * 4); -// CHECK: XAie_DmaSetAxi(&([[bd0]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0), {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_0(), {{.*}} 16 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAxi(&([[bd0]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(2,0), {{.*}} 0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,0)); -// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_1(), {{.*}} 4 * 4); -// CHECK: XAie_DmaSetAxi(&([[bd1]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE); -// CHECK: XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1); -// CHECK: XAie_DmaEnableBd(&([[bd1]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,0), {{.*}} 1); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}}0, {{.*}} DMA_S2MM, {{.*}}0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}} 0, {{.*}} DMA_S2MM); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}}0, {{.*}} DMA_MM2S, {{.*}}1); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}} 0, {{.*}} DMA_MM2S); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,0))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}} mlir_aie_external_get_addr_myBuffer_20_1(), {{.*}} 4 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetAxi(&([[bd1]]), {{.*}} 0, {{.*}} 4, {{.*}} 0, {{.*}} 0, {{.*}} XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(2,0), {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}}0, {{.*}} DMA_S2MM, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}} 0, {{.*}} DMA_S2MM)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}}0, {{.*}} DMA_MM2S, {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(2,0), {{.*}} 0, {{.*}} DMA_MM2S)); // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 2; // CHECK: y = 0; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2); -// CHECK: XAie_EnableAieToShimDmaStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 2); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), NORTH, 0, SOUTH, 2)); +// CHECK: __mlir_aie_try(XAie_EnableAieToShimDmaStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 2)); module { diff --git a/test/Targets/AIEGenerateXAIE/shimmux.mlir b/test/Targets/AIEGenerateXAIE/shimmux.mlir index 035ecd2fb1..e3f5fbaaf0 100644 --- a/test/Targets/AIEGenerateXAIE/shimmux.mlir +++ b/test/Targets/AIEGenerateXAIE/shimmux.mlir @@ -13,7 +13,7 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 2; // CHECK: y = 0; -// CHECK: XAie_EnableShimDmaToAieStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 3); +// CHECK: __mlir_aie_try(XAie_EnableShimDmaToAieStrmPort(&(ctx->DevInst), XAie_TileLoc(x,y), 3)); module { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_explicit_elf.mlir b/test/Targets/AIEGenerateXAIE/test_explicit_elf.mlir index 09fbf90ca6..76ae44b4e2 100644 --- a/test/Targets/AIEGenerateXAIE/test_explicit_elf.mlir +++ b/test/Targets/AIEGenerateXAIE/test_explicit_elf.mlir @@ -11,12 +11,12 @@ // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s // CHECK: mlir_aie_configure_cores -// CHECK: XAie_CoreReset(&(ctx->DevInst), XAie_TileLoc(3,3)); -// CHECK: XAie_CoreDisable(&(ctx->DevInst), XAie_TileLoc(3,3)); +// CHECK: __mlir_aie_try(XAie_CoreReset(&(ctx->DevInst), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_CoreDisable(&(ctx->DevInst), XAie_TileLoc(3,3))); // CHECK: XAie_LoadElf(&(ctx->DevInst), XAie_TileLoc(3,3), (const char*)"test.elf",0); // CHECK: mlir_aie_start_cores -// CHECK: XAie_CoreUnreset(&(ctx->DevInst), XAie_TileLoc(3,3)); -// CHECK: XAie_CoreEnable(&(ctx->DevInst), XAie_TileLoc(3,3)); +// CHECK: __mlir_aie_try(XAie_CoreUnreset(&(ctx->DevInst), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_CoreEnable(&(ctx->DevInst), XAie_TileLoc(3,3))); module @test_xaie0 { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_herd_xaie0.mlir b/test/Targets/AIEGenerateXAIE/test_herd_xaie0.mlir index 7aa723628a..6e7e42d027 100644 --- a/test/Targets/AIEGenerateXAIE/test_herd_xaie0.mlir +++ b/test/Targets/AIEGenerateXAIE/test_herd_xaie0.mlir @@ -13,170 +13,170 @@ // CHECK: for (x = ifm_X + 0; x < ifm_X + 1; x += 1) { // CHECK: for (y = ifm_Y + 0; y < ifm_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 0; x < compute_X + 3; x += 1) { // CHECK: for (y = compute_Y + 0; y < compute_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_NORTH(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_NORTH(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_SOUTH(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 3; x < compute_X + 4; x += 1) { // CHECK: for (y = compute_Y + 0; y < compute_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_NORTH(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 0; x < pp_X + 1; x += 1) { // CHECK: for (y = pp_Y + 0; y < pp_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 0; x < pp_X + 1; x += 1) { // CHECK: for (y = pp_Y + 0; y < pp_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 3), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 4), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 0; x < pp_X + 1; x += 1) { // CHECK: for (y = pp_Y + 1; y < pp_Y + 2; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 3), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 3), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 4), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 4), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 0; x < pp_X + 1; x += 1) { // CHECK: for (y = pp_Y + 0; y < pp_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 0), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 0; x < pp_X + 1; x += 1) { // CHECK: for (y = pp_Y + 0; y < pp_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_EAST(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = pp_X + 3; x < pp_X + 4; x += 1) { // CHECK: for (y = pp_Y + 0; y < pp_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_DMA(&(ctx->TileInst[x][y]), 0), // CHECK: XAIETILE_STRSW_MPORT_WEST(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 0; x < compute_X + 1; x += 1) { // CHECK: for (y = compute_Y + 0; y < compute_Y + 1; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 3), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 4), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 3), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 0; x < compute_X + 1; x += 1) { // CHECK: for (y = compute_Y + 1; y < compute_Y + 2; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 3), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 2), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 0; x < compute_X + 1; x += 1) { // CHECK: for (y = compute_Y + 1; y < compute_Y + 2; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: XAIE_ENABLE)); +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 2), // CHECK: XAIETILE_STRSW_MPORT_NORTH(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } // CHECK: for (x = compute_X + 0; x < compute_X + 1; x += 1) { // CHECK: for (y = compute_Y + 1; y < compute_Y + 2; y += 1) { -// CHECK: XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), +// CHECK: __mlir_aie_try(XAieTile_StrmConnectCct(&(ctx->TileInst[x][y]), // CHECK: XAIETILE_STRSW_SPORT_SOUTH(&(ctx->TileInst[x][y]), 1), // CHECK: XAIETILE_STRSW_MPORT_DMA(&(ctx->TileInst[x][y]), 1), -// CHECK: XAIE_ENABLE); +// CHECK: XAIE_ENABLE)); // CHECK: } // CHECK: } diff --git a/test/Targets/AIEGenerateXAIE/test_lock_init.mlir b/test/Targets/AIEGenerateXAIE/test_lock_init.mlir index 4def1d773a..3949e74ffd 100644 --- a/test/Targets/AIEGenerateXAIE/test_lock_init.mlir +++ b/test/Targets/AIEGenerateXAIE/test_lock_init.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s -// CHECK: XAie_LockSetValue(&(ctx->DevInst), XAie_TileLoc(3,3), XAie_LockInit(0, 1)); +// CHECK: __mlir_aie_try(XAie_LockSetValue(&(ctx->DevInst), XAie_TileLoc(3,3), XAie_LockInit(0, 1))); module @test_lock_init { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_ps0_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps0_xaie.mlir index 3da4ae01b4..d392d5140e 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps0_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps0_xaie.mlir @@ -13,12 +13,12 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); // one-to-many, single arbiter module @test_ps0_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps1_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps1_xaie.mlir index 0c0c32ab93..84713b37c3 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps1_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps1_xaie.mlir @@ -13,15 +13,15 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 1, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 1, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1)); // one-to-many, multiple arbiter module @test_ps1_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps2_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps2_xaie.mlir index c51d65c608..fbde484620 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps2_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps2_xaie.mlir @@ -13,15 +13,15 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // many-to-one, single arbiter module @test_ps2_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps3_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps3_xaie.mlir index 885729c3a9..5a6b9fa6d0 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps3_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps3_xaie.mlir @@ -13,15 +13,15 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x3); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x3)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); // partial multicast module @test_ps3_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps4_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps4_xaie.mlir index 1f59446c66..b0198c344a 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps4_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps4_xaie.mlir @@ -13,16 +13,16 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x3); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x3)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); // many-to-many, 2 streams, 1 arbiter module @test_ps4_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps5_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps5_xaie.mlir index d33be07bec..7868034707 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps5_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps5_xaie.mlir @@ -13,18 +13,18 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 1, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 1, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 1)); // many-to-many, 3 streams, 2 arbiters module @test_ps5_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps6_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps6_xaie.mlir index c2c4c786df..f9fa5f898e 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps6_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps6_xaie.mlir @@ -13,18 +13,18 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 1, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x2)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 1, {{.*}} XAie_PacketInit(1,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1F, {{.*}} 1, {{.*}} 0)); // many-to-many, 3 streams, 1 arbiters module @test_ps6_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_ps7_xaie.mlir b/test/Targets/AIEGenerateXAIE/test_ps7_xaie.mlir index 64921a05ed..a9cf407747 100644 --- a/test/Targets/AIEGenerateXAIE/test_ps7_xaie.mlir +++ b/test/Targets/AIEGenerateXAIE/test_ps7_xaie.mlir @@ -13,15 +13,15 @@ // CHECK: mlir_aie_configure_switchboxes // CHECK: x = 0; // CHECK: y = 1; -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0); -// CHECK: XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 0, EAST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmConnCctEnable(&(ctx->DevInst), XAie_TileLoc(x,y), DMA, 1, EAST, 1)); // CHECK: x = 1; // CHECK: y = 1; -// CHECK: XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1E, {{.*}} 0, {{.*}} 0); -// CHECK: XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1); -// CHECK: XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(2,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_StrmPktSwMstrPortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), CORE, 0, {{.*}} XAIE_SS_PKT_DONOT_DROP_HEADER, {{.*}} 0, {{.*}} 0x1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 0, {{.*}} 0, {{.*}} XAie_PacketInit(0,0), {{.*}} 0x1E, {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlavePortEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1)); +// CHECK: __mlir_aie_try(XAie_StrmPktSwSlaveSlotEnable(&(ctx->DevInst), XAie_TileLoc(x,y), WEST, 1, {{.*}} 0, {{.*}} XAie_PacketInit(2,0), {{.*}} 0x1F, {{.*}} 0, {{.*}} 0)); // many-to-one, 3 streams, 1 arbiters module @test_ps7_xaie { diff --git a/test/Targets/AIEGenerateXAIE/test_xaie1.mlir b/test/Targets/AIEGenerateXAIE/test_xaie1.mlir index 4433372aa4..52dd3044ce 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie1.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie1.mlir @@ -11,14 +11,14 @@ // RUN: aie-translate --aie-generate-xaie %s | FileCheck %s // CHECK: XAie_DmaDesc dma_tile33_bd0; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3)); -// CHECK: XAie_DmaSetLock(&(dma_tile33_bd0), XAie_LockInit(0,0),XAie_LockInit(0,1)); -// CHECK: XAie_DmaSetAddrLen(&(dma_tile33_bd0), {{.*}} 0x1400, {{.*}} 256 * 4); -// CHECK: XAie_DmaSetNextBd(&(dma_tile33_bd0), {{.*}} 0, {{.*}} 0); -// CHECK: XAie_DmaEnableBd(&(dma_tile33_bd0)); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3), {{.*}} 0); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}} DMA_MM2S, {{.*}}0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}} 0, /* dmaDir */ DMA_MM2S); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&(dma_tile33_bd0), XAie_LockInit(0,0),XAie_LockInit(0,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&(dma_tile33_bd0), {{.*}} 0x1400, {{.*}} 256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&(dma_tile33_bd0), {{.*}} 0, {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&(dma_tile33_bd0))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &(dma_tile33_bd0), XAie_TileLoc(3,3), {{.*}} 0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}} DMA_MM2S, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}} 0, /* dmaDir */ DMA_MM2S)); module @test_xaie1 { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_xaie2.mlir b/test/Targets/AIEGenerateXAIE/test_xaie2.mlir index c857a783b8..5ba4b29e54 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie2.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie2.mlir @@ -12,21 +12,21 @@ // Test S2MM, BD chaining. // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), {{.*}}1, {{.*}}1); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}}1, {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3)); -// CHECK: XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(0,0),XAie_LockInit(0,1)); -// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}4 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}1); -// CHECK: XAie_DmaEnableBd(&([[bd1]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM, {{.*}}0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(0,0),XAie_LockInit(0,1))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}4 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM)); module @test_xaie2 { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_xaie3.mlir b/test/Targets/AIEGenerateXAIE/test_xaie3.mlir index e9e518efcf..1cb7bc993a 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie3.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie3.mlir @@ -12,7 +12,7 @@ // Test acquire with '1'. Single BD. // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,1),XAie_LockInit(0,0)); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,1),XAie_LockInit(0,0))); module @test_xaie3 { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/test_xaie4.mlir b/test/Targets/AIEGenerateXAIE/test_xaie4.mlir index 665f8c488b..9a6e4b9568 100644 --- a/test/Targets/AIEGenerateXAIE/test_xaie4.mlir +++ b/test/Targets/AIEGenerateXAIE/test_xaie4.mlir @@ -12,23 +12,23 @@ // Test shared BD list. // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3)); -// CHECK: XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,1),XAie_LockInit(0,0)); -// CHECK: XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), {{.*}}0, {{.*}}0); -// CHECK: XAie_DmaEnableBd(&([[bd0]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd0]]), XAie_LockInit(0,1),XAie_LockInit(0,0))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd0]]), {{.*}}0x1000, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}}0, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd0]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(3,3), {{.*}}0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3)); -// CHECK: XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(1,1),XAie_LockInit(1,0)); -// CHECK: XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}256 * 4); -// CHECK: XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}0); -// CHECK: XAie_DmaEnableBd(&([[bd1]])); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_MM2S, {{.*}}0); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_MM2S); -// CHECK: XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM, {{.*}}1); -// CHECK: XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetLock(&([[bd1]]), XAie_LockInit(1,1),XAie_LockInit(1,0))); +// CHECK: __mlir_aie_try(XAie_DmaSetAddrLen(&([[bd1]]), {{.*}}0x1400, {{.*}}256 * 4)); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}}0, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaEnableBd(&([[bd1]]))); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(3,3), {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_MM2S, {{.*}}0)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_MM2S)); +// CHECK: __mlir_aie_try(XAie_DmaChannelPushBdToQueue(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM, {{.*}}1)); +// CHECK: __mlir_aie_try(XAie_DmaChannelEnable(&(ctx->DevInst), XAie_TileLoc(3,3), {{.*}}0, {{.*}}DMA_S2MM)); module @test_xaie3 { AIE.device(xcvc1902) { diff --git a/test/Targets/AIEGenerateXAIE/tileDMA.mlir b/test/Targets/AIEGenerateXAIE/tileDMA.mlir index 4f0a3ae8f3..1a20c51b11 100644 --- a/test/Targets/AIEGenerateXAIE/tileDMA.mlir +++ b/test/Targets/AIEGenerateXAIE/tileDMA.mlir @@ -13,14 +13,14 @@ // AIE.end is not the last block. // CHECK: XAie_DmaDesc [[bd0:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(8,3)); -// CHECK: XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(8,3), {{.*}} 0); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(8,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd0]]), {{.*}} 0, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd0]]), XAie_TileLoc(8,3), {{.*}} 0)); // CHECK: XAie_DmaDesc [[bd1:.*]]; -// CHECK: XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(8,3)); -// CHECK: XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1); -// CHECK: XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(8,3), {{.*}} 1); +// CHECK: __mlir_aie_try(XAie_DmaDescInit(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(8,3))); +// CHECK: __mlir_aie_try(XAie_DmaSetNextBd(&([[bd1]]), {{.*}} 1, {{.*}} 1)); +// CHECK: __mlir_aie_try(XAie_DmaWriteBd(&(ctx->DevInst), &([[bd1]]), XAie_TileLoc(8,3), {{.*}} 1)); module @aie_module { diff --git a/test/dialect/AIE/nd-dma-oob.mlir b/test/dialect/AIE/nd-dma-oob.mlir new file mode 100644 index 0000000000..600b578b94 --- /dev/null +++ b/test/dialect/AIE/nd-dma-oob.mlir @@ -0,0 +1,40 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile14 = AIE.tile(1, 4) + %tile34 = AIE.tile(3, 4) + + AIE.flow(%tile14, DMA : 0, %tile34, DMA : 0) + + %buf14 = AIE.buffer(%tile14) { sym_name = "buf14" } : memref<128xi32> + + %lock14_done = AIE.lock(%tile14, 0) { init = 0 : i32, sym_name = "lock14_done" } + + %mem14 = AIE.mem(%tile14) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + // The following should generate an out-of-bounds error: the second + // repetition of accessing array %buf14 with stride of 128 will + // attempt an access at index 128, which is OOB for a 128xi32 + // memref. + // expected-error@+1 {{Specified stepsize(s) and wrap(s) result in out of bounds access}} + AIE.dmaBd(<%buf14 : memref<128xi32>, 0, 128>, 0, [<128, 2>]) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} \ No newline at end of file diff --git a/test/dialect/AIE/nd-dma-too-many-dims-1.mlir b/test/dialect/AIE/nd-dma-too-many-dims-1.mlir new file mode 100644 index 0000000000..4237408b19 --- /dev/null +++ b/test/dialect/AIE/nd-dma-too-many-dims-1.mlir @@ -0,0 +1,31 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile31 = AIE.tile(3, 1) + + %buf31 = AIE.buffer(%tile31) { sym_name = "buf31" } : memref<128xi32> + + %mem31 = AIE.memTileDMA(%tile31) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + //expected-error@+1 {{Cannot give more than 4 dimensions}} + AIE.dmaBd(<%buf31 : memref<128xi32>, 0, 128>, 0, [<1, 1>, <1, 1>, <1, 1>, <1, 1>, <1, 1>]) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} \ No newline at end of file diff --git a/test/dialect/AIE/nd-dma-too-many-dims-2.mlir b/test/dialect/AIE/nd-dma-too-many-dims-2.mlir new file mode 100644 index 0000000000..b61c0f612c --- /dev/null +++ b/test/dialect/AIE/nd-dma-too-many-dims-2.mlir @@ -0,0 +1,31 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile33 = AIE.tile(3, 3) + + %buf33 = AIE.buffer(%tile33) { sym_name = "buf33" } : memref<128xi32> + + %mem33 = AIE.mem(%tile33) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + //expected-error@+1 {{Cannot give more than 3 dimensions}} + AIE.dmaBd(<%buf33 : memref<128xi32>, 0, 128>, 0, [<1, 1>, <1, 1>, <1, 1>, <1, 1>]) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} \ No newline at end of file diff --git a/test/dialect/AIE/nd-dma-wrong-rank.mlir b/test/dialect/AIE/nd-dma-wrong-rank.mlir new file mode 100644 index 0000000000..5e647ddc76 --- /dev/null +++ b/test/dialect/AIE/nd-dma-wrong-rank.mlir @@ -0,0 +1,38 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile14 = AIE.tile(1, 4) + %tile34 = AIE.tile(3, 4) + + AIE.flow(%tile14, DMA : 0, %tile34, DMA : 0) + + %buf14 = AIE.buffer(%tile14) { sym_name = "buf14" } : memref<3x2x64xi32> + + %lock14_done = AIE.lock(%tile14, 0) { init = 0 : i32, sym_name = "lock14_done" } + + %mem14 = AIE.mem(%tile14) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + // Currently, we only allow multi-dimensional stride/wrap definitons + // on BDs referring to a memref of rank 1. + // expected-error@+1 {{Specifying transfer step sizes and wraps is only supported for }} + AIE.dmaBd(<%buf14 : memref<3x2x64xi32>, 0, 128>, 0, [<2, 8>]) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} \ No newline at end of file diff --git a/test/dialect/AIE/nd-dma-wrong-type.mlir b/test/dialect/AIE/nd-dma-wrong-type.mlir new file mode 100644 index 0000000000..87a8485bd8 --- /dev/null +++ b/test/dialect/AIE/nd-dma-wrong-type.mlir @@ -0,0 +1,40 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --verify-diagnostics %s + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile14 = AIE.tile(1, 4) + %tile34 = AIE.tile(3, 4) + + AIE.flow(%tile14, DMA : 0, %tile34, DMA : 0) + + %buf14 = AIE.buffer(%tile14) { sym_name = "buf14" } : memref<128xi8> + + %lock14_done = AIE.lock(%tile14, 0) { init = 0 : i32, sym_name = "lock14_done" } + + %mem14 = AIE.mem(%tile14) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + // We should ensure multi-dimensional strides/wraps are only used + // on i32 data types, because that is the elemental transfer size + // the hardware does. + // Cast to an i32 memref type if needed. + //expected-error@+1 {{Specifying transfer step sizes and wraps is only supported for }} + AIE.dmaBd(<%buf14 : memref<128xi8>, 0, 128>, 0, [<2, 8>]) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} \ No newline at end of file diff --git a/test/unit_tests/29_aie2_nd_dma_even_odd/.gitignore b/test/unit_tests/29_aie2_nd_dma_even_odd/.gitignore new file mode 100644 index 0000000000..c795b054e5 --- /dev/null +++ b/test/unit_tests/29_aie2_nd_dma_even_odd/.gitignore @@ -0,0 +1 @@ +build \ No newline at end of file diff --git a/test/unit_tests/29_aie2_nd_dma_even_odd/Makefile b/test/unit_tests/29_aie2_nd_dma_even_odd/Makefile new file mode 100644 index 0000000000..0f6cb5a819 --- /dev/null +++ b/test/unit_tests/29_aie2_nd_dma_even_odd/Makefile @@ -0,0 +1,53 @@ +# Contains common definitions used across the Makefiles of all tutorials. + +# MLIR-AIE install directory. If you have sourced utils/env_setup.sh before +# running make, the following should work to find the AIE install directory. +AIE_RUNTIME_LIB ?= $(shell realpath $(dir $(shell which aie-opt))/../runtime_lib) +AIE_INSTALL ?= $(AIE_RUNTIME_LIB)/aarch64 + +# VITIS related variables +VITIS_ROOT ?= $(shell realpath $(dir $(shell which vitis))/../) +VITIS_AIETOOLS_DIR ?= ${VITIS_ROOT}/aietools +VITIS_AIE_INCLUDE_DIR ?= ${VITIS_ROOT}/aietools/data/versal_prod/lib +VITIS_AIE2_INCLUDE_DIR ?= ${VITIS_ROOT}/aietools/data/aie_ml/lib + +# An aarch64 sysroot is required for cross-compiling the host code. The default +# values of these variables assume that you have built a sysroot by running +# make in platforms/vck190_bare_prod, but you can use other aarch64 sysroots by + +MLIR_AIE_SYSROOT ?= ${VITIS_ROOT}/gnu/aarch64/lin/aarch64-linux/aarch64-xilinx-linux/ + +# The libstdc++ version that is installed in the sysroot given above. This is +# used for include and library paths. If you built the sysroot with Vitis +# 2022.2 and PetaLinux 2022.2, libstdc++ 11.2.0 will be installed. +LIBCXX_VERSION ?= 11.2.0 + +# The following flags are passed to both AI core and host compilation for +# aiecc.py invocations. +AIECC_FLAGS += --sysroot=${MLIR_AIE_SYSROOT} --host-target=aarch64-linux-gnu + +CHESSCC_FLAGS = -f -p me -P ${VITIS_AIE_INCLUDE_DIR} -I ${VITIS_AIETOOLS_DIR}/include +CHESS_FLAGS = -P ${VITIS_AIE_INCLUDE_DIR} + +# The following additional flags are only applied for host code. We add the +# necessary search paths for the sysroot so clang++ can find the aarch64 +# includes and libraries. +AIECC_HOST_FLAGS += -I$(AIE_INSTALL)/test_lib/include -I${AIE_INSTALL}/xaiengine/include -I${MLIR_AIE_SYSROOT}/usr/include -I${MLIR_AIE_SYSROOT}/usr/include/c++/${LIBCXX_VERSION} -I${MLIR_AIE_SYSROOT}/usr/include/c++/${LIBCXX_VERSION}/aarch64-xilinx-linux -L${MLIR_AIE_SYSROOT}/usr/lib/aarch64-xilinx-linux/${LIBCXX_VERSION} -L$(AIE_INSTALL)/test_lib/lib -ltest_lib -B${MLIR_AIE_SYSROOT}/usr/lib/aarch64-xilinx-linux/${LIBCXX_VERSION} + +.PHONY: all clean + +all: build/sim + +# Command line mlir-aie compile script "aiecc.py" +# Sysroot and host target used to cross compile host executable +# Local runtime_lib needed for testbench functions +build/test: test.cpp aie.mlir + mkdir -p ${@D} + cd ${@D} && aiecc.py -j4 $(AIECC_FLAGS) ../$(word 2,$^) $(AIECC_HOST_FLAGS) ../$< -o ${@F} + +build/sim : test.cpp aie.mlir + mkdir -p ${@D} + cd ${@D} && aiecc.py -j4 --xchesscc --xbridge --aiesim ../$(word 2,$^) -ggdb -I$(AIE_RUNTIME_LIB)/x86_64/test_lib/include -L$(AIE_RUNTIME_LIB)/x86_64/test_lib/lib -ltest_lib ../$< + +clean: + rm -rf build diff --git a/test/unit_tests/29_aie2_nd_dma_even_odd/aie.mlir b/test/unit_tests/29_aie2_nd_dma_even_odd/aie.mlir new file mode 100644 index 0000000000..8ff74184fe --- /dev/null +++ b/test/unit_tests/29_aie2_nd_dma_even_odd/aie.mlir @@ -0,0 +1,107 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// This tests the multi-dimensional (n-D) address generation function of AIE2 +// buffer descriptors. +// core 14 generates the sequence 0, 1, 2, 3, 4, ... 126, 127, which is pushed +// onto the DMA stream towards core 34. The data is pushed onto the stream in +// the following order, reading from the buffer with s as: +// +// [<2, 8>, <1, 2>, <16, 8>] +// +// This corresponds to sending the first eight even elements from the buffer +// into the stream, followed by the next eight odd elements, and alternating +// so forth. +// +// The DMA receives this data and writes it to a buffer linearly, which is +// checked from the host code to be correct. + +// REQUIRES: valid_xchess_license +// RUN: aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%aie_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %run_on_board ./test.elf +// RUN: aie.mlir.prj/aiesim.sh | FileCheck %s + +// CHECK: AIE2 ISS +// CHECK: PASS! + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile14 = AIE.tile(1, 4) + %tile34 = AIE.tile(3, 4) + + AIE.flow(%tile14, DMA : 0, %tile34, DMA : 0) + + %buf14 = AIE.buffer(%tile14) { sym_name = "buf14" } : memref<128xi32> + %buf34 = AIE.buffer(%tile34) { sym_name = "buf34" } : memref<128xi32> + + %lock14_done = AIE.lock(%tile14, 0) { init = 0 : i32, sym_name = "lock14_done" } + %lock14_sent = AIE.lock(%tile14, 1) { init = 0 : i32, sym_name = "lock14_sent" } + %lock34_wait = AIE.lock(%tile34, 0) { init = 1 : i32, sym_name = "lock34_wait" } + %lock34_recv = AIE.lock(%tile34, 1) { init = 0 : i32, sym_name = "lock34_recv" } + + // This core stores the sequence of numbers 0, 1, 2, 3, ... into + // buffer buf14, s.t. buf14[i] == i. + // After the array has been written, lock14 signifies core14 is done. + %core14 = AIE.core(%tile14) { + %i0 = arith.constant 0 : index + %i1 = arith.constant 1 : index + %i128 = arith.constant 128 : index + %c0 = arith.constant 0 : i32 + %c1 = arith.constant 1 : i32 + + scf.for %it = %i0 to %i128 step %i1 iter_args(%c = %c0) -> i32 { + memref.store %c, %buf14[%it] : memref<128xi32> + %cp = arith.addi %c1, %c : i32 + scf.yield %cp : i32 + } + + AIE.useLock(%lock14_done, "Release", 1) + + AIE.end + } + + // No code in this core; however, we do have a DMA that receives a + // data from the stream and stores it in a buffer. + %core34 = AIE.core(%tile34) { + AIE.end + } + + // When core (1, 4) is done (lock14 released), its DMA will push all + // of buffer14 onto the stream. + // The order in which the buffer is pushed onto the stream is defined + // by the new attribute at the end of the dmaBd operation. + %mem14 = AIE.mem(%tile14) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + AIE.useLock(%lock14_done, "AcquireGreaterEqual", 1) + ////////// new ////////// + AIE.dmaBd(<%buf14 : memref<128xi32>, 0, 128>, 0, [<16, 8>, <1, 2>, <2, 8>]) + // s, w s, w s, w + // dim 0, dim 1, dim 2 + AIE.useLock(%lock14_sent, "Release", 1) + AIE.nextBd ^end + ^end: + AIE.end + } + + %mem34 = AIE.mem(%tile34) { + %dstDma = AIE.dmaStart("S2MM", 0, ^bd0, ^end) + ^bd0: + AIE.useLock(%lock34_wait, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf34 : memref<128xi32>, 0, 128>, 0) + AIE.useLock(%lock34_recv, "Release", 1) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} diff --git a/test/unit_tests/29_aie2_nd_dma_even_odd/test.cpp b/test/unit_tests/29_aie2_nd_dma_even_odd/test.cpp new file mode 100644 index 0000000000..a460614570 --- /dev/null +++ b/test/unit_tests/29_aie2_nd_dma_even_odd/test.cpp @@ -0,0 +1,97 @@ +//===- test.cpp -------------------------------------------------*- C++ -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +#include "test_library.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "aie_inc.cpp" + +void populate_expected(int *buf) { + const int stepsizes[3] = {2, 1, 16}; + const int wraps[3] = {8, 2, 8}; + int l = 0; + for (int i = 0; i < wraps[2]; i++) { + for (int j = 0; j < wraps[1]; j++) { + for (int k = 0; k < wraps[0]; k++) { + int i_ = i * stepsizes[2]; + int j_ = j * stepsizes[1]; + int k_ = k * stepsizes[0]; + buf[l] = i_ + j_ + k_; + l++; + } + } + } +} + +void read_into(aie_libxaie_ctx_t *_xaie, int *buf) { + for (int i = 0; i < 128; i++) { + buf[i] = mlir_aie_read_buffer_buf34(_xaie, i); + } +} + +void print_buf(int *buf) { + for (int i = 0; i < 128; i++) { + printf("%3d ", buf[i]); + if (0 == (i + 1) % 8) { + printf("\n"); + } + } +} + +int main(int argc, char *argv[]) { + int errors = 0; + int seen[128]; + int expected[128]; + + aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie(); + mlir_aie_init_device(_xaie); + mlir_aie_configure_cores(_xaie); + mlir_aie_configure_switchboxes(_xaie); + mlir_aie_configure_dmas(_xaie); + mlir_aie_initialize_locks(_xaie); + mlir_aie_start_cores(_xaie); + + // After this lock is acquired, the kernels have completed and buf34 + // is populated. + __mlir_aie_try((AieRC)mlir_aie_acquire_lock34_recv(_xaie, -1, 5000)); + read_into(_xaie, seen); + + mlir_aie_deinit_libxaie(_xaie); + + // Compare results. + populate_expected(expected); + for (int i = 0; i < 128; i++) { + if (expected[i] != seen[i]) { + errors = 1; + printf("Mismatch at index %d: %d != %d.\n", i, expected[i], seen[i]); + } + } + if (0 == errors) { + print_buf(seen); + printf("PASS!\n"); + } else { + printf("Expected:\n"); + print_buf(expected); + printf("But got:\n"); + print_buf(seen); + printf("FAIL.\n"); + } + + return errors + 42; +} diff --git a/test/unit_tests/30_aie2_nd_dma_transpose_repeat/.gitignore b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/.gitignore new file mode 100644 index 0000000000..c795b054e5 --- /dev/null +++ b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/.gitignore @@ -0,0 +1 @@ +build \ No newline at end of file diff --git a/test/unit_tests/30_aie2_nd_dma_transpose_repeat/Makefile b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/Makefile new file mode 100644 index 0000000000..0f6cb5a819 --- /dev/null +++ b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/Makefile @@ -0,0 +1,53 @@ +# Contains common definitions used across the Makefiles of all tutorials. + +# MLIR-AIE install directory. If you have sourced utils/env_setup.sh before +# running make, the following should work to find the AIE install directory. +AIE_RUNTIME_LIB ?= $(shell realpath $(dir $(shell which aie-opt))/../runtime_lib) +AIE_INSTALL ?= $(AIE_RUNTIME_LIB)/aarch64 + +# VITIS related variables +VITIS_ROOT ?= $(shell realpath $(dir $(shell which vitis))/../) +VITIS_AIETOOLS_DIR ?= ${VITIS_ROOT}/aietools +VITIS_AIE_INCLUDE_DIR ?= ${VITIS_ROOT}/aietools/data/versal_prod/lib +VITIS_AIE2_INCLUDE_DIR ?= ${VITIS_ROOT}/aietools/data/aie_ml/lib + +# An aarch64 sysroot is required for cross-compiling the host code. The default +# values of these variables assume that you have built a sysroot by running +# make in platforms/vck190_bare_prod, but you can use other aarch64 sysroots by + +MLIR_AIE_SYSROOT ?= ${VITIS_ROOT}/gnu/aarch64/lin/aarch64-linux/aarch64-xilinx-linux/ + +# The libstdc++ version that is installed in the sysroot given above. This is +# used for include and library paths. If you built the sysroot with Vitis +# 2022.2 and PetaLinux 2022.2, libstdc++ 11.2.0 will be installed. +LIBCXX_VERSION ?= 11.2.0 + +# The following flags are passed to both AI core and host compilation for +# aiecc.py invocations. +AIECC_FLAGS += --sysroot=${MLIR_AIE_SYSROOT} --host-target=aarch64-linux-gnu + +CHESSCC_FLAGS = -f -p me -P ${VITIS_AIE_INCLUDE_DIR} -I ${VITIS_AIETOOLS_DIR}/include +CHESS_FLAGS = -P ${VITIS_AIE_INCLUDE_DIR} + +# The following additional flags are only applied for host code. We add the +# necessary search paths for the sysroot so clang++ can find the aarch64 +# includes and libraries. +AIECC_HOST_FLAGS += -I$(AIE_INSTALL)/test_lib/include -I${AIE_INSTALL}/xaiengine/include -I${MLIR_AIE_SYSROOT}/usr/include -I${MLIR_AIE_SYSROOT}/usr/include/c++/${LIBCXX_VERSION} -I${MLIR_AIE_SYSROOT}/usr/include/c++/${LIBCXX_VERSION}/aarch64-xilinx-linux -L${MLIR_AIE_SYSROOT}/usr/lib/aarch64-xilinx-linux/${LIBCXX_VERSION} -L$(AIE_INSTALL)/test_lib/lib -ltest_lib -B${MLIR_AIE_SYSROOT}/usr/lib/aarch64-xilinx-linux/${LIBCXX_VERSION} + +.PHONY: all clean + +all: build/sim + +# Command line mlir-aie compile script "aiecc.py" +# Sysroot and host target used to cross compile host executable +# Local runtime_lib needed for testbench functions +build/test: test.cpp aie.mlir + mkdir -p ${@D} + cd ${@D} && aiecc.py -j4 $(AIECC_FLAGS) ../$(word 2,$^) $(AIECC_HOST_FLAGS) ../$< -o ${@F} + +build/sim : test.cpp aie.mlir + mkdir -p ${@D} + cd ${@D} && aiecc.py -j4 --xchesscc --xbridge --aiesim ../$(word 2,$^) -ggdb -I$(AIE_RUNTIME_LIB)/x86_64/test_lib/include -L$(AIE_RUNTIME_LIB)/x86_64/test_lib/lib -ltest_lib ../$< + +clean: + rm -rf build diff --git a/test/unit_tests/30_aie2_nd_dma_transpose_repeat/aie.mlir b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/aie.mlir new file mode 100644 index 0000000000..0315c68763 --- /dev/null +++ b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/aie.mlir @@ -0,0 +1,86 @@ +//===- aie.mlir ------------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// This tests the multi-dimensional (n-D) address generation function of AIE2 +// buffer descriptors. + +// REQUIRES: valid_xchess_license +// RUN: aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%aie_runtime_lib%/test_lib/lib -ltest_lib +// RUN: %run_on_board ./test.elf +// RUN: aie.mlir.prj/aiesim.sh | FileCheck %s + +// CHECK: AIE2 ISS +// CHECK: PASS! + +module @tutorial_2b { + + AIE.device(xcve2802) { + %tile14 = AIE.tile(1, 4) + %tile34 = AIE.tile(3, 4) + + AIE.flow(%tile14, DMA : 0, %tile34, DMA : 0) + + %buf14 = AIE.buffer(%tile14) { sym_name = "buf14" } : memref<128xi32> + %buf34 = AIE.buffer(%tile34) { sym_name = "buf34" } : memref<128xi32> + + %lock14_done = AIE.lock(%tile14, 0) { init = 0 : i32, sym_name = "lock14_done" } + %lock14_sent = AIE.lock(%tile14, 1) { init = 0 : i32, sym_name = "lock14_sent" } + %lock34_wait = AIE.lock(%tile34, 0) { init = 1 : i32, sym_name = "lock34_wait" } + %lock34_recv = AIE.lock(%tile34, 1) { init = 0 : i32, sym_name = "lock34_recv" } + + %core14 = AIE.core(%tile14) { + %i0 = arith.constant 0 : index + %i1 = arith.constant 1 : index + %i128 = arith.constant 128 : index + %c0 = arith.constant 0 : i32 + %c1 = arith.constant 1 : i32 + + scf.for %it = %i0 to %i128 step %i1 iter_args(%c = %c0) -> i32 { + memref.store %c, %buf14[%it] : memref<128xi32> + %cp = arith.addi %c1, %c : i32 + scf.yield %cp : i32 + } + + AIE.useLock(%lock14_done, "Release", 1) + + AIE.end + } + + %core34 = AIE.core(%tile34) { + AIE.end + } + + %mem14 = AIE.mem(%tile14) { + %srcDma = AIE.dmaStart("MM2S", 0, ^bd0, ^end) + ^bd0: + AIE.useLock(%lock14_done, "AcquireGreaterEqual", 1) + ////////// new ////////// + AIE.dmaBd(<%buf14 : memref<128xi32>, 0, 128>, 0, [<1, 2>, <1, 8>, <8, 8>]) + // s, w s, w s, w + // dim 0, dim 1, dim 2 + AIE.useLock(%lock14_sent, "Release", 1) + AIE.nextBd ^end + ^end: + AIE.end + } + + %mem34 = AIE.mem(%tile34) { + %dstDma = AIE.dmaStart("S2MM", 0, ^bd0, ^end) + ^bd0: + AIE.useLock(%lock34_wait, "AcquireGreaterEqual", 1) + AIE.dmaBd(<%buf34 : memref<128xi32>, 0, 128>, 0) + AIE.useLock(%lock34_recv, "Release", 1) + AIE.nextBd ^end + ^end: + AIE.end + } + + } +} diff --git a/test/unit_tests/30_aie2_nd_dma_transpose_repeat/test.cpp b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/test.cpp new file mode 100644 index 0000000000..befec57b5f --- /dev/null +++ b/test/unit_tests/30_aie2_nd_dma_transpose_repeat/test.cpp @@ -0,0 +1,102 @@ +//===- test.cpp -------------------------------------------------*- C++ -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2023, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +#include "test_library.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "aie_inc.cpp" + +void populate_expected(int *buf) { + const int stepsizes[3] = {8, 1, 1}; + const int wraps[3] = {8, 8, 2}; + int l = 0; + for (int i = 0; i < wraps[2]; i++) { + for (int j = 0; j < wraps[1]; j++) { + for (int k = 0; k < wraps[0]; k++) { + int i_ = i * stepsizes[2]; + int j_ = j * stepsizes[1]; + int k_ = k * stepsizes[0]; + buf[l] = i_ + j_ + k_; + l++; + } + } + } +} + +void read_into(aie_libxaie_ctx_t *_xaie, int *buf) { + for (int i = 0; i < 128; i++) { + buf[i] = mlir_aie_read_buffer_buf34(_xaie, i); + } +} + +void print_buf(int *buf) { + for (int i = 0; i < 128; i++) { + printf("%3d ", buf[i]); + if (0 == (i + 1) % 8) { + printf("\n"); + } + } +} + +int main(int argc, char *argv[]) { + int errors = 0; + int seen[128]; + int expected[128]; + + // Boilerplate setup code + aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie(); + mlir_aie_init_device(_xaie); + mlir_aie_configure_cores(_xaie); + mlir_aie_configure_switchboxes(_xaie); + mlir_aie_configure_dmas(_xaie); + mlir_aie_initialize_locks(_xaie); + mlir_aie_start_cores(_xaie); + + // After this lock is acquired, the kernels have completed and buf34 + // is populated. + assert(XAIE_OK == mlir_aie_acquire_lock34_recv(_xaie, -1, 5000)); + + // Read buf34 into seen. + read_into(_xaie, seen); + + // Tear down. + mlir_aie_deinit_libxaie(_xaie); + + // Compare results to expected results. + populate_expected(expected); + for (int i = 0; i < 128; i++) { + if (expected[i] != seen[i]) { + errors = 1; + printf("Mismatch at index %d: %d != %d.\n", i, expected[i], seen[i]); + } + } + + if (0 == errors) { + print_buf(seen); + printf("PASS!\n"); + } else { + printf("Expected:\n"); + print_buf(expected); + printf("But got:\n"); + print_buf(seen); + printf("FAIL.\n"); + } + + return errors + 42; +} diff --git a/utils/setup_python_packages.sh b/utils/setup_python_packages.sh index eb19ef3f02..070252f941 100755 --- a/utils/setup_python_packages.sh +++ b/utils/setup_python_packages.sh @@ -18,7 +18,7 @@ python3 -m virtualenv sandbox if [ -r sandbox/local/bin/activate ]; then source sandbox/local/bin/activate else - source sandbox/local/activate + source sandbox/bin/activate fi python3 -m pip install --upgrade pip python3 -m pip install -r utils/requirements.txt