From 6723d6d31d208facca6bfaba4d5f8c3136dd6373 Mon Sep 17 00:00:00 2001 From: Lina Yu <108146828+linay-xsj@users.noreply.github.com> Date: Mon, 17 Jul 2023 11:17:00 -0700 Subject: [PATCH] Replace xme_ca_udm_dbg with xca_udm_dbg --aiearch aie-ml in the unit_tests/aievec_tests (#546) --- .../aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc | 2 +- .../bf16_float_add_reduce/bf16_float_add_reduce.mlir | 4 ++-- .../aievec_tests/bf16_float_add_reduce/testbench.cc | 2 +- .../aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc | 2 +- .../aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc | 2 +- .../aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir | 4 ++-- .../aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir | 4 ++-- .../aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir | 4 ++-- .../aievec_tests/float_add_reduce/float_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_add_reduce/testbench.cc | 2 +- .../aievec_tests/float_max_reduce/float_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_max_reduce/testbench.cc | 2 +- .../aievec_tests/float_min_reduce/float_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_min_reduce/testbench.cc | 2 +- .../floatxfloat_add_elem/floatxfloat_add_elem.mlir | 4 ++-- .../floatxfloat_max_elem/floatxfloat_max_elem.mlir | 4 ++-- .../floatxfloat_min_elem/floatxfloat_min_elem.mlir | 4 ++-- .../aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir | 4 ++-- .../floatxfloat_sub_elem/floatxfloat_sub_elem.mlir | 4 ++-- .../aievec_tests/i16_add_reduce/i16_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc | 2 +- .../aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc | 2 +- .../aievec_tests/i16_max_reduce/i16_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc | 2 +- .../aievec_tests/i16_min_reduce/i16_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc | 2 +- .../aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc | 2 +- .../aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir | 4 ++-- .../conv2d_i16_after_polygeist.mlir | 2 +- .../conv2d_i16_after_polygeist_2.mlir | 2 +- .../aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir | 2 +- .../gemm64_int16_unroll32_after_polygeist.mlir | 2 +- .../aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir | 4 ++-- .../i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir | 4 ++-- .../conv2d_uij_i16_noinit.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i32_add_reduce/i32_add_reduce.mlir | 4 ++-- .../aievec_tests/i32_max_reduce/i32_max_reduce.mlir | 4 ++-- .../aievec_tests/i32_min_reduce/i32_min_reduce.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir | 2 +- .../aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir | 4 ++-- .../i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir | 4 ++-- .../aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir | 4 ++-- .../conv2d_i8_after_polygeist.mlir | 2 +- .../aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir | 4 ++-- .../conv2d_uij_i8_noinit.mlir | 4 ++-- .../conv2d_uij_i8_init.mlir | 2 +- .../conv2d_uij_i8_noinit_unsorted.mlir | 2 +- .../aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir | 4 ++-- 81 files changed, 142 insertions(+), 142 deletions(-) diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir index 5b0f8a02a7..fe0d2df12b 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc index 47175e7173..0775761d7d 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir index 95772f35ca..6b83675545 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc index 7043bd0628..e16a2439b2 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir index e0b8e04d1a..74e6780d0b 100644 --- a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc index 830544efb2..276c1c4b6b 100644 --- a/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir index fb81df855f..c873695c5c 100644 --- a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc index 186152df54..3e0b003b2f 100644 --- a/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir index edad465910..a720089936 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir index e921edacc9..993155b2a3 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir index 98037e4d91..bf963fea87 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir index a3ad790b66..9ac3e48293 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir index 1468307ecb..80dd73dd83 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir index e7564b41d4..65822aeb12 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir index d430a202dc..b2d8d842a1 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir index 3988504d4e..76fcd21838 100644 --- a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir index c1f87ee5c7..bce09ebd64 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc index ab78bae2e9..b3ef49c84b 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir index 3ebc3294cc..3c16b931bd 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc index f4f81768bf..8a905d5ce1 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir index 2156789be2..c68a7abccb 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc index 74fa8efedd..dfe0e65ab0 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir index d8c302f0c8..d60ef74de2 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir index e1ebe7a467..d8bc52873d 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir index 59e7662bac..e910b2bc42 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir index fb896820b8..ea2e8ada00 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir index 816c2fba32..e337fe3399 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir index 86916c04d1..1903750935 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc index 34f5fe20c6..b85dd08b3c 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir index 96f5d93515..18f5bb444c 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc index 7db30836b7..bb58b250da 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) int32_t g_out0[OUT0_SIZE]; alignas(32) int32_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir index 5102486bb9..ae3b3810c0 100644 --- a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc index d39407348a..9db86eacfe 100644 --- a/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir index b76ca9aecd..ca6c1c1c36 100644 --- a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc index 73cc78c3a9..0d8314492c 100644 --- a/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir index 5cf5c86949..79db87115c 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc b/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc index 544ab504a9..7e637aa830 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc @@ -13,7 +13,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir index a4267fb920..6ff870f41d 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir index 2d1e54084b..3ef9f9184d 100644 --- a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir index fc96a6ba72..e615422795 100644 --- a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir b/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir index 887e2d4b43..531975f52e 100644 --- a/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc //RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module { func.func @matmul(%arg0: memref<64x64xi16>, %arg1: memref<64x64xi16>, %arg2: memref<64x64xi16>) { diff --git a/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir b/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir index b310016efa..a062604807 100644 --- a/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // XFAIL: * diff --git a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir index 1e5696eb61..14b7e1c97a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir index 44c3a95c1a..8a1c04ac6a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir index f0ea1d0cc7..aadc2d3799 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir index e153875d54..1aea071f05 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir index 7fe37b27eb..08ecee86cc 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir index b533024b02..172d569531 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir b/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir index bc12daf631..62bf84570a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir @@ -1,11 +1,11 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml shift=10" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi16>, %B: memref<9xi16>, %C: memref<16x256xi16>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir index 9e706f74fe..4d8b435576 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir index f512f9a80d..4308e529d8 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir index 780465a791..86d5f97cbb 100644 --- a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir index caa1a31be2..8a43822cdb 100644 --- a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir index 7d72729dec..b5d0c5a74d 100644 --- a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir index 9e121ff8ff..b7753c1254 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir index 6f1efb9836..74f0da4d66 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir b/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir index e03d11ac9d..df5ad5da72 100644 --- a/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc //RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module { func.func @matmul(%arg0: memref<64x64xi32>, %arg1: memref<64x64xi32>, %arg2: memref<64x64xi32>) { affine.for %arg3 = 0 to 64 { diff --git a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir index 8b2c999f31..8bb4cf0fac 100644 --- a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir index d4ec7d58c8..93647d1ff3 100644 --- a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir index 4b54dedf19..ad66d1111e 100644 --- a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir index 72e3b6876d..427cbd4d92 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir index 49c4c92396..7a586595c4 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir index fb3c2966c6..24626ec4db 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir index e4a507be5f..d57a4dfaf0 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir index 4e6acd2110..316004af15 100644 --- a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir index d8365417c9..8736f5c161 100644 --- a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir index e14b894f9a..d2b2d12dce 100644 --- a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir index 83afad04dc..5c2d636f19 100644 --- a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir index 701a157d61..a907d0e2d7 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir index 3b3bd21fb8..d41d3efe90 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir b/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir index ea5defc593..f493b6b5bc 100644 --- a/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize="shift=0 dup-factor=2" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir index 3f95c33d06..d5c497d854 100644 --- a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir index 9818c36c1d..dc86667bad 100644 --- a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir index 867f7d165c..255bd17950 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir index 36e51ab4ec..4bf7202271 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir index 1887b89a7e..1f28f7c775 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir index f5d29d2114..fca8858ed6 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir @@ -1,11 +1,11 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize="shift=0 dup-factor=2" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir index bdd2e230df..9fc88a5416 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir index b5de2e6735..3a90c1c8dd 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir index 018f26c612..d267924eb0 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir index 9915dd12a2..31e56eeae8 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module {