From 7e77c101f0ac6e96e40327998d51ffda52d4f2d7 Mon Sep 17 00:00:00 2001 From: James Lin Date: Wed, 20 Sep 2023 10:50:30 -0500 Subject: [PATCH] Add tosa-to-tensor pass to fix regression (#645) * Add tosa-to-tensor pass to fix regression of tosa broadcast tests --- .../bf16xbf16_sub_elem_2d_broadcast_1d.mlir | 2 +- .../bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir | 2 +- .../i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir | 2 +- .../i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d/bf16xbf16_sub_elem_2d_broadcast_1d.mlir b/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d/bf16xbf16_sub_elem_2d_broadcast_1d.mlir index 8c6feb8ad2..02d7c88b01 100644 --- a/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d/bf16xbf16_sub_elem_2d_broadcast_1d.mlir +++ b/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d/bf16xbf16_sub_elem_2d_broadcast_1d.mlir @@ -2,7 +2,7 @@ // Copyright (C) 2023, Advanced Micro Devices, Inc. // REQUIRES: valid_xchess_license -// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg))" -o linalg.mlir +// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg, tosa-to-tensor))" -o linalg.mlir // RUN: mlir-opt linalg.mlir --linalg-fuse-elementwise-ops --eliminate-empty-tensors --empty-tensor-to-alloc-tensor --one-shot-bufferize="allow-return-allocs allow-unknown-ops bufferize-function-boundaries function-boundary-type-conversion=identity-layout-map" --drop-equivalent-buffer-results --buffer-results-to-out-params --buffer-deallocation --canonicalize --cse --convert-linalg-to-affine-loops --affine-super-vectorize="virtual-vector-size=16" -o affine.mlir // RUN: aie-opt affine.mlir --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o aievec.mlir // RUN: aie-translate aievec.mlir -aieml=true --aievec-to-cpp -o dut.cc diff --git a/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d_reshape/bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir b/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d_reshape/bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir index c37bc77d9e..26b6d5b76c 100644 --- a/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d_reshape/bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir +++ b/test/Integration/Dialect/TOSA/bf16xbf16_sub_elem_2d_broadcast_1d_reshape/bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir @@ -2,7 +2,7 @@ // Copyright (C) 2023, Advanced Micro Devices, Inc. // REQUIRES: valid_xchess_license -// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg))" -o linalg.mlir +// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg, tosa-to-tensor))" -o linalg.mlir // RUN: mlir-opt linalg.mlir --linalg-fuse-elementwise-ops --eliminate-empty-tensors --empty-tensor-to-alloc-tensor --one-shot-bufferize="allow-return-allocs allow-unknown-ops bufferize-function-boundaries function-boundary-type-conversion=identity-layout-map" --drop-equivalent-buffer-results --buffer-results-to-out-params --buffer-deallocation --canonicalize --cse --convert-linalg-to-affine-loops --affine-super-vectorize="virtual-vector-size=16" -o affine.mlir // RUN: aie-opt affine.mlir --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o aievec.mlir // RUN: aie-translate aievec.mlir -aieml=true --aievec-to-cpp -o dut.cc diff --git a/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_1d_unit_dim/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir b/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_1d_unit_dim/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir index 8e17485218..1903e1d647 100644 --- a/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_1d_unit_dim/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir +++ b/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_1d_unit_dim/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir @@ -2,7 +2,7 @@ // Copyright (C) 2023, Advanced Micro Devices, Inc. // REQUIRES: valid_xchess_license -// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg))" -o linalg.mlir +// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg, tosa-to-tensor))" -o linalg.mlir // RUN: mlir-opt linalg.mlir --linalg-fuse-elementwise-ops --eliminate-empty-tensors --empty-tensor-to-alloc-tensor --one-shot-bufferize="allow-return-allocs allow-unknown-ops bufferize-function-boundaries function-boundary-type-conversion=identity-layout-map" --drop-equivalent-buffer-results --buffer-results-to-out-params --buffer-deallocation --canonicalize --cse --convert-linalg-to-affine-loops --affine-super-vectorize="virtual-vector-size=32" -o affine.mlir // RUN: aie-opt affine.mlir --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o aievec.mlir // RUN: aie-translate aievec.mlir -aieml=true --aievec-to-cpp -o dut.cc diff --git a/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_scalar/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir b/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_scalar/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir index 85fa8de4c0..0f08b0d0d7 100644 --- a/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_scalar/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir +++ b/test/Integration/Dialect/TOSA/i16xi16_sub_elem_2d_broadcast_scalar/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir @@ -2,7 +2,7 @@ // Copyright (C) 2023, Advanced Micro Devices, Inc. // REQUIRES: valid_xchess_license -// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg))" -o linalg.mlir +// RUN: mlir-opt %s --pass-pipeline="builtin.module(func.func(tosa-make-broadcastable, tosa-to-linalg-named, tosa-to-linalg, tosa-to-tensor))" -o linalg.mlir // RUN: mlir-opt linalg.mlir --linalg-fuse-elementwise-ops --eliminate-empty-tensors --empty-tensor-to-alloc-tensor --one-shot-bufferize="allow-return-allocs allow-unknown-ops bufferize-function-boundaries function-boundary-type-conversion=identity-layout-map" --drop-equivalent-buffer-results --buffer-results-to-out-params --buffer-deallocation --canonicalize --cse --convert-linalg-to-affine-loops --affine-super-vectorize="virtual-vector-size=32" -o affine.mlir // RUN: aie-opt affine.mlir --convert-vector-to-aievec="aie-target=aieml" -lower-affine -o aievec.mlir // RUN: aie-translate aievec.mlir -aieml=true --aievec-to-cpp -o dut.cc