From 136c516cab9939f0e66102a56ba27e84f7463628 Mon Sep 17 00:00:00 2001 From: Lina Yu Date: Mon, 10 Jul 2023 11:06:08 -0700 Subject: [PATCH 1/3] Implement vector reduction add, reduction min, and reduction max in auto vectorizer with different input and output data types --- .../Transforms/VectorToAIEVecConversions.cpp | 541 ++++++++++++------ .../AIEVecToCpp/TranslateAIEVecToCpp.cpp | 5 + .../VectorToAIEVec/test-arith-aie2.mlir | 14 + .../bf16_float_add_reduce.mlir | 20 + .../bf16_float_add_reduce/defines.h | 3 + .../aievec_tests/bf16_float_add_reduce/dut.cc | 46 ++ .../bf16_float_add_reduce/testbench.cc | 57 ++ .../bf16xfloat_add_elem.mlir | 26 + .../aievec_tests/bf16xf32_add_elem/defines.h | 4 + .../aievec_tests/bf16xf32_add_elem/dut.cc | 16 + .../bf16xf32_add_elem/testbench.cc | 55 ++ .../aievec_tests/i16_i32_add_reduce/defines.h | 3 + .../aievec_tests/i16_i32_add_reduce/dut.cc | 34 ++ .../i16_i32_add_reduce.mlir | 20 + .../i16_i32_add_reduce/testbench.cc | 55 ++ .../aievec_tests/i8_i32_add_reduce/defines.h | 3 + .../aievec_tests/i8_i32_add_reduce/dut.cc | 37 ++ .../i8_i32_add_reduce/i8_i32_add_reduce.mlir | 20 + .../i8_i32_add_reduce/testbench.cc | 55 ++ 19 files changed, 842 insertions(+), 172 deletions(-) create mode 100644 test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir create mode 100644 test/unit_tests/aievec_tests/bf16_float_add_reduce/defines.h create mode 100644 test/unit_tests/aievec_tests/bf16_float_add_reduce/dut.cc create mode 100644 test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc create mode 100644 test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir create mode 100644 test/unit_tests/aievec_tests/bf16xf32_add_elem/defines.h create mode 100644 test/unit_tests/aievec_tests/bf16xf32_add_elem/dut.cc create mode 100644 test/unit_tests/aievec_tests/bf16xf32_add_elem/testbench.cc create mode 100644 test/unit_tests/aievec_tests/i16_i32_add_reduce/defines.h create mode 100644 test/unit_tests/aievec_tests/i16_i32_add_reduce/dut.cc create mode 100644 test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir create mode 100644 test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc create mode 100644 test/unit_tests/aievec_tests/i8_i32_add_reduce/defines.h create mode 100644 test/unit_tests/aievec_tests/i8_i32_add_reduce/dut.cc create mode 100644 test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir create mode 100644 test/unit_tests/aievec_tests/i8_i32_add_reduce/testbench.cc diff --git a/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp b/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp index ae7b380e21..0f79414a9e 100644 --- a/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp +++ b/lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp @@ -234,12 +234,11 @@ static aievec::CmpOp createCmpOpAieML(ConversionPatternRewriter &rewriter, template static void generateAIEVecOpsForReductionOp(ConversionPatternRewriter &rewriter, vector::ReductionOp srcOp, - int shiftIndex) { + int shiftIndex, Value curValue) { assert(shiftIndex > 0 && (shiftIndex & (shiftIndex - 1)) == 0 && "shiftIndex must be power of 2"); Location loc = srcOp.getLoc(); - Value curValue = srcOp.getVector(); VectorType vType = dyn_cast(curValue.getType()); Type scalarType = vType.getElementType(); SmallVector sources = {curValue}; @@ -267,92 +266,6 @@ static void generateAIEVecOpsForReductionOp(ConversionPatternRewriter &rewriter, return; } -static void generateReductionOpForFloat(ConversionPatternRewriter &rewriter, - vector::ReductionOp srcOp, - int shiftIndex) { - assert(shiftIndex > 0 && (shiftIndex & (shiftIndex - 1)) == 0 && - "shiftIndex must be power of 2"); - - Location loc = srcOp.getLoc(); - Value curValue = srcOp.getVector(); - VectorType vType = dyn_cast(curValue.getType()); - - Type scalarType = vType.getElementType(); - aievec::CastOp curOp = nullptr; - unsigned elWidth = scalarType.getIntOrFloatBitWidth(); - assert(elWidth == 32 && "scalar type should be float"); - - for (int id = shiftIndex; id > 0; id /= 2) { - arith::ConstantOp constOp = rewriter.create( - loc, rewriter.getI32IntegerAttr(id * elWidth / 8)); - - auto shiftBytesOp = rewriter.create( - loc, vType, curValue, curValue, constOp.getResult()); - - auto lCastOp = rewriter.create(loc, vType, curValue, - /*isResAcc*/ true); - auto rCastOp = - rewriter.create(loc, vType, shiftBytesOp.getResult(), - /*isResAcc*/ true); - auto elemOp = rewriter.create( - loc, lCastOp.getResult().getType(), lCastOp.getResult(), - rCastOp.getResult()); - curOp = rewriter.create(loc, vType, elemOp.getResult(), - /*isResAcc*/ false); - - curValue = curOp.getResult(); - } - - arith::ConstantOp zeroConstOp = - rewriter.create(loc, rewriter.getI32IntegerAttr(0)); - rewriter.replaceOpWithNewOp(srcOp, scalarType, curOp, - zeroConstOp.getResult()); -} - -static void generateReductionOpForBFloat16(ConversionPatternRewriter &rewriter, - vector::ReductionOp srcOp, - int shiftIndex) { - assert(shiftIndex > 0 && (shiftIndex & (shiftIndex - 1)) == 0 && - "shiftIndex must be power of 2"); - - Value curValue = srcOp.getVector(); - VectorType vType = dyn_cast(curValue.getType()); - - Type scalarType = vType.getElementType(); - Location loc = srcOp.getLoc(); - Type accType = getVectorOpDestType(vType, /*AIEML =*/true); - unsigned accWidth = - dyn_cast(accType).getElementType().getIntOrFloatBitWidth(); - - auto upsOp = rewriter.create(loc, accType, srcOp.getVector()); - - curValue = upsOp.getResult(); - unsigned laneSize = getVectorLaneSize(vType); - - VectorType vecType = createVectorType(2 * laneSize, scalarType); - aievec::AddElemOp curOp = nullptr; - - for (int id = shiftIndex; id > 0; id /= 2) { - arith::ConstantOp constOp = rewriter.create( - loc, rewriter.getI32IntegerAttr(id * accWidth / 8)); - auto shiftBytesOp = rewriter.create( - loc, accType, curValue, curValue, constOp, true); - curOp = rewriter.create(loc, accType, curValue, - shiftBytesOp.getResult()); - curValue = curOp.getResult(); - } - - auto srsOp = rewriter.create(loc, vType, curOp.getResult()); - SmallVector concatSources = {srsOp.getResult(), srsOp.getResult()}; - auto concatOp = - rewriter.create(loc, vecType, concatSources); - - arith::ConstantOp zeroConstOp = - rewriter.create(loc, rewriter.getI32IntegerAttr(0)); - rewriter.replaceOpWithNewOp(srcOp, scalarType, concatOp, - zeroConstOp.getResult()); -} - //===----------------------------------------------------------------------===// // Analyses //===----------------------------------------------------------------------===// @@ -932,61 +845,208 @@ struct LowerVectorAddOrSubOpToAIEVecAddElemOrSubElemOp unsigned resultElWidth = scalarType.getIntOrFloatBitWidth(); unsigned laneSize = getVectorLaneSize(resultType); + // Integer cases if (scalarType.isa()) { if (!laneSizeElWidthPairSet.count( std::make_pair(laneSize, resultElWidth))) return failure(); - if (laneSize == 32 && resultElWidth == 32) { - if (!lhsDefOp || !rhsDefOp) { + // If the ops are defined without extension ops and with supported data + // type, the arith::AddI or arith::SubI can be directly replaced with + // aievec::AddElem or aievec::SubElem. + if (!lhsDefOp && !rhsDefOp) { + if (laneSize * resultElWidth == 512) { + rewriter.replaceOpWithNewOp(srcOp, srcOp.getType(), lhs, + rhs); + return success(); + } else { return genAddElemAieML(rewriter, lhs, rhs, resultType, srcOp); } - auto lhsExt = dyn_cast(lhsDefOp); - auto rhsExt = dyn_cast(rhsDefOp); - if (!lhsExt || !rhsExt) { - return genAddElemAieML(rewriter, lhs, rhs, - resultType, srcOp); + } + + // If element width is 32, we need to consider sign extension cases + if (resultElWidth == 32) { + auto lhsExt = lhsDefOp ? dyn_cast(lhsDefOp) : nullptr; + auto rhsExt = rhsDefOp ? dyn_cast(rhsDefOp) : nullptr; + + if (!lhsExt && !rhsExt) { + if (laneSize * resultElWidth == 512) { + rewriter.replaceOpWithNewOp(srcOp, srcOp.getType(), lhs, + rhs); + return success(); + } else { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } } - auto lval = lhsExt->getOperand(0); - auto rval = rhsExt->getOperand(0); - VectorType lSrcType = cast(lval.getType()); - VectorType rSrcType = cast(rval.getType()); + if (lhsExt && rhsExt) { + auto lval = lhsExt->getOperand(0); + auto rval = rhsExt->getOperand(0); - unsigned lBitWidth = lSrcType.getElementType().getIntOrFloatBitWidth(); - unsigned rBitWidth = rSrcType.getElementType().getIntOrFloatBitWidth(); + VectorType lSrcType = cast(lval.getType()); + VectorType rSrcType = cast(rval.getType()); - if ((lBitWidth != 8 || rBitWidth != 8) && - (lBitWidth != 16 || rBitWidth != 16)) { - return genAddElemAieML(rewriter, lhs, rhs, - resultType, srcOp); + unsigned lBitWidth = + lSrcType.getElementType().getIntOrFloatBitWidth(); + unsigned rBitWidth = + rSrcType.getElementType().getIntOrFloatBitWidth(); + + if ((lBitWidth != 8 || rBitWidth != 8) && + (lBitWidth != 16 || rBitWidth != 16)) { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } + + Type accType = getVectorOpDestType(lSrcType, /*AIEML =*/true); + auto lUpsOp = + rewriter.create(srcOp.getLoc(), accType, lval); + auto rUpsOp = + rewriter.create(srcOp.getLoc(), accType, rval); + auto elemOp = rewriter.create( + srcOp.getLoc(), lUpsOp->getResult(0).getType(), + lUpsOp->getResult(0), rUpsOp->getResult(0)); + rewriter.replaceOpWithNewOp( + srcOp, srcOp.getType(), elemOp.getResult(), /*isResAcc*/ false); + return success(); } - Type accType = getVectorOpDestType(lSrcType, /*AIEML =*/true); - auto lUpsOp = - rewriter.create(srcOp.getLoc(), accType, lval); - auto rUpsOp = - rewriter.create(srcOp.getLoc(), accType, rval); - auto elemOp = rewriter.create( - srcOp.getLoc(), lUpsOp->getResult(0).getType(), - lUpsOp->getResult(0), rUpsOp->getResult(0)); - rewriter.replaceOpWithNewOp( - srcOp, srcOp.getType(), elemOp.getResult(), /*isResAcc*/ false); - return success(); + if (!lhsExt || !rhsExt) { + auto lval = lhsExt ? lhsExt->getOperand(0) : lhs; + auto rval = rhsExt ? rhsExt->getOperand(0) : rhs; + auto extVal = lhsExt ? lval : rval; + VectorType vType = cast(extVal.getType()); + unsigned bitWidth = vType.getElementType().getIntOrFloatBitWidth(); + + if (bitWidth != 8 && bitWidth != 16) { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } + + if (bitWidth * laneSize != 256) { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } + + Type accType = nullptr; + + if (bitWidth == 8) { + accType = getVectorOpDestType(vType, /*AIEML =*/true); + aievec::UPSOp upsOp = nullptr; + aievec::CastOp castOp = nullptr; + if (lhsExt) { + upsOp = + rewriter.create(srcOp.getLoc(), accType, lval); + castOp = rewriter.create(srcOp.getLoc(), + resultType, rval, + /*isResAcc*/ true); + } else { + upsOp = + rewriter.create(srcOp.getLoc(), accType, rval); + castOp = rewriter.create(srcOp.getLoc(), + resultType, lval, + /*isResAcc*/ true); + } + auto elemOp = rewriter.create( + srcOp.getLoc(), upsOp->getResult(0).getType(), + upsOp->getResult(0), castOp->getResult(0)); + + rewriter.replaceOpWithNewOp( + srcOp, srcOp.getType(), elemOp.getResult(), /*isResAcc*/ false); + return success(); + + } else if (bitWidth == 16) { + accType = getVectorOpDestType(resultType, /*AIEML =*/true); + auto lUpsOp = + rewriter.create(srcOp.getLoc(), accType, lval); + auto rUpsOp = + rewriter.create(srcOp.getLoc(), accType, rval); + + auto elemOp = rewriter.create( + srcOp.getLoc(), lUpsOp->getResult(0).getType(), + lUpsOp->getResult(0), rUpsOp->getResult(0)); + + rewriter.replaceOpWithNewOp(srcOp, srcOp.getType(), + elemOp.getResult()); + return success(); + } + } } else { rewriter.replaceOpWithNewOp(srcOp, srcOp.getType(), lhs, rhs); return success(); } - } // Float types + } + // Float types else { if (laneSize != 16) return failure(); - // v16float + // v16float or v16bf16 with extension op case if (resultElWidth == 32) { - return genAddElemAieML(rewriter, lhs, rhs, resultType, - srcOp); + if (!lhsDefOp && !rhsDefOp) { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } + + auto lhsExt = lhsDefOp ? dyn_cast(lhsDefOp) : nullptr; + auto rhsExt = rhsDefOp ? dyn_cast(rhsDefOp) : nullptr; + // v16float + if (!lhsExt && !rhsExt) { + return genAddElemAieML(rewriter, lhs, rhs, + resultType, srcOp); + } + + // v16bf16 with two extension ops + if (lhsExt && rhsExt) { + auto lval = lhsExt->getOperand(0); + auto rval = rhsExt->getOperand(0); + VectorType vType = cast(lval.getType()); + + Type accType = getVectorOpDestType(vType, /*AIEML =*/true); + auto lUpsOp = + rewriter.create(srcOp.getLoc(), accType, lval); + auto rUpsOp = + rewriter.create(srcOp.getLoc(), accType, rval); + auto elemOp = rewriter.create( + srcOp.getLoc(), lUpsOp->getResult(0).getType(), + lUpsOp->getResult(0), rUpsOp->getResult(0)); + rewriter.replaceOpWithNewOp(srcOp, srcOp.getType(), + elemOp.getResult()); + return success(); + } + + // v16bf16 with one extension op + if (!lhsExt || !rhsExt) { + auto lval = lhsExt ? lhsExt->getOperand(0) : lhs; + auto rval = rhsExt ? rhsExt->getOperand(0) : rhs; + auto extVal = lhsExt ? lval : rval; + VectorType vType = cast(extVal.getType()); + Type accType = getVectorOpDestType(vType, /*AIEML =*/true); + aievec::UPSOp upsOp = nullptr; + aievec::CastOp castOp = nullptr; + + if (lhsExt) { + upsOp = + rewriter.create(srcOp.getLoc(), accType, lval); + castOp = rewriter.create(srcOp.getLoc(), resultType, + rval, + /*isResAcc*/ true); + } else { + upsOp = + rewriter.create(srcOp.getLoc(), accType, rval); + castOp = rewriter.create(srcOp.getLoc(), resultType, + lval, + /*isResAcc*/ true); + } + auto elemOp = rewriter.create( + srcOp.getLoc(), upsOp->getResult(0).getType(), + upsOp->getResult(0), castOp->getResult(0)); + + rewriter.replaceOpWithNewOp( + srcOp, srcOp.getType(), elemOp.getResult(), /*isResAcc*/ false); + return success(); + } } // v16bfloat16 Type accType = getVectorOpDestType(resultType, /*AIEML =*/true); @@ -1160,7 +1220,7 @@ struct LowerVectorSelectOpToAIEVecSelOp } }; -struct LowerVectorReductionOp +struct LowerVectorReductionMinOp : public OpConversionPattern { using OpConversionPattern::OpConversionPattern; @@ -1168,81 +1228,215 @@ struct LowerVectorReductionOp matchAndRewrite(vector::ReductionOp srcOp, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto kind = srcOp.getKind(); - - if (kind != vector::CombiningKind::ADD && - kind != vector::CombiningKind::MINSI && + if (kind != vector::CombiningKind::MINSI && kind != vector::CombiningKind::MINUI && - kind != vector::CombiningKind::MINF && - kind != vector::CombiningKind::MAXSI && + kind != vector::CombiningKind::MINF) + return failure(); + + VectorType vType = cast(srcOp.getVector().getType()); + Type scalarType = vType.getElementType(); + unsigned elWidth = scalarType.getIntOrFloatBitWidth(); + unsigned laneSize = getVectorLaneSize(vType); + + if (laneSize * elWidth != 512) + return failure(); + + int shiftIndex = laneSize / 2; + generateAIEVecOpsForReductionOp(rewriter, srcOp, shiftIndex, + srcOp.getVector()); + return success(); + } +}; + +struct LowerVectorReductionMaxOp + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + + LogicalResult + matchAndRewrite(vector::ReductionOp srcOp, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + auto kind = srcOp.getKind(); + if (kind != vector::CombiningKind::MAXSI && kind != vector::CombiningKind::MAXUI && - kind != vector::CombiningKind::MAXF) { + kind != vector::CombiningKind::MAXF) return failure(); - } - VectorType vType = dyn_cast(srcOp.getVector().getType()); - if (!vType) + VectorType vType = cast(srcOp.getVector().getType()); + Type scalarType = vType.getElementType(); + unsigned elWidth = scalarType.getIntOrFloatBitWidth(); + unsigned laneSize = getVectorLaneSize(vType); + + if (laneSize * elWidth != 512) return failure(); - // A set recording the vector lane size and element width we are - // supporting for aie-ml. + int shiftIndex = laneSize / 2; + generateAIEVecOpsForReductionOp(rewriter, srcOp, shiftIndex, + srcOp.getVector()); + return success(); + } +}; + +struct LowerVectorReductionAddIntOp + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + + LogicalResult + matchAndRewrite(vector::ReductionOp srcOp, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + auto kind = srcOp.getKind(); + if (kind != vector::CombiningKind::ADD) + return failure(); + + VectorType vType = cast(srcOp.getVector().getType()); + Type scalarType = vType.getElementType(); + unsigned elWidth = scalarType.getIntOrFloatBitWidth(); + unsigned laneSize = getVectorLaneSize(vType); llvm::SmallSet, 16> laneSizeElWidthPairSet; laneSizeElWidthPairSet.insert({64, 8}); laneSizeElWidthPairSet.insert({32, 16}); + laneSizeElWidthPairSet.insert({32, 32}); laneSizeElWidthPairSet.insert({16, 32}); + if (!isa(scalarType) || + !laneSizeElWidthPairSet.count(std::make_pair(laneSize, elWidth))) + return failure(); + + int shiftIndex = laneSize / 2; + if (laneSize == 32 && elWidth == 32) { + Location loc = srcOp.getLoc(); + VectorType vecType = createVectorType(laneSize / 2, scalarType); + + auto lExtOp = + rewriter.create(loc, vecType, srcOp.getVector(), 0); + auto rExtOp = + rewriter.create(loc, vecType, srcOp.getVector(), 1); + auto addElemOp = rewriter.create( + loc, lExtOp.getResult().getType(), lExtOp.getResult(), + rExtOp.getResult()); + shiftIndex /= 2; + generateAIEVecOpsForReductionOp( + rewriter, srcOp, shiftIndex, addElemOp.getResult()); + } else { + generateAIEVecOpsForReductionOp( + rewriter, srcOp, shiftIndex, srcOp.getVector()); + } + return success(); + } +}; + +struct LowerVectorReductionAddFloatOp + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + + LogicalResult + matchAndRewrite(vector::ReductionOp srcOp, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + auto kind = srcOp.getKind(); + if (kind != vector::CombiningKind::ADD) + return failure(); + + VectorType vType = cast(srcOp.getVector().getType()); Type scalarType = vType.getElementType(); unsigned elWidth = scalarType.getIntOrFloatBitWidth(); unsigned laneSize = getVectorLaneSize(vType); - if (scalarType.isa() && - !laneSizeElWidthPairSet.count(std::make_pair(laneSize, elWidth))) - return failure(); - - if (scalarType.isa() && laneSize != 16 && laneSize != 32) + if (!isa(scalarType) || laneSize != 16 || elWidth != 32) return failure(); int shiftIndex = laneSize / 2; + assert(shiftIndex > 0 && (shiftIndex & (shiftIndex - 1)) == 0 && + "shiftIndex must be power of 2"); - // Reduction minimum - if (kind == vector::CombiningKind::MINSI || - kind == vector::CombiningKind::MINUI || - kind == vector::CombiningKind::MINF) { - generateAIEVecOpsForReductionOp(rewriter, srcOp, - shiftIndex); - return success(); + Location loc = srcOp.getLoc(); + Value curValue = srcOp.getVector(); + aievec::CastOp curOp = nullptr; + + for (int id = shiftIndex; id > 0; id /= 2) { + arith::ConstantOp constOp = rewriter.create( + loc, rewriter.getI32IntegerAttr(id * elWidth / 8)); + + auto shiftBytesOp = rewriter.create( + loc, vType, curValue, curValue, constOp.getResult()); + + auto lCastOp = rewriter.create(loc, vType, curValue, + /*isResAcc*/ true); + auto rCastOp = + rewriter.create(loc, vType, shiftBytesOp.getResult(), + /*isResAcc*/ true); + auto elemOp = rewriter.create( + loc, lCastOp.getResult().getType(), lCastOp.getResult(), + rCastOp.getResult()); + curOp = rewriter.create(loc, vType, elemOp.getResult(), + /*isResAcc*/ false); + + curValue = curOp.getResult(); } - // Reduction maximum - if (kind == vector::CombiningKind::MAXSI || - kind == vector::CombiningKind::MAXUI || - kind == vector::CombiningKind::MAXF) { - generateAIEVecOpsForReductionOp(rewriter, srcOp, - shiftIndex); - return success(); - } + arith::ConstantOp zeroConstOp = + rewriter.create(loc, rewriter.getI32IntegerAttr(0)); + rewriter.replaceOpWithNewOp(srcOp, scalarType, curOp, + zeroConstOp.getResult()); + return success(); + } +}; - // Reduction add for i32, i16 and i8 types - if (kind == vector::CombiningKind::ADD && isa(scalarType)) { - generateAIEVecOpsForReductionOp(rewriter, srcOp, - shiftIndex); - return success(); - } +struct LowerVectorReductionAddBfloat16Op + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; - // Reduction add for float and bfloat16 - if (kind == vector::CombiningKind::ADD && isa(scalarType)) { - // float type - if (elWidth == 32 && laneSize == 16) { - generateReductionOpForFloat(rewriter, srcOp, shiftIndex); - return success(); - } + LogicalResult + matchAndRewrite(vector::ReductionOp srcOp, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + auto kind = srcOp.getKind(); + if (kind != vector::CombiningKind::ADD) + return failure(); - // bfloat16 type - if (elWidth == 16 && laneSize == 16) { - generateReductionOpForBFloat16(rewriter, srcOp, shiftIndex); - return success(); - } + VectorType vType = cast(srcOp.getVector().getType()); + Type scalarType = vType.getElementType(); + unsigned elWidth = scalarType.getIntOrFloatBitWidth(); + unsigned laneSize = getVectorLaneSize(vType); + + if (!isa(scalarType) || laneSize != 16 || elWidth != 16) + return failure(); + + int shiftIndex = laneSize / 2; + assert(shiftIndex > 0 && (shiftIndex & (shiftIndex - 1)) == 0 && + "shiftIndex must be power of 2"); + + Value curValue = srcOp.getVector(); + Location loc = srcOp.getLoc(); + Type accType = getVectorOpDestType(vType, /*AIEML =*/true); + unsigned accWidth = + dyn_cast(accType).getElementType().getIntOrFloatBitWidth(); + + auto upsOp = + rewriter.create(loc, accType, srcOp.getVector()); + + curValue = upsOp.getResult(); + + VectorType vecType = createVectorType(2 * laneSize, scalarType); + aievec::AddElemOp curOp = nullptr; + + for (int id = shiftIndex; id > 0; id /= 2) { + arith::ConstantOp constOp = rewriter.create( + loc, rewriter.getI32IntegerAttr(id * accWidth / 8)); + auto shiftBytesOp = rewriter.create( + loc, accType, curValue, curValue, constOp, true); + curOp = rewriter.create(loc, accType, curValue, + shiftBytesOp.getResult()); + curValue = curOp.getResult(); } - return failure(); + + auto srsOp = rewriter.create(loc, vType, curOp.getResult()); + SmallVector concatSources = {srsOp.getResult(), srsOp.getResult()}; + auto concatOp = + rewriter.create(loc, vecType, concatSources); + + arith::ConstantOp zeroConstOp = + rewriter.create(loc, rewriter.getI32IntegerAttr(0)); + rewriter.replaceOpWithNewOp(srcOp, scalarType, concatOp, + zeroConstOp.getResult()); + return success(); } }; @@ -1304,7 +1498,9 @@ static void populateAIEVecV2ConversionPatterns(RewritePatternSet &patterns, LowerVectorMinSIOpToAIEVecMinOp, LowerVectorMaxSIOpToAIEVecMaxOp, LowerVectorMinFOpToAIEVecMinOp, LowerVectorMaxFOpToAIEVecMaxOp, LowerVectorCmpIOpToAIEVecCmpOp, LowerVectorCmpFOpToAIEVecCmpOp, - LowerVectorSelectOpToAIEVecSelOp, LowerVectorReductionOp, + LowerVectorSelectOpToAIEVecSelOp, LowerVectorReductionMinOp, + LowerVectorReductionMaxOp, LowerVectorReductionAddIntOp, + LowerVectorReductionAddFloatOp, LowerVectorReductionAddBfloat16Op, FoldVectorExtractAndBroadcastToAIEBroadcast, ConvertMulAddToAIEVecFMAElemOpPattern, ConvertMulIToAIEVecMulElemOpPattern, ConvertMulFToAIEVecMulElemOpPattern>( @@ -1574,6 +1770,7 @@ static void configureAIEVecV2Legalizations(ConversionTarget &target, llvm::SmallSet, 16> laneSizeElWidthPairSet; laneSizeElWidthPairSet.insert({64, 8}); laneSizeElWidthPairSet.insert({32, 16}); + laneSizeElWidthPairSet.insert({32, 32}); laneSizeElWidthPairSet.insert({16, 32}); Type scalarType = vType.getElementType(); diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp index d39a1b475e..0c6581d285 100644 --- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp +++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp @@ -2647,6 +2647,11 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { unsigned width = iType.getWidth(); if (llvm::all_of(dense, [](const APInt &val) { return val == 0; })) { if (AIEML) { + if (width * getVectorLaneSize(vType) == 1024) { + os << "concat(broadcast_zero_s" << width << "(), broadcast_zero_s" + << width << "())"; + return success(); + } os << "broadcast_zero_s"; os << width; } else { diff --git a/test/Conversion/VectorToAIEVec/test-arith-aie2.mlir b/test/Conversion/VectorToAIEVec/test-arith-aie2.mlir index 7d05180eff..122f5ce3ce 100644 --- a/test/Conversion/VectorToAIEVec/test-arith-aie2.mlir +++ b/test/Conversion/VectorToAIEVec/test-arith-aie2.mlir @@ -38,6 +38,20 @@ func.func @vecaddi_i16_i32(%arg0 : vector<32xi16>, %arg1 : vector<32xi16>) -> ve return %3 : vector<32xi32> } +// CHECK-LABEL: func @vecaddi_i16_i32_2( +// CHECK-SAME: %[[LHS:.*]]: vector<16xi16>, +// CHECK-SAME: %[[RHS:.*]]: vector<16xi32>) +func.func @vecaddi_i16_i32_2(%arg0 : vector<16xi16>, %arg1 : vector<16xi32>) -> vector<16xi32> { + // CHECK: %[[LUPS:.*]] = aievec.ups %[[LHS]] {shift = 0 : i8} : vector<16xi16>, vector<16xi64> + // CHECK: %[[RUPS:.*]] = aievec.ups %[[RHS]] {shift = 0 : i8} : vector<16xi32>, vector<16xi64> + // CHECK: %[[ADD:.*]] = aievec.add_elem %[[LUPS]], %[[RUPS]] : vector<16xi64> + // CHECK: %[[SRS:.*]] = aievec.srs %[[ADD]] {shift = 0 : i8} : vector<16xi64>, vector<16xi32> + %1 = arith.extsi %arg0 : vector<16xi16> to vector<16xi32> + %2 = arith.addi %1, %arg1 : vector<16xi32> + // CHECK: return %[[SRS]] : vector<16xi32> + return %2 : vector<16xi32> +} + // CHECK-LABEL: func @vecaddi_i8_i32( // CHECK-SAME: %[[LHS:.*]]: vector<32xi8>, // CHECK-SAME: %[[RHS:.*]]: vector<32xi8>) diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir new file mode 100644 index 0000000000..95772f35ca --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir @@ -0,0 +1,20 @@ +// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc +// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc +// RUN: mkdir -p data +// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// CHECK: TEST PASSED + +module { +func.func @dut(%arg0: memref<1024xbf16>, %arg1: memref) { + %cst = arith.constant 0.000000e+00 : f32 + %0 = affine.for %arg2 = 0 to 1024 iter_args(%arg3 = %cst) -> (f32) { + %1 = affine.load %arg0[%arg2] : memref<1024xbf16> + %2 = arith.extf %1 : bf16 to f32 + %3 = arith.addf %arg3, %2 : f32 + affine.yield %3 : f32 + } + affine.store %0, %arg1[] : memref + return + } +} diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/defines.h b/test/unit_tests/aievec_tests/bf16_float_add_reduce/defines.h new file mode 100644 index 0000000000..118779d291 --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/defines.h @@ -0,0 +1,3 @@ +#pragma once +constexpr unsigned const IN0_SIZE = 1024; +constexpr unsigned const OUT0_SIZE = 1; diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/dut.cc b/test/unit_tests/aievec_tests/bf16_float_add_reduce/dut.cc new file mode 100644 index 0000000000..96b5cfc0c9 --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/dut.cc @@ -0,0 +1,46 @@ +void dut(bfloat16 *restrict v1, float *restrict v2) { + int32_t v3 = 0; + int32_t v4 = 4; + int32_t v5 = 8; + int32_t v6 = 16; + int32_t v7 = 32; + v16float v8 = broadcast_zero_float(); + size_t v9 = 0; + size_t v10 = 1024; + size_t v11 = 16; + v16float v12; + v16float v13 = v8; + for (size_t v14 = v9; v14 < v10; v14 += v11) + chess_prepare_for_pipelining chess_loop_range(64, 64) { + v16bfloat16 v15 = *(v16bfloat16 *)(v1 + v14); + v16accfloat v16 = ups_to_v16accfloat(v15); + v16accfloat v17 = v16accfloat(v13); + v16accfloat v18 = add(v16, v17); + v16float v19 = v16float(v18); + v13 = v19; + } + v12 = v13; + v16float v20 = shift_bytes(v12, v12, v7); + v16accfloat v21 = v16accfloat(v12); + v16accfloat v22 = v16accfloat(v20); + v16accfloat v23 = add(v21, v22); + v16float v24 = v16float(v23); + v16float v25 = shift_bytes(v24, v24, v6); + v16accfloat v26 = v16accfloat(v24); + v16accfloat v27 = v16accfloat(v25); + v16accfloat v28 = add(v26, v27); + v16float v29 = v16float(v28); + v16float v30 = shift_bytes(v29, v29, v5); + v16accfloat v31 = v16accfloat(v29); + v16accfloat v32 = v16accfloat(v30); + v16accfloat v33 = add(v31, v32); + v16float v34 = v16float(v33); + v16float v35 = shift_bytes(v34, v34, v4); + v16accfloat v36 = v16accfloat(v34); + v16accfloat v37 = v16accfloat(v35); + v16accfloat v38 = add(v36, v37); + v16float v39 = v16float(v38); + float v40 = extract_elem(v39, v3); + *(float *)v2 = v40; + return; +} diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc new file mode 100644 index 0000000000..7043bd0628 --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc @@ -0,0 +1,57 @@ +#include "../common/testbench.h" +#include "defines.h" +#include +#include +#include +#include +void dut(bfloat16 *restrict in0, float *restrict out0); +void dut_ref(bfloat16 *in0, float *out0); + +alignas(32) bfloat16 g_in0[IN0_SIZE]; +alignas(32) float g_out0[OUT0_SIZE]; +alignas(32) float g_out0Ref[OUT0_SIZE]; + +int main(int argc, char *argv[]) { + // XXX Figure out how to use argv with xme_ca_udm_dbg -A + std::string dataDir(TO_STR(DATA_DIR)); + srand(10); + std::generate(g_in0, g_in0 + IN0_SIZE, + [&]() { return random_bfloat16(-3, 3, 2); }); + + writeData(g_in0, IN0_SIZE, dataDir + "/in0.txt"); + + chess_memory_fence(); + auto cyclesBegin = chess_cycle_count(); + dut(g_in0, g_out0); + auto cyclesEnd = chess_cycle_count(); + chess_memory_fence(); + + auto cycleCount = (int)(cyclesEnd - cyclesBegin); + reportCycleCount(cycleCount, dataDir + "/cycle_count.txt"); + + writeData(g_out0, OUT0_SIZE, dataDir + "/out0.txt"); + printf("g_out0 = %f\n", (float)(*g_out0)); + dut_ref(g_in0, g_out0Ref); + writeData(g_out0Ref, OUT0_SIZE, dataDir + "/out0_ref.txt"); + + bool ok = true; + ok &= checkData(g_out0, g_out0Ref, OUT0_SIZE, 0, 1e-3, 1e-3); + + if (ok) + printf("TEST PASSED\n"); + else + printf("TEST FAILED\n"); + + return ok ? 0 : 1; +} + +void dut_ref(bfloat16 *in0, float *out0) { + float res = 0.0f; + for (unsigned k = 0; k < IN0_SIZE; k += 16) { + for (unsigned i = 0; i < 16; ++i) { + res += in0[k + i]; + } + } + printf("sum = %f\n", res); + *out0 = res; +} diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir new file mode 100644 index 0000000000..3988504d4e --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// Copyright (C) 2023, Advanced Micro Devices, Inc. + +// REQUIRES: valid_xchess_license +// RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc +// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc +// RUN: mkdir -p data +// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// CHECK: TEST PASSED + +module { + func.func @dut(%arg0: memref<1024xbf16>, %arg1: memref<1024xbf16>, %arg2: memref<1024xf32>) { + affine.for %arg3 = 0 to 1024 step 16 { + %cst = arith.constant 0.000000e+00 : bf16 + %0 = vector.transfer_read %arg0[%arg3], %cst : memref<1024xbf16>, vector<16xbf16> + %1 = arith.extf %0 : vector<16xbf16> to vector<16xf32> + %cst_0 = arith.constant 0.000000e+00 : bf16 + %2 = vector.transfer_read %arg1[%arg3], %cst_0 : memref<1024xbf16>, vector<16xbf16> + %3 = arith.extf %2 : vector<16xbf16> to vector<16xf32> + %4 = arith.addf %1, %3 : vector<16xf32> + vector.transfer_write %4, %arg2[%arg3] : vector<16xf32>, memref<1024xf32> + } + return + } +} diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/defines.h b/test/unit_tests/aievec_tests/bf16xf32_add_elem/defines.h new file mode 100644 index 0000000000..b0366ff425 --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/defines.h @@ -0,0 +1,4 @@ +#pragma once +constexpr unsigned const IN0_SIZE = 1024; +constexpr unsigned const IN1_SIZE = 1024; +constexpr unsigned const OUT0_SIZE = 1024; diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/dut.cc b/test/unit_tests/aievec_tests/bf16xf32_add_elem/dut.cc new file mode 100644 index 0000000000..5839f7d50a --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/dut.cc @@ -0,0 +1,16 @@ +void dut(bfloat16 *restrict v1, bfloat16 *restrict v2, float *restrict v3) { + size_t v4 = 0; + size_t v5 = 1024; + size_t v6 = 16; + for (size_t v7 = v4; v7 < v5; v7 += v6) + chess_prepare_for_pipelining chess_loop_range(64, 64) { + v16bfloat16 v8 = *(v16bfloat16 *)(v1 + v7); + v16bfloat16 v9 = *(v16bfloat16 *)(v2 + v7); + v16accfloat v10 = ups_to_v16accfloat(v8); + v16accfloat v11 = ups_to_v16accfloat(v9); + v16accfloat v12 = add(v10, v11); + v16float v13 = v16float(v12); + *(v16float *)(v3 + v7) = v13; + } + return; +} diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/testbench.cc b/test/unit_tests/aievec_tests/bf16xf32_add_elem/testbench.cc new file mode 100644 index 0000000000..4150e7b007 --- /dev/null +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/testbench.cc @@ -0,0 +1,55 @@ +#include "../common/testbench.h" +#include "defines.h" +#include +#include +#include +#include +void dut(bfloat16 *restrict in0, bfloat16 *restrict in1, float *restrict out0); +void dut_ref(bfloat16 *in0, bfloat16 *in1, float *out0); + +alignas(32) bfloat16 g_in0[IN0_SIZE]; +alignas(32) bfloat16 g_in1[IN1_SIZE]; +alignas(32) float g_out0[OUT0_SIZE]; +alignas(32) float g_out0Ref[OUT0_SIZE]; + +int main(int argc, char *argv[]) { + std::string dataDir(TO_STR(DATA_DIR)); + srand(10); + std::generate(g_in0, g_in0 + IN0_SIZE, + [&]() { return random_bfloat16(-10, 10, 2); }); + std::generate(g_in1, g_in1 + IN1_SIZE, + [&]() { return random_bfloat16(-10, 10, 2); }); + + writeData(g_in0, IN0_SIZE, dataDir + "/in0.txt"); + writeData(g_in1, IN1_SIZE, dataDir + "/in1.txt"); + + chess_memory_fence(); + auto cyclesBegin = chess_cycle_count(); + dut(g_in0, g_in1, g_out0); + auto cyclesEnd = chess_cycle_count(); + chess_memory_fence(); + + auto cycleCount = (int)(cyclesEnd - cyclesBegin); + reportCycleCount(cycleCount, dataDir + "/cycle_count.txt"); + + writeData(g_out0, OUT0_SIZE, dataDir + "/out0.txt"); + + dut_ref(g_in0, g_in1, g_out0Ref); + writeData(g_out0Ref, OUT0_SIZE, dataDir + "/out0_ref.txt"); + + bool ok = true; + ok &= checkData(g_out0, g_out0Ref, OUT0_SIZE, 1); + + if (ok) + printf("TEST PASSED\n"); + else + printf("TEST FAILED\n"); + + return ok ? 0 : 1; +} + +void dut_ref(bfloat16 *in0, bfloat16 *in1, float *out0) { + for (unsigned k = 0; k < OUT0_SIZE; k += 1) { + out0[k] = (float)in0[k] + (float)in1[k]; + } +} diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/defines.h b/test/unit_tests/aievec_tests/i16_i32_add_reduce/defines.h new file mode 100644 index 0000000000..118779d291 --- /dev/null +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/defines.h @@ -0,0 +1,3 @@ +#pragma once +constexpr unsigned const IN0_SIZE = 1024; +constexpr unsigned const OUT0_SIZE = 1; diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/dut.cc b/test/unit_tests/aievec_tests/i16_i32_add_reduce/dut.cc new file mode 100644 index 0000000000..d6c62cc818 --- /dev/null +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/dut.cc @@ -0,0 +1,34 @@ +void dut(int16_t *restrict v1, int32_t *restrict v2) { + int32_t v3 = 0; + int32_t v4 = 4; + int32_t v5 = 8; + int32_t v6 = 16; + int32_t v7 = 32; + v16int32 v8 = broadcast_zero_s32(); + size_t v9 = 0; + size_t v10 = 1024; + size_t v11 = 16; + v16int32 v12; + v16int32 v13 = v8; + for (size_t v14 = v9; v14 < v10; v14 += v11) + chess_prepare_for_pipelining chess_loop_range(64, 64) { + v16int16 v15 = *(v16int16 *)(v1 + v14); + v16acc64 v16 = ups_to_v16acc64(v13, 0); + v16acc64 v17 = ups_to_v16acc64(v15, 0); + v16acc64 v18 = add(v16, v17); + v16int32 v19 = srs_to_v16int32(v18, 0); + v13 = v19; + } + v12 = v13; + v16int32 v20 = shift_bytes(v12, v12, v7); + v16int32 v21 = add(v12, v20); + v16int32 v22 = shift_bytes(v21, v21, v6); + v16int32 v23 = add(v21, v22); + v16int32 v24 = shift_bytes(v23, v23, v5); + v16int32 v25 = add(v23, v24); + v16int32 v26 = shift_bytes(v25, v25, v4); + v16int32 v27 = add(v25, v26); + int32_t v28 = extract_elem(v27, v3); + *(int32_t *)v2 = v28; + return; +} diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir new file mode 100644 index 0000000000..96f5d93515 --- /dev/null +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir @@ -0,0 +1,20 @@ +// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc +// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc +// RUN: mkdir -p data +// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// CHECK: TEST PASSED + +module { +func.func @dut(%arg0: memref<1024xi16>, %arg1: memref) { + %c0_i32 = arith.constant 0 : i32 + %0 = affine.for %arg2 = 0 to 1024 iter_args(%arg3 = %c0_i32) -> (i32) { + %1 = affine.load %arg0[%arg2] : memref<1024xi16> + %2 = arith.extsi %1 : i16 to i32 + %3 = arith.addi %arg3, %2 : i32 + affine.yield %3 : i32 + } + affine.store %0, %arg1[] : memref + return + } +} diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc new file mode 100644 index 0000000000..7db30836b7 --- /dev/null +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc @@ -0,0 +1,55 @@ +#include "../common/testbench.h" +#include "defines.h" +#include +#include +#include +#include +void dut(int16_t *restrict in0, int32_t *restrict out0); +void dut_ref(int16_t *in0, int32_t *out0); + +alignas(32) int16_t g_in0[IN0_SIZE]; +alignas(32) int32_t g_out0[OUT0_SIZE]; +alignas(32) int32_t g_out0Ref[OUT0_SIZE]; + +int main(int argc, char *argv[]) { + // XXX Figure out how to use argv with xme_ca_udm_dbg -A + std::string dataDir(TO_STR(DATA_DIR)); + srand(10); + std::generate(g_in0, g_in0 + IN0_SIZE, + [&]() { return random_integer(); }); + + writeData(g_in0, IN0_SIZE, dataDir + "/in0.txt"); + + chess_memory_fence(); + auto cyclesBegin = chess_cycle_count(); + dut(g_in0, g_out0); + auto cyclesEnd = chess_cycle_count(); + chess_memory_fence(); + + auto cycleCount = (int)(cyclesEnd - cyclesBegin); + reportCycleCount(cycleCount, dataDir + "/cycle_count.txt"); + + writeData(g_out0, OUT0_SIZE, dataDir + "/out0.txt"); + + dut_ref(g_in0, g_out0Ref); + writeData(g_out0Ref, OUT0_SIZE, dataDir + "/out0_ref.txt"); + + bool ok = true; + ok &= checkData(g_out0, g_out0Ref, OUT0_SIZE, 1); + + if (ok) + printf("TEST PASSED\n"); + else + printf("TEST FAILED\n"); + + return ok ? 0 : 1; +} + +// in0 and out0 are in C4 layout. +void dut_ref(int16_t *in0, int32_t *out0) { + int32_t sum = 0; + for (unsigned k = 0; k < IN0_SIZE; k += 1) { + sum += in0[k]; + } + *out0 = sum; +} diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/defines.h b/test/unit_tests/aievec_tests/i8_i32_add_reduce/defines.h new file mode 100644 index 0000000000..118779d291 --- /dev/null +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/defines.h @@ -0,0 +1,3 @@ +#pragma once +constexpr unsigned const IN0_SIZE = 1024; +constexpr unsigned const OUT0_SIZE = 1; diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/dut.cc b/test/unit_tests/aievec_tests/i8_i32_add_reduce/dut.cc new file mode 100644 index 0000000000..d59b084ba5 --- /dev/null +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/dut.cc @@ -0,0 +1,37 @@ +void dut(int8_t *restrict v1, int32_t *restrict v2) { + int32_t v3 = 0; + int32_t v4 = 4; + int32_t v5 = 8; + int32_t v6 = 16; + int32_t v7 = 32; + v32int32 v8 = concat(broadcast_zero_s32(), broadcast_zero_s32()); + size_t v9 = 0; + size_t v10 = 1024; + size_t v11 = 32; + v32int32 v12; + v32int32 v13 = v8; + for (size_t v14 = v9; v14 < v10; v14 += v11) + chess_prepare_for_pipelining chess_loop_range(32, 32) { + v32int8 v15 = *(v32int8 *)(v1 + v14); + v32acc32 v16 = ups_to_v32acc32(v15, 0); + v32acc32 v17 = v32acc32(v13); + v32acc32 v18 = add(v16, v17); + v32int32 v19 = v32int32(v18); + v13 = v19; + } + v12 = v13; + v16int32 v20 = extract_v16int32(v12, 0); + v16int32 v21 = extract_v16int32(v12, 1); + v16int32 v22 = add(v20, v21); + v16int32 v23 = shift_bytes(v22, v22, v7); + v16int32 v24 = add(v22, v23); + v16int32 v25 = shift_bytes(v24, v24, v6); + v16int32 v26 = add(v24, v25); + v16int32 v27 = shift_bytes(v26, v26, v5); + v16int32 v28 = add(v26, v27); + v16int32 v29 = shift_bytes(v28, v28, v4); + v16int32 v30 = add(v28, v29); + int32_t v31 = extract_elem(v30, v3); + *(int32_t *)v2 = v31; + return; +} diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir new file mode 100644 index 0000000000..d8365417c9 --- /dev/null +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir @@ -0,0 +1,20 @@ +// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc +// RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc +// RUN: mkdir -p data +// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// CHECK: TEST PASSED + +module { +func.func @dut(%arg0: memref<1024xi8>, %arg1: memref) { + %c0_i32 = arith.constant 0 : i32 + %0 = affine.for %arg2 = 0 to 1024 iter_args(%arg3 = %c0_i32) -> (i32) { + %1 = affine.load %arg0[%arg2] : memref<1024xi8> + %2 = arith.extsi %1 : i8 to i32 + %3 = arith.addi %arg3, %2 : i32 + affine.yield %3 : i32 + } + affine.store %0, %arg1[] : memref + return + } +} diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i8_i32_add_reduce/testbench.cc new file mode 100644 index 0000000000..29d39da663 --- /dev/null +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/testbench.cc @@ -0,0 +1,55 @@ +#include "../common/testbench.h" +#include "defines.h" +#include +#include +#include +#include +void dut(int8_t *restrict in0, int32_t *restrict out0); +void dut_ref(int8_t *in0, int32_t *out0); + +alignas(32) int8_t g_in0[IN0_SIZE]; +alignas(32) int32_t g_out0[OUT0_SIZE]; +alignas(32) int32_t g_out0Ref[OUT0_SIZE]; + +int main(int argc, char *argv[]) { + // XXX Figure out how to use argv with xme_ca_udm_dbg -A + std::string dataDir(TO_STR(DATA_DIR)); + srand(10); + std::generate(g_in0, g_in0 + IN0_SIZE, + [&]() { return random_integer(); }); + + writeData(g_in0, IN0_SIZE, dataDir + "/in0.txt"); + + chess_memory_fence(); + auto cyclesBegin = chess_cycle_count(); + dut(g_in0, g_out0); + auto cyclesEnd = chess_cycle_count(); + chess_memory_fence(); + + auto cycleCount = (int)(cyclesEnd - cyclesBegin); + reportCycleCount(cycleCount, dataDir + "/cycle_count.txt"); + + writeData(g_out0, OUT0_SIZE, dataDir + "/out0.txt"); + + dut_ref(g_in0, g_out0Ref); + writeData(g_out0Ref, OUT0_SIZE, dataDir + "/out0_ref.txt"); + + bool ok = true; + ok &= checkData(g_out0, g_out0Ref, OUT0_SIZE, 1); + + if (ok) + printf("TEST PASSED\n"); + else + printf("TEST FAILED\n"); + + return ok ? 0 : 1; +} + +// in0 and out0 are in C4 layout. +void dut_ref(int8_t *in0, int32_t *out0) { + int32_t sum = 0; + for (unsigned k = 0; k < IN0_SIZE; k += 1) { + sum += in0[k]; + } + *out0 = sum; +} From 4491f7c6ff646f24fb1237542b61408b7fc597f2 Mon Sep 17 00:00:00 2001 From: Lina Yu Date: Mon, 17 Jul 2023 10:32:28 -0700 Subject: [PATCH 2/3] Replace xme_ca_udm_dbg with xca_udm_dbg --aiearch aie-ml in the unit_tests/aievec_tests --- .../aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc | 2 +- .../bf16_float_add_reduce/bf16_float_add_reduce.mlir | 4 ++-- .../aievec_tests/bf16_float_add_reduce/testbench.cc | 2 +- .../aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc | 2 +- .../aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc | 2 +- .../aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir | 4 ++-- .../aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir | 4 ++-- .../aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir | 4 ++-- .../aievec_tests/float_add_reduce/float_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_add_reduce/testbench.cc | 2 +- .../aievec_tests/float_max_reduce/float_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_max_reduce/testbench.cc | 2 +- .../aievec_tests/float_min_reduce/float_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/float_min_reduce/testbench.cc | 2 +- .../floatxfloat_add_elem/floatxfloat_add_elem.mlir | 4 ++-- .../floatxfloat_max_elem/floatxfloat_max_elem.mlir | 4 ++-- .../floatxfloat_min_elem/floatxfloat_min_elem.mlir | 4 ++-- .../aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir | 4 ++-- .../floatxfloat_sub_elem/floatxfloat_sub_elem.mlir | 4 ++-- .../aievec_tests/i16_add_reduce/i16_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc | 2 +- .../aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc | 2 +- .../aievec_tests/i16_max_reduce/i16_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc | 2 +- .../aievec_tests/i16_min_reduce/i16_min_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc | 2 +- .../aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc | 2 +- .../aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir | 4 ++-- .../conv2d_i16_after_polygeist.mlir | 2 +- .../conv2d_i16_after_polygeist_2.mlir | 2 +- .../aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir | 2 +- .../gemm64_int16_unroll32_after_polygeist.mlir | 2 +- .../aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir | 4 ++-- .../i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir | 4 ++-- .../conv2d_uij_i16_noinit.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i32_add_reduce/i32_add_reduce.mlir | 4 ++-- .../aievec_tests/i32_max_reduce/i32_max_reduce.mlir | 4 ++-- .../aievec_tests/i32_min_reduce/i32_min_reduce.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir | 2 +- .../aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir | 4 ++-- .../i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir | 4 ++-- .../aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir | 4 ++-- .../conv2d_i8_after_polygeist.mlir | 2 +- .../aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir | 4 ++-- .../conv2d_uij_i8_noinit.mlir | 4 ++-- .../conv2d_uij_i8_init.mlir | 2 +- .../conv2d_uij_i8_noinit_unsorted.mlir | 2 +- .../aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir | 4 ++-- 81 files changed, 142 insertions(+), 142 deletions(-) diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir index 5b0f8a02a7..180b63dc87 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc index 47175e7173..0775761d7d 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir index 95772f35ca..ab79b2065d 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc index 7043bd0628..e16a2439b2 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir index e0b8e04d1a..857aad25f8 100644 --- a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc index 830544efb2..276c1c4b6b 100644 --- a/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_max_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir index fb81df855f..db20666b9b 100644 --- a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc index 186152df54..3e0b003b2f 100644 --- a/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/bf16_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) bfloat16 g_out0[OUT0_SIZE]; alignas(32) bfloat16 g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir index edad465910..16bd67c061 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir index e921edacc9..5f38c2ff3d 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir index 98037e4d91..f38728b0b3 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir index a3ad790b66..ddecaaab02 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir index 1468307ecb..8cc047478f 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir index e7564b41d4..efaa25a20d 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir index d430a202dc..0096c761e5 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir index 3988504d4e..1e8b687953 100644 --- a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir index c1f87ee5c7..80de5660f5 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc index ab78bae2e9..b3ef49c84b 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir index 3ebc3294cc..b5b6d18443 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc index f4f81768bf..8a905d5ce1 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_max_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir index 2156789be2..f3cbfc6d40 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc index 74fa8efedd..dfe0e65ab0 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/float_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) float g_out0[OUT0_SIZE]; alignas(32) float g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir index d8c302f0c8..f44017dbfb 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir index e1ebe7a467..ca56f1e3dd 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir index 59e7662bac..2b2b26eb96 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir index fb896820b8..9d3454eaf1 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir index 816c2fba32..871bc5573a 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir index 86916c04d1..1a4ad677d7 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc index 34f5fe20c6..b85dd08b3c 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir index 96f5d93515..318588c6ca 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc index 7db30836b7..bb58b250da 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/testbench.cc @@ -12,7 +12,7 @@ alignas(32) int32_t g_out0[OUT0_SIZE]; alignas(32) int32_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir index 5102486bb9..8a975cce20 100644 --- a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc index d39407348a..9db86eacfe 100644 --- a/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_max_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir index b76ca9aecd..ddfe183a42 100644 --- a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc b/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc index 73cc78c3a9..0d8314492c 100644 --- a/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc +++ b/test/unit_tests/aievec_tests/i16_min_reduce/testbench.cc @@ -14,7 +14,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir index 5cf5c86949..03eb7f5553 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc b/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc index 544ab504a9..7e637aa830 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem/testbench.cc @@ -13,7 +13,7 @@ alignas(32) int16_t g_out0[OUT0_SIZE]; alignas(32) int16_t g_out0Ref[OUT0_SIZE]; int main(int argc, char *argv[]) { - // XXX Figure out how to use argv with xme_ca_udm_dbg -A + // XXX Figure out how to use argv with xca_udm_dbg --aiearch aie-ml -A std::string dataDir(TO_STR(DATA_DIR)); srand(10); std::generate(g_in0, g_in0 + IN0_SIZE, diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir index a4267fb920..d9f4795791 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir index 2d1e54084b..3ef9f9184d 100644 --- a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml/conv2d_i16_after_polygeist.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir index fc96a6ba72..e615422795 100644 --- a/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_conv2d_1x3_after_polygeist_aie-ml_2/conv2d_i16_after_polygeist_2.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir b/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir index 887e2d4b43..531975f52e 100644 --- a/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_gemm/gemm64_int16_unroll32.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc //RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module { func.func @matmul(%arg0: memref<64x64xi16>, %arg1: memref<64x64xi16>, %arg2: memref<64x64xi16>) { diff --git a/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir b/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir index b310016efa..a062604807 100644 --- a/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_gemm_after_polygeist/gemm64_int16_unroll32_after_polygeist.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // XFAIL: * diff --git a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir index 1e5696eb61..8667cf4e87 100644 --- a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir index 44c3a95c1a..0dde88fc76 100644 --- a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir index f0ea1d0cc7..b1acc2c195 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir index e153875d54..973dda05af 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir index 7fe37b27eb..76ea06cbde 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir index b533024b02..3779d12dbb 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir b/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir index bc12daf631..62bf84570a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_static_sized_memref_aie-ml/conv2d_uij_i16_noinit.mlir @@ -1,11 +1,11 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize="shift=10 zero-offset=4" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml shift=10" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi16>, %B: memref<9xi16>, %C: memref<16x256xi16>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir index 9e706f74fe..bebc97c659 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir index f512f9a80d..0235cd0acf 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir index 780465a791..f81786df39 100644 --- a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir index caa1a31be2..ea3cfd232b 100644 --- a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir index 7d72729dec..4b8bd4be78 100644 --- a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir index 9e121ff8ff..51368a5f13 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir index 6f1efb9836..79c0631860 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir b/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir index e03d11ac9d..df5ad5da72 100644 --- a/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_gemm/gemm64_int_unroll16.mlir @@ -2,7 +2,7 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" -aieml=true --aie-vectorize | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc //RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/testbench.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module { func.func @matmul(%arg0: memref<64x64xi32>, %arg1: memref<64x64xi32>, %arg2: memref<64x64xi32>) { affine.for %arg3 = 0 to 64 { diff --git a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir index 8b2c999f31..91873380c9 100644 --- a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir index d4ec7d58c8..17c64cbe6e 100644 --- a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir index 4b54dedf19..ba7fd09656 100644 --- a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir index 72e3b6876d..f6c47dffd8 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir index 49c4c92396..f7b4f1704a 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir index fb3c2966c6..91d82f3102 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir index e4a507be5f..12a487b8f5 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir index 4e6acd2110..aa4fb27011 100644 --- a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir index d8365417c9..5a7e22fbaa 100644 --- a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir index e14b894f9a..2c1b07b6d8 100644 --- a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir index 83afad04dc..0ef7961e44 100644 --- a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir index 701a157d61..2fa2b9e66d 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir index 3b3bd21fb8..7e752e2b71 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir b/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir index ea5defc593..f493b6b5bc 100644 --- a/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_conv2d_1x3_after_polygeist_aie-ml/conv2d_i8_after_polygeist.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize="shift=0 dup-factor=2" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>, #dlti.dl_entry : vector<2xi32>>>, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "polygeist.target-cpu" = "x86-64", "polygeist.target-features" = "+cx8,+fxsr,+mmx,+sse,+sse2,+x87", "polygeist.tune-cpu" = "generic"} { func.func @conv2d(%arg0: memref, %arg1: memref, %arg2: memref) attributes {llvm.linkage = #llvm.linkage} { diff --git a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir index 3f95c33d06..b8f8a6b680 100644 --- a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir index 9818c36c1d..4fa05c21b9 100644 --- a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir index 867f7d165c..4e1a456bf7 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir index 36e51ab4ec..0018d38ae3 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir index 1887b89a7e..17903ec943 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir index f5d29d2114..fca8858ed6 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_aie-ml/conv2d_uij_i8_noinit.mlir @@ -1,11 +1,11 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" -aieml=true --aie-vectorize="shift=0 dup-factor=2" | aie-translate -aieml=true --aievec-to-cpp -o gen_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir index bdd2e230df..9fc88a5416 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_init_aie-ml/conv2d_uij_i8_init.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir index b5de2e6735..3a90c1c8dd 100644 --- a/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_static_sized_memref_unsorted_aie-ml/conv2d_uij_i8_noinit_unsorted.mlir @@ -4,7 +4,7 @@ // REQUIRES: valid_xchess_license // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o convert_aie-ml.cc // RUN: xchesscc -f -g +s -p me -P %aietools/data/aie_ml/lib/ +w work +o work -I%S -I. %S/i8xi8.cc %S/convert_kernel.cc -// RUN: cp -r %S/data . && xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" +// RUN: cp -r %S/data . && xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" func.func @conv2d (%A: memref<18x288xi8>, %B: memref<48xi8>, %C: memref<16x256xi8>) { affine.for %arg3 = 0 to 16 { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir index 018f26c612..f5fdbc5688 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir index 9915dd12a2..42d946b15f 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xme_ca_udm_dbg -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xme_ca_udm_dbg.stdout -// RUN: FileCheck --input-file=./xme_ca_udm_dbg.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s // CHECK: TEST PASSED module { From fa20a147ce031898cf2c4b0e2c38e6ac67555ceb Mon Sep 17 00:00:00 2001 From: Lina Yu Date: Mon, 17 Jul 2023 10:56:20 -0700 Subject: [PATCH 3/3] clean up --- .../aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir | 4 ++-- .../bf16_float_add_reduce/bf16_float_add_reduce.mlir | 4 ++-- .../aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir | 4 ++-- .../aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir | 4 ++-- .../aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir | 4 ++-- .../aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir | 4 ++-- .../aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir | 4 ++-- .../aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir | 4 ++-- .../aievec_tests/float_add_reduce/float_add_reduce.mlir | 4 ++-- .../aievec_tests/float_max_reduce/float_max_reduce.mlir | 4 ++-- .../aievec_tests/float_min_reduce/float_min_reduce.mlir | 4 ++-- .../floatxfloat_add_elem/floatxfloat_add_elem.mlir | 4 ++-- .../floatxfloat_max_elem/floatxfloat_max_elem.mlir | 4 ++-- .../floatxfloat_min_elem/floatxfloat_min_elem.mlir | 4 ++-- .../aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir | 4 ++-- .../floatxfloat_sub_elem/floatxfloat_sub_elem.mlir | 4 ++-- .../aievec_tests/i16_add_reduce/i16_add_reduce.mlir | 4 ++-- .../aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir | 4 ++-- .../aievec_tests/i16_max_reduce/i16_max_reduce.mlir | 4 ++-- .../aievec_tests/i16_min_reduce/i16_min_reduce.mlir | 4 ++-- .../aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir | 4 ++-- .../i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir | 4 ++-- .../aievec_tests/i32_add_reduce/i32_add_reduce.mlir | 4 ++-- .../aievec_tests/i32_max_reduce/i32_max_reduce.mlir | 4 ++-- .../aievec_tests/i32_min_reduce/i32_min_reduce.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir | 4 ++-- .../i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir | 4 ++-- .../aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir | 4 ++-- .../aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir | 4 ++-- test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir | 4 ++-- test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir | 4 ++-- .../aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir | 4 ++-- .../aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir | 4 ++-- 59 files changed, 118 insertions(+), 118 deletions(-) diff --git a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir index 180b63dc87..fe0d2df12b 100644 --- a/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_add_reduce/bf16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir index ab79b2065d..6b83675545 100644 --- a/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_float_add_reduce/bf16_float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir index 857aad25f8..74e6780d0b 100644 --- a/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_max_reduce/bf16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir index db20666b9b..c873695c5c 100644 --- a/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/bf16_min_reduce/bf16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir index 16bd67c061..a720089936 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir index 5f38c2ff3d..993155b2a3 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_max_elem/bf16xbf16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir index f38728b0b3..bf963fea87 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_min_elem/bf16xbf16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir index ddecaaab02..9ac3e48293 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir index 8cc047478f..80dd73dd83 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir index efaa25a20d..65822aeb12 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sel/bf16xbf16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir index 0096c761e5..b2d8d842a1 100644 --- a/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir index 1e8b687953..76fcd21838 100644 --- a/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/bf16xf32_add_elem/bf16xfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir index 80de5660f5..bce09ebd64 100644 --- a/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_add_reduce/float_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir index b5b6d18443..3c16b931bd 100644 --- a/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_max_reduce/float_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir index f3cbfc6d40..c68a7abccb 100644 --- a/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/float_min_reduce/float_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir index f44017dbfb..d60ef74de2 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_add_elem/floatxfloat_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir index ca56f1e3dd..d8bc52873d 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_max_elem/floatxfloat_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir index 2b2b26eb96..e910b2bc42 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_min_elem/floatxfloat_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir index 9d3454eaf1..ea2e8ada00 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sel/floatxfloat_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir index 871bc5573a..e337fe3399 100644 --- a/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir index 1a4ad677d7..1903750935 100644 --- a/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_add_reduce/i16_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir index 318588c6ca..18f5bb444c 100644 --- a/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_i32_add_reduce/i16_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir index 8a975cce20..ae3b3810c0 100644 --- a/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_max_reduce/i16_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir index ddfe183a42..ca6c1c1c36 100644 --- a/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i16_min_reduce/i16_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir index 03eb7f5553..79db87115c 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir index d9f4795791..6ff870f41d 100644 --- a/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_add_elem_2/i16xi16_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir index 8667cf4e87..14b7e1c97a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_max_elem/i16xi16_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir index 0dde88fc76..8a1c04ac6a 100644 --- a/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_min_elem/i16xi16_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir index b1acc2c195..aadc2d3799 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir index 973dda05af..1aea071f05 100644 --- a/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir index 76ea06cbde..08ecee86cc 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel/i16xi16_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir index 3779d12dbb..172d569531 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sel_unsigned_cmp/i16xi16_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir index bebc97c659..4d8b435576 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir index 0235cd0acf..4308e529d8 100644 --- a/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i16xi16_sub_elem_2/i16xi16_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir index f81786df39..86d5f97cbb 100644 --- a/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_add_reduce/i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir index ea3cfd232b..8a43822cdb 100644 --- a/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_max_reduce/i32_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir index 4b8bd4be78..b5d0c5a74d 100644 --- a/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i32_min_reduce/i32_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir index 51368a5f13..b7753c1254 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir index 79c0631860..74f0da4d66 100644 --- a/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_add_elem_2/i32xi32_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir index 91873380c9..8bb4cf0fac 100644 --- a/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_max_elem/i32xi32_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir index 17c64cbe6e..93647d1ff3 100644 --- a/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_min_elem/i32xi32_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir index ba7fd09656..ad66d1111e 100644 --- a/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir index f6c47dffd8..427cbd4d92 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel/i32xi32_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir index f7b4f1704a..7a586595c4 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sel_unsigned_cmp/i32xi32_sel_unsigned_cmp.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir index 91d82f3102..24626ec4db 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir index 12a487b8f5..d57a4dfaf0 100644 --- a/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i32xi32_sub_elem_2/i32xi32_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir index aa4fb27011..316004af15 100644 --- a/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_add_reduce/i8_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir index 5a7e22fbaa..8736f5c161 100644 --- a/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_i32_add_reduce/i8_i32_add_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32 test-fastest-varying=0 vectorize-reductions=true" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir index 2c1b07b6d8..d2b2d12dce 100644 --- a/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_max_reduce/i8_max_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir index 0ef7961e44..5c2d636f19 100644 --- a/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir +++ b/test/unit_tests/aievec_tests/i8_min_reduce/i8_min_reduce.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir index 2fa2b9e66d..a907d0e2d7 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir index 7e752e2b71..d41d3efe90 100644 --- a/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_add_elem_2/i8xi8_add_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir index b8f8a6b680..d5c497d854 100644 --- a/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_max_elem/i8xi8_max_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir index 4fa05c21b9..dc86667bad 100644 --- a/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_min_elem/i8xi8_min_elem.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir index 4e1a456bf7..255bd17950 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir index 0018d38ae3..4bf7202271 100644 --- a/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=32" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir index 17903ec943..1f28f7c775 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sel/i8xi8_sel.mlir @@ -1,8 +1,8 @@ // RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=64" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir index f5fdbc5688..d267924eb0 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module { diff --git a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir index 42d946b15f..31e56eeae8 100644 --- a/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir +++ b/test/unit_tests/aievec_tests/i8xi8_sub_elem_2/i8xi8_sub_elem.mlir @@ -5,8 +5,8 @@ // RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc // RUN: xchesscc_wrapper aie2 -f -g +s +w work +o work -I%S -I. %S/testbench.cc dut.cc // RUN: mkdir -p data -// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg --aiearch aie-ml.stdout -// RUN: FileCheck --input-file=./xca_udm_dbg --aiearch aie-ml.stdout %s +// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout +// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s // CHECK: TEST PASSED module {