Is the CPU in PicoRV32 Implemented as a 5-Stage Pipeline?

[alihkousha]

Hello YosysHQ Team,

First, thank you for your incredible work on the PicoRV32 project. I’ve been exploring the core and its documentation and have a question about its CPU design.

Could you confirm whether the CPU in PicoRV32 is implemented as a 5-stage pipeline? If not, could you provide some insights into the pipeline structure used? Additionally, it would be great if you could point me to any related documentation or sections in the source code that elaborate on this aspect.

Thank you for your time and support. Looking forward to your response!

Best regards,