unexpected TOK_ID

[jalcim]

I want to test udp with Yosys.
but I have a problem (its work with icarus).

For this code :

`
module tester;
reg a, b, c;
wire out;

end3 inst0(out, a, b, c);
endmodule

primitive end3(out, a, b, c);
output out;
input a, b, c;

table
 //a b c   out
   0 0 0 : 0;
   0 0 1 : 0;
   0 1 0 : 0;
   0 1 1 : 0;
   1 0 0 : 0;
   1 0 1 : 0;
   1 1 0 : 0;
   1 1 1 : 1;
endtable

endprimitive
`

I have this error message...
Parsing Verilog input from `test.v' to AST representation.
test.v:8: ERROR: syntax error, unexpected TOK_ID

I'm stupid ?

[nakengelhardt]

The primitive syntax is not supported by yosys, sorry!

[jalcim]

Why ? What's other possibility can I have ?
Its an conception choice ?

[nakengelhardt]

Why ?

I'm not sure in this specific case if there is something that makes it especially difficult, but the general answer is "because nobody needed it desperately enough to add it"...

What's other possibility can I have ?

Do you need yosys to know the contents of the primitive or is it enough to have as blackbox? In the latter case you can read with read_verilog -lib. Or if you have liberty files you can load it with read_liberty (again this will only load blackbox models because yosys does not need to know the contents of the cells, for mapping only abc will need to look at the contents and it has its own liberty parser).

[jalcim]

I'm not sure in this specific case if there is something that makes it especially difficult, but the general answer is "because nobody needed it desperately enough to add it"...

It's legitimate.

Do you need yosys to know the contents of the primitive or is it enough to have as blackbox? In the latter case you can read with read_verilog -lib. Or if you have liberty files you can load it with read_liberty (again this will only load blackbox models because yosys does not need to know the contents of the cells, for mapping only abc will need to look at the contents and it has its own liberty parser).

Thanks a lot for the tips !