Keeping module parameters as variables, so they become BTOR2 inputs

[gussmith23]

Hi all!

Love Yosys -- this is a really impressive project that has sped along my current research in so many ways (synthesis for various backends, compilation to Verilog via the JSON format...). So thank you!

My goal: to compile Verilog modules to BTOR2, with both module parameters and ports becoming BTOR2 inputs in the output BTOR2 program.

Current status: Module ports become BTOR2 inputs, but module parameters do not.

My understanding of why this happens:

1. When Yosys reads in Verilog, it treats ports differently from parameters. Ports are essentially variables that vary at runtime, and so they are treated as such: they are just abstract objects that represent values, but don't necessarily have a concrete value at compiletime. Parameters are essentially compiletime variables; they can change at compiletime (i.e. during Yosys synthesis), but must be constant at runtime. Thus, Yosys does not represent parameters as abstract objects representing values---parameters are instead immediately converted to constant values (with the initial value being the default value of the parameter.) Yosys allows users to change their values before compilation/synthesis via commands.
2. When Yosys compiles a design to BTOR2, ports become inputs. This is because Yosys doesn't know their value, because their value will change at runtime. (As I understand it, this is also how the Verilog->BTOR2 compiler also implements undefined values! Very cool.) However, parameters are already constants, and so they just become constants in the BTOR2 program.

It seems like the fix to my issue lies not in step 2 (the Verilog->BTOR2 compiler) but instead in step 1 (the Verilog importer for Yosys). This makes the problem a lot more daunting! So I have a few questions.

1. Does Yosys currently have any tools to help me do what I'm trying to do here? This could be things like:
   • A way to tell Yosys to keep parameters "abstract"/treat them like ports when importing Verilog.
   • A way to tell the Verilog->BTOR2 converter to make parameters into inputs (I don't think this is possible; I think the parameters are very literally constants by the time the BTOR2 converter sees them).
2. How hard would this be to implement this in Yosys, and where would I begin? I suspect it might involve stopping Yosys from converting parameters to constants, but that seems like it could touch a lot of parts of the codebase!

Thanks everyone!

[nakengelhardt]

Hi! I'm afraid with the current intermediate representation this is not possible in the general case. The problem is that parameters are usually used to affect not just the values of some signals, but the geometry of the design itself. A very common use is for the width of the signals - but in the RTLIL netlist (and in the BTOR2 format iirc), the width cannot be symbolic, it has to be a concrete value. Even worse for parameters that are used in generate statements, and can affect the existence and/or number and/or connectivity of many cells in the netlist. RTLIL can only represent a concrete netlist, which is why the frontend resolves all parameters to constants when you import the design. What you propose could only work in the very limited context where parameters are used to specify some constants used in value assignments in the design, and in that case I think a verilog-to-verilog rewriter based on a parser with a better AST than Yosys would be an easier tool for the job!

[gussmith23]

Appreciate the reply, and I suspected this might be the case.

What parsers would you recommend I look at? I've looked at a few, but could always use more suggestions.