How to transfer the bahivour model to gate-level model in Verilog?

[ZhiyuanYan]

I tried to use the standard cell library to represent behaviour model as gate-level model. However, for some multiple-bit wire variable. It cannot be represented sucessfully. It will be represented like in the figure. How can I represent this into cell library.

[nakengelhardt]

The representation is only about cells, not about wires. Even in gate-level representation the wires will continue to be grouped into buses, as they have to be connected to ports etc. You can use the splitnets command if you would like to divide some wires into individual bits.

[ZhiyuanYan]

Thank you for your reply! Does it means that I cannot remove these wires by cell or other representation method? By the way, there are still some "assign" in my module. Are there any way to represent by other form?

[nakengelhardt]

I don't understand what you are trying to do - if you remove the wires, then your gates are connected to nothing? It's not a netlist without the nets...

The verilog backend emits assign for aliased wires (when the original design has two named wires that are directly connected after optimization). If you want to arbitrarily delete one of the two aliases, you can run clean -purge.

[ZhiyuanYan]

Thank you for your reply! I am trying to represent such kind of "assign" operation as a cell directly. Does it have any method?

[nakengelhardt]

No, there is no cell for this, it is not an operation - "assign" means they are supposed to be the same wire, it just has 2 names.

[ZhiyuanYan]

I see. Thank you for your reply!