What's the relationship between wire->start_offset and sigbit->offset when start_offset is negative?

[DylanLiuH2O]

Supposed that we declare an a by wire [-1:-5] a , it's start_offset is -5, then construct a signal by RTLIL::SigSpec sig(wire_a) . Is the offset of every sigbit in sig always non-negative (from 0 to GetSize(wire_a)) ?

What's the relationship between wire->start_offset and sigbit->offset when start_offset is negative?

[jix]

The RTLIL internal indexing is zero based, and wire->start_offset (together with wire->upto) defines how to map between Verilog indices and the internal indexing. So for the example in the question, the answer is yes, they're always non-negative and start at 0.

The SigSpec(RTLIL::Wire *wire) constructor creates a single SigChunk using the SigChunk(RTLIL::Wire *wire) constructor which in turn sets the offset of the SigChunk to 0 and width to GetSize(wire). When unpacking a SigChunk into individual bits, the SigBit(const RTLIL::SigChunk &chunk, int index) constructor is used with index ranging from 0 to chunk.width - 1 (inclusive) and this constructor sets sigbit.index to chunk.offset + index, so you end up with sigbits with offsets from 0 to GetSize(wire) - 1.

[DylanLiuH2O]

I got it! Thank you for your detailed answer!