Flip-flops with two outputs Q and QN

[alpwood]

Is it possible to use flip-flops with two outputs Q (non-inverted) and QN (inverted) from a liberty file? It seems that Yosys ignores these cells and uses a flip-flop with non-inverted output followed by a separate inverter instead.
According to this post there was added this functionality but it seems not to work.

Here a small example before mapping with dfflibmap and ABC:
module test(resb, clk, Q);
wire _0_; output Q; wire Q; input clk; wire clk; input resb; wire resb;

\$_DFF_PN0_ Q_reg ( .C(clk), .D(_0_), .Q(Q), .R(resb) );
\$_NOT_ _2_ ( .A(Q), .Y(_0_) );
endmodule

[alpwood]

The final netlist is
module test(resb, clk, Q);
wire _0_; output Q; wire Q; input clk; wire clk; input resb; wire resb;
INVX0 _1_ ( .A(Q), .Q(_0_) );
DFFRQX0 _2_ ( .C(clk), .D(_0_), .Q(Q), .RN(resb) );
endmodule

The expected netlist would be
module test(resb, clk, Q);
wire _0_; output Q; wire Q; input clk; wire clk; input resb; wire resb;
DFFRQQNX0 _1_ ( .C(clk), .D(Q) .Q(_0_), .QN(Q), .RN(resb) );
endmodule

[Ravenslofty]

I think that functionality got effectively broken by #2243, but conversely that PR improved support for other flop configurations, so it's a difficult thing. Flops with two outputs like that are common in ASICs, but basically unheard of in FPGAs.

Being somewhat skeptical, I think that this case isn't nearly common enough to justify special handling.

[alpwood]

Thanks for your answer. For ASICs the use of flops with two outputs Q/QN needs about 4% less area than a combination of a flop with single output followed by an inverter. The handling of flops with dual outputs would therefore optimize the overall area of a digital ASIC design. An option for this feature would be appreciated.

[Ravenslofty]

But my point is that this is an incredibly rare thing to happen in actual practice. Even if it's a 4% area reduction, if it happens basically never it's not going to be useful.