Force output assignments to occur at the end?

[j2kun]

Hi there, I've been working with Yosys for a while, doing a techmap + abc + write_verilog script, and I noticed that sometimes the resulting netlist will use assign statements to map inputs and/or intermediate wires to the output, while sometimes the output of a cell will be wired directly to the output net. Moreover, sometimes the output verilog has a cell output go to an output net, but then that output net is used by a later cell.

Is there a way to explicitly control the behavior of these output nets? Specifically, I'd like to ensure outputs are not reused by later cells, and that all output assignments happen via assign statements (even if this means introducing more intermediate wires).

So instead of a cell being expressed like

  some_cell _4_ (
    .A(_1_),
    .B(_2_),
    .C(_3_),
    .Y(out[5])
  );

I would like to export it like

  some_cell _4_ (
    .A(_1_),
    .B(_2_),
    .C(_3_),
    .Y(_99_)
  );
  ... <at the very end> ...
  assign out[5] = _99_

I'm fine with multiple assignments happening in the same assign statement, or having them in different assign statements.

[whitequark]

Are you sure you should be using Verilog as your intermediate netlist format? It sounds like a more restricted format would serve your needs better.

[j2kun]

That's a good idea! Which format do you think would be good?

[whitequark]

There are BLIF and EDIF, which are both industry standard netlist interchange formats. They have some significant flaws (but so does Verilog). It is worth taking a look at them, I think.

Alternatively, you could ingest RTLIL, Yosys' own netlist interchange format.

[j2kun]

Does Yosys have RTLIL input/output commands? I see a text format but no write_rtlil or similar in the yosys manual

[nakengelhardt]

Where are you looking at the manual? The command is included here: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/write_rtlil.html