dummy adder

[narutozxp]

Feature Description

As we hope to using the adder chain in the FPGA，However， the cin signal of adder can only get from the previous adder so we hope yosys could generate a dummy adder to output the first cin signal.
Is there any way that could realize our goal?
Thanks a lot !

[gatecat]

Yes, there are several architectures where we do such things already.

For example; on Intel ALM we create a feed-in carry ALM only if the first carry input is anything other than a constant zero:

yosys/techlibs/intel_alm/common/arith_alm_map.v

Lines 36 to 49 in d82bae3

	generate
	if (_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 1'b0) begin
	assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
	end else begin
	MISTRAL_ALUT_ARITH #(
	.LUT0(16'b1010_1010_1010_1010), // Q = A
	.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
	) alm_start (
	.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
	.CI(1'b0),
	.CO(ALM_CARRY[0])
	);
	end
	endgenerate

For FABulous, we create the feed-in carry LUT always:

yosys/techlibs/fabulous/arith_map.v

Lines 36 to 43 in d82bae3

	LUT4_HA #(
	.INIT(16'b0),
	.I0MUX(1'b1)
	) carry_statrt (
	.I0(), .I1(CI), .I2(CI), .I3(),
	.Ci(),
	.Co(CARRY[0])
	);

[narutozxp]

oh, thanks, but it seems, in FABulous, that the adders use the input signal of lut ,rather than the output signal. However, our adders use the output of lut, so the yosys should insert a lut to supply the input signal of adder.
Is there any doc that could help me to realize our goal?

[Ravenslofty]

The Intel ALM code above has the LUT and carry chain grouped together into a MISTRAL_ALUT_ARITH to achieve that.