Limiting excessive memory consumption during techmap?

[asraa]

Hi all,

I'm not too familiar with Verilog, so bear with me here. I'm trying to techmap a model that seems to exhaust my machine's RAM (32GiB). The model is only made up of arithmetic operations, and I'm curious to know why this one seems to exhaust RAM. Are there any configurations or options that will limit the memory usage during techmap?

Also, I'm generating the model programattically, so if there any design tips, I'd like to understand if I can tweak its representation to process faster. I've already been experimenting with submodules since there is repeated logic in the circuit, and while that seeems to help somewhat, I'm still running into memory exhaustion.

Here's a gist of the model https://gist.github.com/asraa/0759798fc5ba81bc17d7c8f1a4a4341d, and for reference, I'm using Yosys on my linux machine at version .28+6

Thank you!

[asraa]

Another point of reference: if I provision more RAM (up to 128 GiB) then I hit the hash table exception: https://github.com/YosysHQ/yosys/blob/master/kernel/hashlib.h#L198

[gatecat]

Roughly how big are you expecting this design to be? And what are you targeting - a particular FPGA or ASIC node?

[asraa]

Hey! We're not that interested in a target hardware or size right now, the current size of the design is:

   Number of wires:             102994
   Number of wire bits:         3413417
   Number of public wires:       57759
   Number of public wire bits:  1895309
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              45235
     $add                        17920
     $ge                           164
     $gt                          2444
     $lt                          2444
     $mul                        12487
     $mux                         5212
     $sshr                        2284
     $sub                         2280

We're only trying to use Yosys to techmap and optimize the boolean circuit, and then use the generated netlist later in our pipeline.

[j2kun]

I've run into the same problem as well, and I'm curious to know how to tell if an input is going to be too large for Yosys to handle. A rule of thumb, perhaps

[asraa]

Going to resolve this - things have been speeding up by using a more hierarchical design.