NOT cell in cmos_cells.lib not used in synthesis

[shengqilong]

After synthesis, the netlist contains the assign statement，Why isn't the BUF cell mapped to the netlist instead of the assign statement？$syn_lib contains the BUF cell declaration
yosys -q -p "read -sv xxx.sv;
hierarchy -check -top xxx;
flatten;
proc; fsm; opt; memory; opt;
techmap; opt;
write_json xxx.json;
dfflibmap -liberty $syn_lib;
abc -liberty $syn_lib;
opt_clean -purge;
write_verilog -noattr -noexpr xxx_netlist.v; "

[nakengelhardt]

That is because in verilog semantics, a buffer is a no-op, so opt_clean will always remove all buffers in the design and remap all users of wires with the same value to one representative wire. The assign statement is generated by write_verilog for the aliased wires in the internal netlist. opt_clean -purge should be removing these aliases, but it may not be able to if they are e.g. I/O ports. If you want to ensure that buffers are inserted for any direct connection between wires, you should call the insbuf command after the last opt_clean.

[shengqilong]

Thank you for your answer. I add insbuf command after the last opt_clean，the assignment statement becomes $_BUF_，but $_BUF_ is not a real BUF cell in the $syn_lib，how to change $_BUF_ to real BUF cell in $syn_lib after synthesis?

[nakengelhardt]

You need to provide the cell type to insert to the insbuf command as an argument (the default is $_BUF_). I linked the documentation of the insbuf command above; or you can type help insbuf in the yosys interactive shell to print the usage.

[shengqilong]

abc -liberty $syn_lib;
opt_clean -purge;
insbuf -chain;
abc -liberty $syn_lib;
opt_clean -purge;

Thanks again for your answer. The problem is solved when I use above command.