Are these Verilog files equivalent?

[ninehusky]

cc @gussmith23

We're trying to use Yosys to remove attributes from the following file:

module mult_0_stage_signed_1_bit(
        input signed [0:0] a,
        input signed [0:0] b,
        output signed [0:0] out,
        input clk);

        assign out = a * b;
endmodule

We do this by sending the file to the proc pass of Yosys, i.e., by running yosys -p "read_verilog -sv <filepath>; proc; write_verilog -noattr". This gives the following output:

module mult_0_stage_signed_1_bit(a, b, out, clk);                                                                                                                                                  
  wire _0_;
  input a;
  wire a;
  input b;
  wire b;
  input clk;
  wire clk;
  output out;
  wire out;
  assign _0_ = $signed(a) * $signed(b);
  assign out = _0_;
endmodule

Are these two files equivalent? It's my understanding that in the output above, the value being assigned to _0_ in the above is unsigned, while in the original file it is signed. I believe this signedness difference manifests because according to the Verilog standard, "a value assigned to a reg variable or a net shall be treated as an unsigned value unless the reg variable or net
has been explicitly declared to be signed."

Am curious for your thoughts! 

[gussmith23]

Talking to Nina and Jannis:

• We should check the spec for the bottom line on multiplication, signedness concerns
• Multiplication where the two input bitwidths and the output bitwidth are equal, signedness shouldn't matter. That is, unsigned (bitvector n) x (bitvector n) -> (bitvector n) is equivalent to signed.
• Nina mentioned that the dropping of the signed may be a problem in a larger context; something involving if this module is instantiated in such a way that the instantiator expects signedness.