Dual port RAM for complex data structure #4011
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I have an array of data objects with a (moderately) complex data structure, made up of fields of varying bit widths (1, 2, 4 and 10 bit wide fields). I'd like to be able to read the entire structure at once, but need to write individual fields. On the Ice40HX devices that I'm targeting, the BRAM primitive appears to support a bitwise write mask, so it looks like at the low level at least, I could instantiate as many parallel BRAM instances as I need to support the full width of the data structure, and then write only the bits I need for updates. The question is - is it possible to represent this at the higher level so that the 'packed' object occupies as few BRAM blocks as possible? I've looked for examples and haven't managed to come up with anything. |
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I'm guessing you want to still infer the BRAM blocks rather than manually instantiating the primitives? The bitwise write mask is treated as a byte enable in |
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I'm guessing you want to still infer the BRAM blocks rather than manually instantiating the primitives?
The bitwise write mask is treated as a byte enable in
memory_libmap, with a "byte" width of 1 bit. So if you make sure to match the byte enable pattern and do any other manipulation before those signals, it should be able to infer that.