How to constraint the maximum fanout when maping to a techfile.

[secure-v]

Hello, I want to map my design to nangate45, but it report the fanout is too high (>1000), so I want to limit the maximum fanout (<20), I have try to add (*MAX_FANOUT = 50 *) in the verilog file, but this did not work. How can I solve this problem with yosys? Beside, I also want to know about how can I find out the signal name with high fanout with yosys, O^O!

[nakengelhardt]

Yosys currently does not concern itself with high fanout at all (in fact, it will always consider any fanout-lowering measures as useless duplicate logic to be optimized away). This is something the downstream toolchain is expected to handle, though you could write your own custom yosys pass to work on this, as long as you make sure it is the very last thing to run before exporting the output netlist.

[secure-v]

Thanks!