How should I synthesize for generating smaller circuit or faster circuit ?

[takanie1967]

I use "synth" command to synthesize my Verilog model.
(This Verilog model is for training purposes.)
I can generate circuit whose clock frequency is 100MHz.
My script is following.

====BEGIN ====
read_verilog CHIPTOP.v
read_verilog DCLAMP.v
read_verilog HADJST.v
read_verilog OFFSET.v
read_verilog CPU.v
read_verilog TIMER.v
read_verilog VDETECT.v
read_verilog WDT.v
synth -top chiptop
insbuf -buf BUFX2 A Y
dfflibmap -liberty osu018_stdcells.lib
abc -liberty osu018_stdcells.lib -constr constr.txt
clean
write_verilog CHIPTOP_gate.v
==== END ====

The constr.txt is following.
set_driving_cell BUFX2
set_load 1

I want to generate next two version,
(A) clock speed is slow(e.x. 10MHz), but number of cells is smaller,
(B) number of cells is large, but clock frequency is higher(e.x. 150MHz).

What kind of Yosys script should I write?

[nakengelhardt]

Yosys is not timing-driven, it will not know what speed any circuit has, so it only ever tries to reduce the number of cells.

The only thing we currently have in that direction, if your circuit has multipliers, you can use the -booth option to use a booth multiplier architecture that has different timing characteristics than the default multiplier.

For FPGA flows, abc9 can do timing-aware lut mapping, but I don't know what timing features abc has for liberty flows.