non gate-level verilog code generated using synth_xilinx mode

[xtofalex]

Using: Yosys 0.36 (git sha1 8f07a0d, clang 15.0.0 -fPIC -Os)
with following command: synth_xilinx -top design.v
I'm seeing following verilog code:

   if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
     $display("ERROR writeBack stuck by another plugin is not allowed");
   end

synthesized as:

  always @(posedge clk) begin
    if (_132_)
      $write("ERROR writeBack stuck by another plugin is not allowed\n");
  end

This fails to be parsed in the gate level verilog parser I'm using and I'm not sure if this can be parsed in Vivado backend (I don't have access to Vivado so I cannot test this unfortunately).
Is this something new ? Using previous yosys version, I was not seeing such code being generated.
Is there a switch to disable non gate level verilog code generation ?
Thanks !
Christophe

[nakengelhardt]

Support for $display was recently added, mainly for use in sim with CXXRTL. We probably should be deleting non-synthesizable constructs in the synth_* passes now that we don't just ignore or error out when they exist...

[xtofalex]

Thanks for your answer. Should I open an issue for this topic ?

[nakengelhardt]

I opened #4122, we'll discuss the best approach to take

[xtofalex]

Thanks a lot !