how to properly prevent FSM recoding?

[gkamendje]

I am using Yosys with OpenROadFlow and I have the following SystemVerilog code

typedef enum logic [4:0] {
STATE0,
STATE1,
...
STATEN
} state_t;

 (* fsm_encoding="binary" *) state_t curr_state; 
   state_t                           next_state; 

// ----------------------------------------------------
// Current state register 
// ----------------------------------------------------

always_ff @(posedge i_clk or negedge i_rst_n  ) begin
    if ( i_rst_n == 1'b0) begin
       curr_state <= STATE0; 
    end else begin
        if (i_mem_if_en == 1'b1) begin
           curr_state <= next_state; 
        end        
    end
end

// ----------------------------------------------------
// STATES TRANSITION
// ----------------------------------------------------

always_comb begin
    my_output0  = 1'b0;
   my_output1  = 1'b0;
...
my_outputN  = 1'b0;
    next_state      = STATE0;
    unique case(curr_state)
       STATE0: begin
            my_output0   = 1'b1;
            next_state          = STATE1;
        end
       STATE1: begin
            my_output1   = 1'b1;
            next_state          = STATE2;
        end
...
       STATEN: begin
            my_outputN   = 1'b1;
            next_state          = STATE0;
        end
endcase
end

For Gate Level Simulation debug, I would like to prevent YOSYS from recoding the FSM into a one-hot format. Despite using (* fsm_encoding="binary" *) on the state variable, recoding still happens. I have tried passing the -nofsm option to the synth command but this results in an error (missing signal in an unrelated submodule). What would be the recommended way to achieve this?
BTW among all the FSM that I have in the design, only one of them is being recoded. What drives FSM recoding?

[nakengelhardt]

I can't reproduce this - do you have a complete example (RTL+yosys script)?
With the following code:

module top (input i_clk, input i_rst_n, input i_mem_if_en, output reg [3:0] my_output);

typedef enum logic [4:0] {
STATE0,
STATE1,
STATE2,
STATE3
} state_t;

(* fsm_encoding = "binary" *) state_t curr_state; 
state_t next_state; 

// ----------------------------------------------------
// Current state register 
// ----------------------------------------------------

always_ff @(posedge i_clk or negedge i_rst_n  ) begin
    if (i_rst_n == 1'b0) begin
        curr_state <= STATE0; 
    end else begin
        if (i_mem_if_en == 1'b1) begin
            curr_state <= next_state; 
        end        
    end
end

// ----------------------------------------------------
// STATES TRANSITION
// ----------------------------------------------------

always_comb begin
    my_output  = 'b0;
    next_state  = STATE0;
    unique case(curr_state)
    STATE0: begin
        my_output[0] = 1'b1;
        next_state   = STATE1;
    end
    STATE1: begin
        my_output[1] = 1'b1;
        next_state   = STATE2;
    end
    STATE2: begin
        my_output[2] = 1'b1;
        next_state   = STATE3;
    end
    STATE3: begin
        my_output[3] = 1'b1;
        next_state   = STATE0;
    end
    endcase
end

endmodule

and the script:

read_verilog top.v
hierarchy -top top
proc
opt_expr
opt_clean
opt -nodffe -nosdff
debug fsm

it correctly applies the attribute and just trims the unused bits:

Recoding FSM `$fsm$\curr_state$46' from module `\top' using `binary' encoding:
  00000 -> 00
  00010 -> 01
  00001 -> 10
  00011 -> 11

If you want it to not touch the state bits at all, you can use the attribute (* fsm_encoding = "user" *) instead.

As for what drives recoding, the heuristic there is very simple: if the FSM has less than 32 states, it prefers one-hot encoding, otherwise binary.

[gkamendje]

It looks like the attribute is simply ignored in my case. I am using the systemverilog module as a frontend and I am wondering if it does pass the attribute properly. Here is a self contained complete example (RTL + Yosys script) that reproduces the problem https://drive.google.com/file/d/1227_ul1Q_E0YteFAvkZ7HTWQ5CoVVe7A/view?usp=drive_link
Just change the pointer to the Yosys binary in the Makefile and run make kiss

[nakengelhardt]

I am using the systemverilog module as a frontend

Do you mean a third-party plugin? Have you checked if the attribute is present after importing the design?

You can run this script to check:

hierarchy -top top
proc
clean
dump w:curr_state

If you do not see attribute \fsm_encoding "user" listed in the output, that would be a problem with the plugin that you should report to its authors.

[gkamendje]

As a matter of fact, the attribute is not listed in the output. Reporting the issue to the authors.

[gkamendje]

Issue reported here chipsalliance/synlig#2263