Implementing Custom Passes in Yosys for Module Integration and Signal Connection

[mmxsrup]

Hello Yosys Community,

I am working on a synthesis toolchain project and am currently exploring the capabilities of Yosys for implementing custom synthesis passes. My objective is to integrate a custom module into my design through a Yosys pass and to establish specific signal connections between this module and other elements within the design. However, I am encountering difficulties in understanding how to effectively define and execute these custom passes within the Yosys framework.

Could someone provide insights or examples on:

1. The process for defining a custom pass in Yosys that can add a custom module to the synthesis flow?
2. How to manipulate the RTLIL representation to create connections between the custom module and existing modules or signals?

Thank you for your assistance and sharing your expertise!

[nakengelhardt]

This document has an introduction to how to create your own pass: https://github.com/YosysHQ/yosys/blob/master/guidelines/GettingStarted

To add a module, your pass can use the design->addModule(ID(your_custom_module_name)) function, and then module->addPort(), module->addWire(), and all the module->addXXX() for internal cells to construct the module contents. To instantiate the module inside another existing module, you find the module you want using design->module(ID(module_name)), then use module->addCell(ID(your_custom_module_name)) to instantiate the custom module. Then you can use cell->setPort() to connect it to wires within the existing module. If you need to add new ports to existing modules in the design to pass connections hierarchically, you can add elements to module->ports, but be sure to call module->fixup_ports() afterwards to reindex the structure.

[mmxsrup]

Thanks for your thoughtful response! I'm currently trying - the module->addPort() method doesn't seem to exist, but would it be OK to replace it with a snippet like the following?

RTLIL::Wire *a = module->addWire("\\a", 4);
a->port_input = true;
a->port_id = 1;

RTLIL::Wire *y = module->addWire("\\y", 4);
y->port_output = true;
y->port_id = 2;

[nakengelhardt]

Ah, yes, the perils of just going from memory...

Your snippet is good, but it's enough to just set port_input and port_output on the wires, unless you have a reason to change the order of the ports. You still need to call module->fixup_ports() after the snippet, it'll make sure all the internal structures describing ports are coherent again.

[mmxsrup]

Sorry for the delay in replying. I was able to create the desired path! Thank you for your kind support!