Hard Macros, etc.

[stacksmith]

I am tired of rebuilding an entire SOC with peripherals (which is invariant) just to make tiny changes to an extra circuit I am working on.

Is there a way to constrain a part of the design, and just partially rebuild a small module?

Hard macros in old Xilinx toolchain kind of worked that way, but anything along these lines would be a great help.

Pls point me in the right direction (I don't even mind building up some tools to parse/merge json or whatever if necessary)

Thank you

[whitequark]

Try write_rtlil and delete to save everything but a small part of the design. You'll also need to mark it as keep_hierarchy or it'll get merged with the rest of the netlist. Later, you can read_rtlil the saved bits, read_verilog (or whatever's your frontend) to fill in the changed part, and run synthesis again. (As far as I know, running e.g. synth_ecp5 on an already synthesized design should work fine, but I don't know if that's a well-tested path...)

There are other ways to do this, this is the one that I would personally take.

[stacksmith]

How would you define the interface between the static part and the new circuit?

Is it possible to pin some of the design after placement, or are you talking strictly synthesis?

Do you know of any examples of this technique that I could look at?

Thank you

[whitequark]

Is it possible to pin some of the design after placement, or are you talking strictly synthesis?

Not really. So if most of your time is spent in nextpnr, there is nothing you can practically do right now. (I gave an answer anyway to cover the synthesis part at least, since some designs are particularly slow to synthesize.)

How would you define the interface between the static part and the new circuit?

Given keep_hierarchy the ports of the inner circuit become that interface. This will also, of course, inhibit any optimizations crossing module boundaries.

[stacksmith]

Understood re: optimizations... The goal is to get a fast turnaround for prototyping, then do a full pass with global optimization.

Won't yosys complain or eliminate the circuit if it doesn't terminate in IO pins? Does keep_hierarchy preserve the circuit that would otherwise be incomplete?

Thanks, and would love to see an example if you can think of someplace to look... It's a bit past my comfort zone and I will likely get stuck, given my experience...

[whitequark]

Sorry, I don't have an example. This was meant to give you pointers to explore on your own.

[stacksmith]

Many thanks, understood.

[stacksmith]

If anyone can chime in with details on how to define an interface between the static circuit and the secondary one, would greatly appreciate it.