Area Increase in Yosys 0.43 vs 0.37+64 on GCD Design (ORFS)

[rr667]

Hey everyone,

I'm seeing a big area difference between Yosys 0.37+64 and 0.43 (latest) in the ORFS GCD design with Nangate45 (and other designs as well).

With Yosys 0.37+64, I get 365 cells and an area of 523.754, but Yosys 0.43 gives me 503 cells and an area of 650.104 (same design and constraints, same ABC area script).

My goal is to synthesize the design and reduce the area as much as possible, such a cliché I know, but what are the knobs in yosys and ABC to do a synthesis exploration and reduce the area? I can't seem to find good docs for this.

Thanks a lot! 😄

Here's a quick comparison:

The newer Yosys seems to be replacing complex gates (MUX, XOR) with simpler ones (INV, NAND, AOI21), reducing critical path delay but increasing area.

Yosys 0.37+64 (git sha1 bbb8ad5)

Cells: 365
Area: 523.754
Critical Path Delay: 0.4598
Total Power: 2.30e-03

Yosys 0.43 (git sha1 ead4718)

Cells: 503
Area: 650.104
Critical Path Delay: 0.4223
Total Power: 3.15e-03

Link to the ORFS thread on slack

[georgerennie]

If you can use git bisect to try to get an indication of when this regression came about that would be helpful, otherwise theres 600 odd commits between the two so its hard to suggest much. As this looks like a reasonable regression I think it would be more useful for us to know when the regression came about than just trying to tweak knobs (and its hard to know what knobs to tweak without knowing why it regressed)

[povik]

Note ORFS switched the default adder architecture from Brent-Kung to Kogge-Stone, though that’s a change in ORFS scripts not Yosys.

[povik]

The switch would show a similar increase in area

[rr667]

You're right! 😄
By adding the following line in the design config of gcd - Nangate 45, it defaults to Brent Kung adder in the techmap. BK adder is more area efficient than KS adder post layout. Reference: A Comparative Study of Adders by Sumant Dalmiya.

export SYNTH_OPERATIONS_ARGS = # (Empty = Use Default Brent Kung Adder (better area than Kogge Stone)

• Old ORFS/YOSYS

• ABC_AREA
• CORE_UTILIZATION 55
• set clk_period 2
• Adder: BK
  --- Number of cells: 365
  --- Chip area for module '\gcd': 523.754000
  --- "finish__design__core__area": 899.346

• New ORFS/YOSYS

• ABC_AREA
• CORE_UTILIZATION 55
• set clk_period 2
• Adder: KS
  --- Number of cells: 503
  --- Chip area for module '\gcd': 650.104000
  --- "finish__design__core__area": 1149.12

• New ORFS/YOSYS

• ABC_AREA
• CORE_UTILIZATION 55
• set clk_period 2
  + Adder: BK << Changed from KS to BK
  --- Number of cells: 378
  --- Chip area for module '\gcd': 563.122000
  --- "finish__design__core__area": 977.284

Conclusion: The area increase went down from 27.8% to 8.67% (wrt the old commit) which is really great! But there's an 8.67% missing. I thing it might be a better design if ORFS used BK adder instead of KS if the user used abc area script (by default).

• The new techmap file (yosys uses) is the same as the old one. (except for the module name change of the lcu). ABC Area script is the same, constraints are the same, design is the same. I've tried to build old yosys commits with newer ORFS commit (pre-built binaries method) but I kept running into version conflicts issues.

• When I comment out renames -wire in scripts/synth.tcl, there is some negligible improvement in area. it becomes 8%.

# renames -wire

Number of cells: 361
Chip area for module '\gcd': 553.280
"finish__design__core__area": 971.432

Thank you for taking the time ✔
If there are other things we can try to reduce the area even more, I'll gladly look into them.