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z80emu.c
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z80emu.c
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/* z80emu.c
* Z80 processor emulator.
*
* Copyright (C) 2012-2017 Lin Ke-Fong
*
* This code is free, you may do whatever you want with it.
*/
#include "z80emu.h"
#include "z80user.h"
#include "instructions.h"
#include "macros.h"
#include "tables.h"
/* Indirect (HL) or prefixed indexed (IX + d) and (IY + d) memory operands are
* encoded using the 3 bits "110" (0x06).
*/
#define INDIRECT_HL 0x06
/* Condition codes are encoded using 2 or 3 bits. The xor table is needed for
* negated conditions, it is used along with the and table.
*/
static const int XOR_CONDITION_TABLE[8] = {
Z80_Z_FLAG,
0,
Z80_C_FLAG,
0,
Z80_P_FLAG,
0,
Z80_S_FLAG,
0,
};
static const int AND_CONDITION_TABLE[8] = {
Z80_Z_FLAG,
Z80_Z_FLAG,
Z80_C_FLAG,
Z80_C_FLAG,
Z80_P_FLAG,
Z80_P_FLAG,
Z80_S_FLAG,
Z80_S_FLAG,
};
/* RST instruction restart addresses, encoded by Y() bits of the opcode. */
static const int RST_TABLE[8] = {
0x00,
0x08,
0x10,
0x18,
0x20,
0x28,
0x30,
0x38,
};
/* There is an overflow if the xor of the carry out and the carry of the most
* significant bit is not zero.
*/
static const int OVERFLOW_TABLE[4] = {
0,
Z80_V_FLAG,
Z80_V_FLAG,
0,
};
static int emulate (Z80_STATE * state,
int opcode,
int elapsed_cycles, int number_cycles,
void *context);
void Z80Reset (Z80_STATE *state)
{
int i;
state->status = 0;
AF = 0xffff;
SP = 0xffff;
state->i = state->pc = state->iff1 = state->iff2 = 0;
state->im = Z80_INTERRUPT_MODE_0;
/* Build register decoding tables for both 3-bit encoded 8-bit
* registers and 2-bit encoded 16-bit registers. When an opcode is
* prefixed by 0xdd, HL is replaced by IX. When 0xfd prefixed, HL is
* replaced by IY.
*/
/* 8-bit "R" registers. */
state->register_table[0] = &state->registers.byte[Z80_B];
state->register_table[1] = &state->registers.byte[Z80_C];
state->register_table[2] = &state->registers.byte[Z80_D];
state->register_table[3] = &state->registers.byte[Z80_E];
state->register_table[4] = &state->registers.byte[Z80_H];
state->register_table[5] = &state->registers.byte[Z80_L];
/* Encoding 0x06 is used for indexed memory operands and direct HL or
* IX/IY register access.
*/
state->register_table[6] = &state->registers.word[Z80_HL];
state->register_table[7] = &state->registers.byte[Z80_A];
/* "Regular" 16-bit "RR" registers. */
state->register_table[8] = &state->registers.word[Z80_BC];
state->register_table[9] = &state->registers.word[Z80_DE];
state->register_table[10] = &state->registers.word[Z80_HL];
state->register_table[11] = &state->registers.word[Z80_SP];
/* 16-bit "SS" registers for PUSH and POP instructions (note that SP is
* replaced by AF).
*/
state->register_table[12] = &state->registers.word[Z80_BC];
state->register_table[13] = &state->registers.word[Z80_DE];
state->register_table[14] = &state->registers.word[Z80_HL];
state->register_table[15] = &state->registers.word[Z80_AF];
/* 0xdd and 0xfd prefixed register decoding tables. */
for (i = 0; i < 16; i++)
state->dd_register_table[i]
= state->fd_register_table[i]
= state->register_table[i];
state->dd_register_table[4] = &state->registers.byte[Z80_IXH];
state->dd_register_table[5] = &state->registers.byte[Z80_IXL];
state->dd_register_table[6] = &state->registers.word[Z80_IX];
state->dd_register_table[10] = &state->registers.word[Z80_IX];
state->dd_register_table[14] = &state->registers.word[Z80_IX];
state->fd_register_table[4] = &state->registers.byte[Z80_IYH];
state->fd_register_table[5] = &state->registers.byte[Z80_IYL];
state->fd_register_table[6] = &state->registers.word[Z80_IY];
state->fd_register_table[10] = &state->registers.word[Z80_IY];
state->fd_register_table[14] = &state->registers.word[Z80_IY];
}
int Z80Interrupt (Z80_STATE *state, int data_on_bus, void *context)
{
state->status = 0;
if (state->iff1) {
state->iff1 = state->iff2 = 0;
state->r = (state->r & 0x80) | ((state->r + 1) & 0x7f);
switch (state->im) {
case Z80_INTERRUPT_MODE_0: {
/* Assuming the opcode in data_on_bus is an
* RST instruction, accepting the interrupt
* should take 2 + 11 = 13 cycles.
*/
return emulate(state,
data_on_bus,
2, 4,
context);
}
case Z80_INTERRUPT_MODE_1: {
int elapsed_cycles;
elapsed_cycles = 0;
SP -= 2;
Z80_WRITE_WORD_INTERRUPT(SP, state->pc);
state->pc = 0x0038;
return elapsed_cycles + 13;
}
case Z80_INTERRUPT_MODE_2:
default: {
int elapsed_cycles;
elapsed_cycles = 0;
SP -= 2;
Z80_WRITE_WORD_INTERRUPT(SP, state->pc);
state->pc =
(state->i << 8 | data_on_bus)
& 0xfffe;
return elapsed_cycles + 19;
}
}
} else
return 0;
}
int Z80NonMaskableInterrupt (Z80_STATE *state, void *context)
{
int elapsed_cycles;
state->status = 0;
state->iff2 = state->iff1;
state->iff1 = 0;
state->r = (state->r & 0x80) | ((state->r + 1) & 0x7f);
elapsed_cycles = 0;
SP -= 2;
Z80_WRITE_WORD_INTERRUPT(SP, state->pc);
state->pc = 0x0066;
return elapsed_cycles + 11;
}
int Z80Emulate (Z80_STATE *state, int number_cycles, void *context)
{
int elapsed_cycles, pc, opcode;
state->status = 0;
elapsed_cycles = 0;
pc = state->pc;
Z80_FETCH_BYTE(pc, opcode);
state->pc = pc + 1;
return emulate(state, opcode, elapsed_cycles, number_cycles, context);
}
/* Actual emulation function. opcode is the first opcode to emulate, this is
* needed by Z80Interrupt() for interrupt mode 0.
*/
static int emulate (Z80_STATE * state,
int opcode,
int elapsed_cycles, int number_cycles,
void *context)
{
int pc, r;
pc = state->pc;
r = state->r & 0x7f;
goto start_emulation;
for ( ; ; ) {
void **registers;
int instruction;
Z80_FETCH_BYTE(pc, opcode);
pc++;
start_emulation:
registers = state->register_table;
emulate_next_opcode:
instruction = INSTRUCTION_TABLE[opcode];
emulate_next_instruction:
elapsed_cycles += 4;
r++;
switch (instruction) {
/* 8-bit load group. */
case LD_R_R: {
R(Y(opcode)) = R(Z(opcode));
break;
}
case LD_R_N: {
READ_N(R(Y(opcode)));
break;
}
case LD_R_INDIRECT_HL: {
if (registers == state->register_table) {
READ_BYTE(HL, R(Y(opcode)));
} else {
int d;
READ_D(d);
d += HL_IX_IY;
READ_BYTE(d, S(Y(opcode)));
elapsed_cycles += 5;
}
break;
}
case LD_INDIRECT_HL_R: {
if (registers == state->register_table) {
WRITE_BYTE(HL, R(Z(opcode)));
} else {
int d;
READ_D(d);
d += HL_IX_IY;
WRITE_BYTE(d, S(Z(opcode)));
elapsed_cycles += 5;
}
break;
}
case LD_INDIRECT_HL_N: {
int n;
if (registers == state->register_table) {
READ_N(n);
WRITE_BYTE(HL, n);
} else {
int d;
READ_D(d);
d += HL_IX_IY;
READ_N(n);
WRITE_BYTE(d, n);
elapsed_cycles += 2;
}
break;
}
case LD_A_INDIRECT_BC: {
READ_BYTE(BC, A);
break;
}
case LD_A_INDIRECT_DE: {
READ_BYTE(DE, A);
break;
}
case LD_A_INDIRECT_NN: {
int nn;
READ_NN(nn);
READ_BYTE(nn, A);
break;
}
case LD_INDIRECT_BC_A: {
WRITE_BYTE(BC, A);
break;
}
case LD_INDIRECT_DE_A: {
WRITE_BYTE(DE, A);
break;
}
case LD_INDIRECT_NN_A: {
int nn;
READ_NN(nn);
WRITE_BYTE(nn, A);
break;
}
case LD_A_I_LD_A_R: {
int a, f;
a = opcode == OPCODE_LD_A_I
? state->i
: (state->r & 0x80) | (r & 0x7f);
f = SZYX_FLAGS_TABLE[a];
/* Note: On a real processor, if an interrupt
* occurs during the execution of either
* "LD A, I" or "LD A, R", the parity flag is
* reset. That can never happen here.
*/
f |= state->iff2 << Z80_P_FLAG_SHIFT;
f |= F & Z80_C_FLAG;
AF = (a << 8) | f;
elapsed_cycles++;
break;
}
case LD_I_A_LD_R_A: {
if (opcode == OPCODE_LD_I_A)
state->i = A;
else {
state->r = A;
r = A & 0x7f;
}
elapsed_cycles++;
break;
}
/* 16-bit load group. */
case LD_RR_NN: {
READ_NN(RR(P(opcode)));
break;
}
case LD_HL_INDIRECT_NN: {
int nn;
READ_NN(nn);
READ_WORD(nn, HL_IX_IY);
break;
}
case LD_RR_INDIRECT_NN: {
int nn;
READ_NN(nn);
READ_WORD(nn, RR(P(opcode)));
break;
}
case LD_INDIRECT_NN_HL: {
int nn;
READ_NN(nn);
WRITE_WORD(nn, HL_IX_IY);
break;
}
case LD_INDIRECT_NN_RR: {
int nn;
READ_NN(nn);
WRITE_WORD(nn, RR(P(opcode)));
break;
}
case LD_SP_HL: {
SP = HL_IX_IY;
elapsed_cycles += 2;
break;
}
case PUSH_SS: {
PUSH(SS(P(opcode)));
elapsed_cycles++;
break;
}
case POP_SS: {
POP(SS(P(opcode)));
break;
}
/* Exchange, block transfer and search group. */
case EX_DE_HL: {
EXCHANGE(DE, HL);
break;
}
case EX_AF_AF_PRIME: {
EXCHANGE(AF, state->alternates[Z80_AF]);
break;
}
case EXX: {
EXCHANGE(BC, state->alternates[Z80_BC]);
EXCHANGE(DE, state->alternates[Z80_DE]);
EXCHANGE(HL, state->alternates[Z80_HL]);
break;
}
case EX_INDIRECT_SP_HL: {
int t;
READ_WORD(SP, t);
WRITE_WORD(SP, HL_IX_IY);
HL_IX_IY = t;
elapsed_cycles += 3;
break;
}
case LDI_LDD: {
int n, f, d;
READ_BYTE(HL, n);
WRITE_BYTE(DE, n);
f = F & SZC_FLAGS;
f |= --BC ? Z80_P_FLAG : 0;
#ifndef Z80_DOCUMENTED_FLAGS_ONLY
n += A;
f |= n & Z80_X_FLAG;
f |= (n << (Z80_Y_FLAG_SHIFT - 1))
& Z80_Y_FLAG;
#endif
F = f;
d = opcode == OPCODE_LDI ? +1 : -1;
DE += d;
HL += d;
elapsed_cycles += 2;
break;
}
case LDIR_LDDR: {
int d, f, bc, de, hl, n;
#ifdef Z80_HANDLE_SELF_MODIFYING_CODE
int p, q;
p = (pc - 2) & 0xffff;
q = (pc - 1) & 0xffff;
#endif
d = opcode == OPCODE_LDIR ? +1 : -1;
f = F & SZC_FLAGS;
bc = BC;
de = DE;
hl = HL;
r -= 2;
elapsed_cycles -= 8;
for ( ; ; ) {
r += 2;
Z80_READ_BYTE(hl, n);
Z80_WRITE_BYTE(de, n);
hl += d;
de += d;
if (--bc)
elapsed_cycles += 21;
else {
elapsed_cycles += 16;
break;
}
#ifdef Z80_HANDLE_SELF_MODIFYING_CODE
if (((de - d) & 0xffff) == p
|| ((de - d) & 0xffff) == q) {
f |= Z80_P_FLAG;
pc -= 2;
break;
}
#endif
if (elapsed_cycles < number_cycles)
continue;
else {
f |= Z80_P_FLAG;
pc -= 2;
break;
}
}
HL = hl;
DE = de;
BC = bc;
#ifndef Z80_DOCUMENTED_FLAGS_ONLY
n += A;
f |= n & Z80_X_FLAG;
f |= (n << (Z80_Y_FLAG_SHIFT - 1))
& Z80_Y_FLAG;
#endif
F = f;
break;
}
case CPI_CPD: {
int a, n, z, f;
a = A;
READ_BYTE(HL, n);
z = a - n;
HL += opcode == OPCODE_CPI ? +1 : -1;
f = (a ^ n ^ z) & Z80_H_FLAG;
#ifndef Z80_DOCUMENTED_FLAGS_ONLY
n = z - (f >> Z80_H_FLAG_SHIFT);
f |= (n << (Z80_Y_FLAG_SHIFT - 1))
& Z80_Y_FLAG;
f |= n & Z80_X_FLAG;
#endif
f |= SZYX_FLAGS_TABLE[z & 0xff] & SZ_FLAGS;
f |= --BC ? Z80_P_FLAG : 0;
F = f | Z80_N_FLAG | (F & Z80_C_FLAG);
elapsed_cycles += 5;
break;
}
case CPIR_CPDR: {
int d, a, bc, hl, n, z, f;
d = opcode == OPCODE_CPIR ? +1 : -1;
a = A;
bc = BC;
hl = HL;
r -= 2;
elapsed_cycles -= 8;
for ( ; ; ) {
r += 2;
Z80_READ_BYTE(hl, n);
z = a - n;
hl += d;
if (--bc && z)
elapsed_cycles += 21;
else {
elapsed_cycles += 16;
break;
}
if (elapsed_cycles < number_cycles)
continue;
else {
pc -= 2;
break;
}
}
HL = hl;
BC = bc;
f = (a ^ n ^ z) & Z80_H_FLAG;
#ifndef Z80_DOCUMENTED_FLAGS_ONLY
n = z - (f >> Z80_H_FLAG_SHIFT);
f |= (n << (Z80_Y_FLAG_SHIFT - 1))
& Z80_Y_FLAG;
f |= n & Z80_X_FLAG;
#endif
f |= SZYX_FLAGS_TABLE[z & 0xff] & SZ_FLAGS;
f |= bc ? Z80_P_FLAG : 0;
F = f | Z80_N_FLAG | (F & Z80_C_FLAG);
break;
}
/* 8-bit arithmetic and logical group. */
case ADD_R: {
ADD(R(Z(opcode)));
break;
}
case ADD_N: {
int n;
READ_N(n);
ADD(n);
break;
}
case ADD_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
ADD(x);
break;
}
case ADC_R: {
ADC(R(Z(opcode)));
break;
}
case ADC_N: {
int n;
READ_N(n);
ADC(n);
break;
}
case ADC_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
ADC(x);
break;
}
case SUB_R: {
SUB(R(Z(opcode)));
break;
}
case SUB_N: {
int n;
READ_N(n);
SUB(n);
break;
}
case SUB_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
SUB(x);
break;
}
case SBC_R: {
SBC(R(Z(opcode)));
break;
}
case SBC_N: {
int n;
READ_N(n);
SBC(n);
break;
}
case SBC_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
SBC(x);
break;
}
case AND_R: {
AND(R(Z(opcode)));
break;
}
case AND_N: {
int n;
READ_N(n);
AND(n);
break;
}
case AND_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
AND(x);
break;
}
case OR_R: {
OR(R(Z(opcode)));
break;
}
case OR_N: {
int n;
READ_N(n);
OR(n);
break;
}
case OR_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
OR(x);
break;
}
case XOR_R: {
XOR(R(Z(opcode)));
break;
}
case XOR_N: {
int n;
READ_N(n);
XOR(n);
break;
}
case XOR_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
XOR(x);
break;
}
case CP_R: {
CP(R(Z(opcode)));
break;
}
case CP_N: {
int n;
READ_N(n);
CP(n);
break;
}
case CP_INDIRECT_HL: {
int x;
READ_INDIRECT_HL(x);
CP(x);
break;
}
case INC_R: {