From e228612fd0e48c31d7c5ab0a78a53619133e9d12 Mon Sep 17 00:00:00 2001 From: liaoao Date: Thu, 9 Nov 2023 12:18:51 +0800 Subject: [PATCH] assert:read content of undefinedinsn address read content of undefinedinsn address, and compare it with what it is in elf to check if there is a ram bit flip Signed-off-by: liaoao --- arch/arm/src/arm/arm_undefinedinsn.c | 11 ++++++++++- arch/arm/src/armv7-a/arm_undefinedinsn.c | 11 ++++++++++- arch/arm/src/armv7-r/arm_undefinedinsn.c | 11 ++++++++++- arch/arm/src/armv8-r/arm_undefinedinsn.c | 11 ++++++++++- boards/arm/lpc31xx/ea3131/scripts/pg-ld.script | 2 ++ 5 files changed, 42 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/arm/arm_undefinedinsn.c b/arch/arm/src/arm/arm_undefinedinsn.c index 7e9253a55204e..fb20aced9ea60 100644 --- a/arch/arm/src/arm/arm_undefinedinsn.c +++ b/arch/arm/src/arm/arm_undefinedinsn.c @@ -42,7 +42,16 @@ void arm_undefinedinsn(uint32_t *regs) { - _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) + { + _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", + regs[REG_PC], *(uint32_t *)regs[REG_PC]); + } + else + { + _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + } + up_set_current_regs(regs); PANIC_WITH_REGS("panic", regs); diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c index 3fb7af2bfb94f..7a6fc8ef5708c 100644 --- a/arch/arm/src/armv7-a/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c @@ -42,7 +42,16 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { - _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) + { + _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", + regs[REG_PC], *(uint32_t *)regs[REG_PC]); + } + else + { + _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + } + up_set_current_regs(regs); PANIC_WITH_REGS("panic", regs); diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c index 69dda47de7bba..6e069cbc40eb2 100644 --- a/arch/arm/src/armv7-r/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-r/arm_undefinedinsn.c @@ -42,7 +42,16 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { - _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) + { + _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", + regs[REG_PC], *(uint32_t *)regs[REG_PC]); + } + else + { + _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + } + up_set_current_regs(regs); PANIC_WITH_REGS("panic", regs); diff --git a/arch/arm/src/armv8-r/arm_undefinedinsn.c b/arch/arm/src/armv8-r/arm_undefinedinsn.c index 02025361c52b0..47568d953e975 100644 --- a/arch/arm/src/armv8-r/arm_undefinedinsn.c +++ b/arch/arm/src/armv8-r/arm_undefinedinsn.c @@ -42,7 +42,16 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { - _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) + { + _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", + regs[REG_PC], *(uint32_t *)regs[REG_PC]); + } + else + { + _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); + } + up_set_current_regs(regs); PANIC_WITH_REGS("panic", regs); diff --git a/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script b/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script index de06fb53b3b6f..372d476c77b18 100644 --- a/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script +++ b/boards/arm/lpc31xx/ea3131/scripts/pg-ld.script @@ -99,6 +99,7 @@ SECTIONS .paged : { _spaged = ABSOLUTE(.); + _stext = _spaged; *(.text .text.*) *(.fixup) *(.gnu.warning) @@ -110,6 +111,7 @@ SECTIONS *(.gcc_except_table) *(.gnu.linkonce.r.*) _epaged = ABSOLUTE(.); + _etext = _epaged; } > paged .data : {