diff --git a/py2hwsw/lib/hardware/csrs/scripts/csr_gen.py b/py2hwsw/lib/hardware/csrs/scripts/csr_gen.py
index c7e03091..ae847b19 100644
--- a/py2hwsw/lib/hardware/csrs/scripts/csr_gen.py
+++ b/py2hwsw/lib/hardware/csrs/scripts/csr_gen.py
@@ -181,6 +181,13 @@ def gen_wr_reg(self, row):
             lines += f"    assign {name}_addressed_w = (waddr >= {addr}) && (waddr < ({addr}+(2**({addr_w}))));\n"
 
         if auto:  # generate register
+            n_items = 2**eval_param_expression_from_config(log2n_items, self.config, "max")
+            # Create addressed signal for each reg in regfile
+            if n_items > 1:
+                for idx in range(n_items):
+                    name_idx = f"{name}_{idx}"
+                    lines += f"    assign {name_idx}_addressed_w = (waddr >= {addr+idx*addr_w}) && (waddr < ({addr+(idx+1)*addr_w}));\n"
+
             # fill remaining bits with 0s
             if isinstance(n_bits, str):
                 if rst_val != 0:
@@ -202,19 +209,21 @@ def gen_wr_reg(self, row):
                     rst_val_str = "{" + str(n_bits) + "{1'd0}}"
             else:
                 rst_val_str = str(n_bits) + "'d" + str(rst_val)
-            lines += f"    wire {name}_wen;\n"
-            lines += f"    assign {name}_wen = (internal_iob_valid & internal_iob_ready) & ((|internal_iob_wstrb) & {name}_addressed_w);\n"
-            lines += "    iob_reg_e #(\n"
-            lines += f"      .DATA_W({n_bits}),\n"
-            lines += f"      .RST_VAL({rst_val_str})\n"
-            lines += f"    ) {name}_datareg (\n"
-            lines += "      .clk_i  (clk_i),\n"
-            lines += "      .cke_i  (cke_i),\n"
-            lines += "      .arst_i (arst_i),\n"
-            lines += f"      .en_i   ({name}_wen),\n"
-            lines += f"      .data_i ({name}_wdata),\n"
-            lines += f"      .data_o ({name}_o)\n"
-            lines += "    );\n"
+            for idx in range(n_items):
+                name_idx = f"{name}_{idx}" if n_items > 1 else name
+                lines += f"    wire {name_idx}_wen;\n"
+                lines += f"    assign {name_idx}_wen = (internal_iob_valid & internal_iob_ready) & ((|internal_iob_wstrb) & {name_idx}_addressed_w);\n"
+                lines += "    iob_reg_e #(\n"
+                lines += f"      .DATA_W({n_bits}),\n"
+                lines += f"      .RST_VAL({rst_val_str})\n"
+                lines += f"    ) {name_idx}_datareg (\n"
+                lines += "      .clk_i  (clk_i),\n"
+                lines += "      .cke_i  (cke_i),\n"
+                lines += "      .arst_i (arst_i),\n"
+                lines += f"      .en_i   ({name_idx}_wen),\n"
+                lines += f"      .data_i ({name}_wdata),\n"
+                lines += f"      .data_o ({name_idx}_o)\n"
+                lines += "    );\n\n"
         else:  # compute wen
             lines += f"    assign {name}_wen_o = ({name}_addressed_w & (internal_iob_valid & internal_iob_ready))? |internal_iob_wstrb: 1'b0;\n"
             lines += f"    assign {name}_wdata_o = {name}_wdata;\n"
@@ -243,41 +252,6 @@ def gen_rd_reg(self, row):
 
         return lines
 
-    # generate ports for csrs module
-    def gen_port(self, table, f):
-        for row in table:
-            name = row.name
-            n_bits = row.n_bits
-            auto = row.autoreg
-
-            # version is not a register, it is an internal constant
-            if name != "version":
-                if "W" in row.type:
-                    if auto:
-                        f.write(
-                            f"    output [{self.verilog_max(n_bits,1)}-1:0] {name}_o,\n"
-                        )
-                    else:
-                        f.write(
-                            f"    output [{self.verilog_max(n_bits,1)}-1:0] {name}_wdata_o,\n"
-                        )
-                        f.write(f"    output {name}_wen_o,\n")
-                        f.write(f"    input {name}_wready_i,\n")
-                if "R" in row.type:
-                    if auto:
-                        f.write(
-                            f"    input [{self.verilog_max(n_bits,1)}-1:0] {name}_i,\n"
-                        )
-                    else:
-                        f.write(
-                            f"""
-    input [{self.verilog_max(n_bits, 1)}-1:0] {name}_rdata_i,
-    input {name}_rvalid_i,
-    output {name}_ren_o,
-    input {name}_rready_i,
-"""
-                        )
-
     # auxiliar read register case name
     def aux_read_reg_case_name(self, row):
         aux_read_reg_case_name = ""
@@ -364,6 +338,7 @@ def gen_ports(self, table):
             name = row.name
             auto = row.autoreg
             n_bits = row.n_bits
+            log2n_items = row.log2n_items
             register_signals = []
 
             # version is not a register, it is an internal constant
@@ -372,11 +347,14 @@ def gen_ports(self, table):
 
             if "W" in row.type:
                 if auto:
-                    register_signals.append({
-                        "name": name,
-                        "direction": "output",
-                        "width": self.verilog_max(n_bits, 1),
-                    })
+                    n_items = 2**eval_param_expression_from_config(log2n_items, self.config, "max")
+                    for idx in range(n_items):
+                        name_idx = f"{name}_{idx}" if n_items > 1 else name
+                        register_signals.append({
+                            "name": name_idx,
+                            "direction": "output",
+                            "width": self.verilog_max(n_bits, 1),
+                        })
                 else:
                     register_signals += [
                         {
diff --git a/py2hwsw/lib/hardware/csrs/scripts/fifos.py b/py2hwsw/lib/hardware/csrs/scripts/fifos.py
index f65fbd30..2d815715 100644
--- a/py2hwsw/lib/hardware/csrs/scripts/fifos.py
+++ b/py2hwsw/lib/hardware/csrs/scripts/fifos.py
@@ -52,7 +52,7 @@
 def find_and_update_fifo_csrs(csrs_dict):
     """Given a dictionary of CSRs, find the fifo CSRs group and update the dictionary
     accordingly.
-    User should provide a CSRs of type "*FIFO". This CSR will be replaced by fifo_csrs.
+    User should provide a CSR of type "*FIFO". This CSR will be replaced by fifo_csrs.
     """
     csr_group_ref = None
     csr_ref = None
diff --git a/py2hwsw/lib/hardware/csrs/scripts/interrupts.py b/py2hwsw/lib/hardware/csrs/scripts/interrupts.py
index 6310e78f..d650a374 100644
--- a/py2hwsw/lib/hardware/csrs/scripts/interrupts.py
+++ b/py2hwsw/lib/hardware/csrs/scripts/interrupts.py
@@ -32,7 +32,7 @@
 def find_and_update_interrupt_csrs(csrs_dict):
     """Given a dictionary of CSRs, find the interrupt CSRs group and update the dictionary
     accordingly.
-    User should provide a CSRs of type "INTERRUPT". This CSR will be replaced by interrupt_csrs.
+    User should provide a CSR of type "INTERRUPT". This CSR will be replaced by interrupt_csrs.
     """
     csr_group_ref = None
     csr_ref = None