From 3683707419f2fac050e8ce147b5db002b18521d4 Mon Sep 17 00:00:00 2001 From: Florin Popescu Date: Wed, 8 Feb 2023 00:15:56 +0100 Subject: [PATCH] added updi support and test devices --- src/devdescr.cc | 94 ++- src/ioreg.cc | 1580 ++++++++++++++++++++++++++++++++++++++++++++ src/ioreg.h | 3 + src/jtag.h | 13 +- src/jtag2io.cc | 2 + src/jtag3.h | 2 + src/jtag3io.cc | 43 +- src/jtag3rw.cc | 50 +- src/jtaggeneric.cc | 6 +- src/main.cc | 8 +- src/remote.cc | 2 +- 11 files changed, 1791 insertions(+), 12 deletions(-) diff --git a/src/devdescr.cc b/src/devdescr.cc index 41b49cd..d9b8d6e 100644 --- a/src/devdescr.cc +++ b/src/devdescr.cc @@ -6308,8 +6308,98 @@ jtag_device_def_type deviceDefinitions[] = { fill_b2(0x90), // IO space address of MCU control }, }, - // DEV_ATXMEGA64A3 - { + // DEV_ATMEGA3208 + { + "atmega3208", + 0x9552, + 128, 256, // 32768 bytes flash (page size. # pages) + 64, 4, // 256 bytes EEPROM + 0x50, // First flash address which is not an interrupt vector + DEVFL_NONE, + atmega3208_io_registers, + false, + 0x5E7, 0, // fuses + 0, // osccal + 0, // OCD revision + { + 0 // no mkI support + }, + { + 0 // no mkII JTAG support + }, + { + 0 // no Xmega support + }, + { + fill_b2(0x4000), // Start address of Program memory + 128, // Page size of flash in bytes + 64, // Page size of EEPROM + fill_b2(0x1000), // Address of NVMCTRL module + fill_b2(0x0F80), // Address of OCD module + }, + }, + // DEV_ATMEGA4808 + { + "atmega4808", + 0x9650, + 128, 384, // 49152 bytes flash (page size. # pages) + 64, 4, // 256 bytes EEPROM + 0x50, // First flash address which is not an interrupt vector + DEVFL_NONE, + atmega4808_io_registers, + false, + 0x5E7, 0, // fuses + 0, // osccal + 0, // OCD revision + { + 0 // no mkI support + }, + { + 0 // no mkII JTAG support + }, + { + 0 // no Xmega support + }, + { + fill_b2(0x4000), // Start address of Program memory + 128, // Page size of flash in bytes + 64, // Page size of EEPROM + fill_b2(0x1000), // Address of NVMCTRL module + fill_b2(0x0F80), // Address of OCD module + }, + }, + // DEV_ATMEGA4809 + { + "atmega4809", + 0x9651, + 128, 384, // 49152 bytes flash (page size. # pages) + 64, 4, // 256 bytes EEPROM + 0x50, // First flash address which is not an interrupt vector + DEVFL_NONE, + atmega4809_io_registers, + false, + 0x5E7, 0, // fuses + 0, // osccal + 0, // OCD revision + { + 0 // no mkI support + }, + { + 0 // no mkII JTAG support + }, + { + 0 // no Xmega support + }, + { + fill_b2(0x4000), // Start address of Program memory + 128, // Page size of flash in bytes + 64, // Page size of EEPROM + fill_b2(0x1000), // Address of NVMCTRL module + fill_b2(0x0F80), // Address of OCD module + }, + }, + // DEV_ATXMEGA64A3 + { "atxmega64a3", 0x9642, 256, 272, // 69,632 bytes flash (page size. # pages) diff --git a/src/ioreg.cc b/src/ioreg.cc index c21bb93..16429a1 100644 --- a/src/ioreg.cc +++ b/src/ioreg.cc @@ -7464,6 +7464,1586 @@ gdb_io_reg_def_type atmega48p_io_registers[] = }; +gdb_io_reg_def_type atmega3208_io_registers[] = +{ + { "VPORTA_DIR", 0x0, 0x00 }, + { "VPORTA_OUT", 0x1, 0x00 }, + { "VPORTA_IN" , 0x2, 0x00 }, + { "VPORTA_INTFLAGS", 0x3, 0x00 }, + { "VPORTB_DIR", 0x4, 0x00 }, + { "VPORTB_OUT", 0x5, 0x00 }, + { "VPORTB_IN" , 0x6, 0x00 }, + { "VPORTB_INTFLAGS", 0x7, 0x00 }, + { "VPORTC_DIR", 0x8, 0x00 }, + { "VPORTC_OUT", 0x9, 0x00 }, + { "VPORTC_IN" , 0xA, 0x00 }, + { "VPORTC_INTFLAGS", 0xB, 0x00 }, + { "VPORTD_DIR", 0xC, 0x00 }, + { "VPORTD_OUT", 0xD, 0x00 }, + { "VPORTD_IN" , 0xE, 0x00 }, + { "VPORTD_INTFLAGS", 0xF, 0x00 }, + { "VPORTE_DIR", 0x10, 0x00 }, + { "VPORTE_OUT", 0x11, 0x00 }, + { "VPORTE_IN" , 0x12, 0x00 }, + { "VPORTE_INTFLAGS", 0x13, 0x00 }, + { "VPORTF_DIR", 0x14, 0x00 }, + { "VPORTF_OUT", 0x15, 0x00 }, + { "VPORTF_IN" , 0x16, 0x00 }, + { "VPORTF_INTFLAGS", 0x17, 0x00 }, + { "GPIO_GPIO0", 0x1C, 0x00 }, + { "GPIO_GPIO1", 0x1D, 0x00 }, + { "GPIO_GPIO2", 0x1E, 0x00 }, + { "GPIO_GPIO3", 0x1F, 0x00 }, + { "CPU_CCP" , 0x34, 0x00 }, + { "CPU_SPL" , 0x3D, 0x00 }, + { "CPU_SPH" , 0x3E, 0x00 }, + { "CPU_SREG" , 0x3F, 0x00 }, + { "RSTCTRL_RSTFR", 0x40, 0x00 }, + { "RSTCTRL_SWRR", 0x41, 0x00 }, + { "SLPCTRL_CTRLA", 0x50, 0x00 }, + { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 }, + { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 }, + { "CLKCTRL_MCLKLOCK", 0x62, 0x00 }, + { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 }, + { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 }, + { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 }, + { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 }, + { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 }, + { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 }, + { "BOD_CTRLA" , 0x80, 0x00 }, + { "BOD_CTRLB" , 0x81, 0x00 }, + { "BOD_VLMCTRLA", 0x88, 0x00 }, + { "BOD_INTCTRL", 0x89, 0x00 }, + { "BOD_INTFLAGS", 0x8A, 0x00 }, + { "BOD_STATUS", 0x8B, 0x00 }, + { "VREF_CTRLA", 0xA0, 0x00 }, + { "VREF_CTRLB", 0xA1, 0x00 }, + { "WDT_CTRLA" , 0x100, 0x00 }, + { "WDT_STATUS", 0x101, 0x00 }, + { "CPUINT_CTRLA", 0x110, 0x00 }, + { "CPUINT_STATUS", 0x111, 0x00 }, + { "CPUINT_LVL0PRI", 0x112, 0x00 }, + { "CPUINT_LVL1VEC", 0x113, 0x00 }, + { "CRCSCAN_CTRLA", 0x120, 0x00 }, + { "CRCSCAN_CTRLB", 0x121, 0x00 }, + { "CRCSCAN_STATUS", 0x122, 0x00 }, + { "RTC_CTRLA" , 0x140, 0x00 }, + { "RTC_STATUS", 0x141, 0x00 }, + { "RTC_INTCTRL", 0x142, 0x00 }, + { "RTC_INTFLAGS", 0x143, 0x00 }, + { "RTC_TEMP" , 0x144, 0x00 }, + { "RTC_DBGCTRL", 0x145, 0x00 }, + { "RTC_CALIB" , 0x146, 0x00 }, + { "RTC_CLKSEL", 0x147, 0x00 }, + { "RTC_CNTL" , 0x148, 0x00 }, + { "RTC_CNTH" , 0x149, 0x00 }, + { "RTC_PERL" , 0x14A, 0x00 }, + { "RTC_PERH" , 0x14B, 0x00 }, + { "RTC_CMPL" , 0x14C, 0x00 }, + { "RTC_CMPH" , 0x14D, 0x00 }, + { "RTC_PITCTRLA", 0x150, 0x00 }, + { "RTC_PITSTATUS", 0x151, 0x00 }, + { "RTC_PITINTCTRL", 0x152, 0x00 }, + { "RTC_PITINTFLAGS", 0x153, 0x00 }, + { "RTC_PITDBGCTRL", 0x155, 0x00 }, + { "EVSYS_STROBE", 0x180, 0x00 }, + { "EVSYS_CHANNEL0", 0x190, 0x00 }, + { "EVSYS_CHANNEL1", 0x191, 0x00 }, + { "EVSYS_CHANNEL2", 0x192, 0x00 }, + { "EVSYS_CHANNEL3", 0x193, 0x00 }, + { "EVSYS_CHANNEL4", 0x194, 0x00 }, + { "EVSYS_CHANNEL5", 0x195, 0x00 }, + { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 }, + { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 }, + { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 }, + { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 }, + { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 }, + { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 }, + { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 }, + { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 }, + { "EVSYS_USERADC0", 0x1A8, 0x00 }, + { "EVSYS_USEREVOUTA", 0x1A9, 0x00 }, + { "EVSYS_USEREVOUTB", 0x1AA, 0x00 }, + { "EVSYS_USEREVOUTC", 0x1AB, 0x00 }, + { "EVSYS_USEREVOUTD", 0x1AC, 0x00 }, + { "EVSYS_USEREVOUTE", 0x1AD, 0x00 }, + { "EVSYS_USEREVOUTF", 0x1AE, 0x00 }, + { "EVSYS_USERUSART0", 0x1AF, 0x00 }, + { "EVSYS_USERUSART1", 0x1B0, 0x00 }, + { "EVSYS_USERUSART2", 0x1B1, 0x00 }, + { "EVSYS_USERUSART3", 0x1B2, 0x00 }, + { "EVSYS_USERTCA0", 0x1B3, 0x00 }, + { "EVSYS_USERTCB0", 0x1B4, 0x00 }, + { "EVSYS_USERTCB1", 0x1B5, 0x00 }, + { "EVSYS_USERTCB2", 0x1B6, 0x00 }, + { "EVSYS_USERTCB3", 0x1B7, 0x00 }, + { "CCL_CTRLA" , 0x1C0, 0x00 }, + { "CCL_SEQCTRL0", 0x1C1, 0x00 }, + { "CCL_SEQCTRL1", 0x1C2, 0x00 }, + { "CCL_INTCTRL0", 0x1C5, 0x00 }, + { "CCL_INTFLAGS", 0x1C7, 0x00 }, + { "CCL_LUT0CTRLA", 0x1C8, 0x00 }, + { "CCL_LUT0CTRLB", 0x1C9, 0x00 }, + { "CCL_LUT0CTRLC", 0x1CA, 0x00 }, + { "CCL_TRUTH0", 0x1CB, 0x00 }, + { "CCL_LUT1CTRLA", 0x1CC, 0x00 }, + { "CCL_LUT1CTRLB", 0x1CD, 0x00 }, + { "CCL_LUT1CTRLC", 0x1CE, 0x00 }, + { "CCL_TRUTH1", 0x1CF, 0x00 }, + { "CCL_LUT2CTRLA", 0x1D0, 0x00 }, + { "CCL_LUT2CTRLB", 0x1D1, 0x00 }, + { "CCL_LUT2CTRLC", 0x1D2, 0x00 }, + { "CCL_TRUTH2", 0x1D3, 0x00 }, + { "CCL_LUT3CTRLA", 0x1D4, 0x00 }, + { "CCL_LUT3CTRLB", 0x1D5, 0x00 }, + { "CCL_LUT3CTRLC", 0x1D6, 0x00 }, + { "CCL_TRUTH3", 0x1D7, 0x00 }, + { "PORTA_DIR" , 0x400, 0x00 }, + { "PORTA_DIRSET", 0x401, 0x00 }, + { "PORTA_DIRCLR", 0x402, 0x00 }, + { "PORTA_DIRTGL", 0x403, 0x00 }, + { "PORTA_OUT" , 0x404, 0x00 }, + { "PORTA_OUTSET", 0x405, 0x00 }, + { "PORTA_OUTCLR", 0x406, 0x00 }, + { "PORTA_OUTTGL", 0x407, 0x00 }, + { "PORTA_IN" , 0x408, 0x00 }, + { "PORTA_INTFLAGS", 0x409, 0x00 }, + { "PORTA_PORTCTRL", 0x40A, 0x00 }, + { "PORTA_PIN0CTRL", 0x410, 0x00 }, + { "PORTA_PIN1CTRL", 0x411, 0x00 }, + { "PORTA_PIN2CTRL", 0x412, 0x00 }, + { "PORTA_PIN3CTRL", 0x413, 0x00 }, + { "PORTA_PIN4CTRL", 0x414, 0x00 }, + { "PORTA_PIN5CTRL", 0x415, 0x00 }, + { "PORTA_PIN6CTRL", 0x416, 0x00 }, + { "PORTA_PIN7CTRL", 0x417, 0x00 }, + { "PORTB_DIR" , 0x420, 0x00 }, + { "PORTB_DIRSET", 0x421, 0x00 }, + { "PORTB_DIRCLR", 0x422, 0x00 }, + { "PORTB_DIRTGL", 0x423, 0x00 }, + { "PORTB_OUT" , 0x424, 0x00 }, + { "PORTB_OUTSET", 0x425, 0x00 }, + { "PORTB_OUTCLR", 0x426, 0x00 }, + { "PORTB_OUTTGL", 0x427, 0x00 }, + { "PORTB_IN" , 0x428, 0x00 }, + { "PORTB_INTFLAGS", 0x429, 0x00 }, + { "PORTB_PORTCTRL", 0x42A, 0x00 }, + { "PORTB_PIN0CTRL", 0x430, 0x00 }, + { "PORTB_PIN1CTRL", 0x431, 0x00 }, + { "PORTB_PIN2CTRL", 0x432, 0x00 }, + { "PORTB_PIN3CTRL", 0x433, 0x00 }, + { "PORTB_PIN4CTRL", 0x434, 0x00 }, + { "PORTB_PIN5CTRL", 0x435, 0x00 }, + { "PORTB_PIN6CTRL", 0x436, 0x00 }, + { "PORTB_PIN7CTRL", 0x437, 0x00 }, + { "PORTC_DIR" , 0x440, 0x00 }, + { "PORTC_DIRSET", 0x441, 0x00 }, + { "PORTC_DIRCLR", 0x442, 0x00 }, + { "PORTC_DIRTGL", 0x443, 0x00 }, + { "PORTC_OUT" , 0x444, 0x00 }, + { "PORTC_OUTSET", 0x445, 0x00 }, + { "PORTC_OUTCLR", 0x446, 0x00 }, + { "PORTC_OUTTGL", 0x447, 0x00 }, + { "PORTC_IN" , 0x448, 0x00 }, + { "PORTC_INTFLAGS", 0x449, 0x00 }, + { "PORTC_PORTCTRL", 0x44A, 0x00 }, + { "PORTC_PIN0CTRL", 0x450, 0x00 }, + { "PORTC_PIN1CTRL", 0x451, 0x00 }, + { "PORTC_PIN2CTRL", 0x452, 0x00 }, + { "PORTC_PIN3CTRL", 0x453, 0x00 }, + { "PORTC_PIN4CTRL", 0x454, 0x00 }, + { "PORTC_PIN5CTRL", 0x455, 0x00 }, + { "PORTC_PIN6CTRL", 0x456, 0x00 }, + { "PORTC_PIN7CTRL", 0x457, 0x00 }, + { "PORTD_DIR" , 0x460, 0x00 }, + { "PORTD_DIRSET", 0x461, 0x00 }, + { "PORTD_DIRCLR", 0x462, 0x00 }, + { "PORTD_DIRTGL", 0x463, 0x00 }, + { "PORTD_OUT" , 0x464, 0x00 }, + { "PORTD_OUTSET", 0x465, 0x00 }, + { "PORTD_OUTCLR", 0x466, 0x00 }, + { "PORTD_OUTTGL", 0x467, 0x00 }, + { "PORTD_IN" , 0x468, 0x00 }, + { "PORTD_INTFLAGS", 0x469, 0x00 }, + { "PORTD_PORTCTRL", 0x46A, 0x00 }, + { "PORTD_PIN0CTRL", 0x470, 0x00 }, + { "PORTD_PIN1CTRL", 0x471, 0x00 }, + { "PORTD_PIN2CTRL", 0x472, 0x00 }, + { "PORTD_PIN3CTRL", 0x473, 0x00 }, + { "PORTD_PIN4CTRL", 0x474, 0x00 }, + { "PORTD_PIN5CTRL", 0x475, 0x00 }, + { "PORTD_PIN6CTRL", 0x476, 0x00 }, + { "PORTD_PIN7CTRL", 0x477, 0x00 }, + { "PORTE_DIR" , 0x480, 0x00 }, + { "PORTE_DIRSET", 0x481, 0x00 }, + { "PORTE_DIRCLR", 0x482, 0x00 }, + { "PORTE_DIRTGL", 0x483, 0x00 }, + { "PORTE_OUT" , 0x484, 0x00 }, + { "PORTE_OUTSET", 0x485, 0x00 }, + { "PORTE_OUTCLR", 0x486, 0x00 }, + { "PORTE_OUTTGL", 0x487, 0x00 }, + { "PORTE_IN" , 0x488, 0x00 }, + { "PORTE_INTFLAGS", 0x489, 0x00 }, + { "PORTE_PORTCTRL", 0x48A, 0x00 }, + { "PORTE_PIN0CTRL", 0x490, 0x00 }, + { "PORTE_PIN1CTRL", 0x491, 0x00 }, + { "PORTE_PIN2CTRL", 0x492, 0x00 }, + { "PORTE_PIN3CTRL", 0x493, 0x00 }, + { "PORTE_PIN4CTRL", 0x494, 0x00 }, + { "PORTE_PIN5CTRL", 0x495, 0x00 }, + { "PORTE_PIN6CTRL", 0x496, 0x00 }, + { "PORTE_PIN7CTRL", 0x497, 0x00 }, + { "PORTF_DIR" , 0x4A0, 0x00 }, + { "PORTF_DIRSET", 0x4A1, 0x00 }, + { "PORTF_DIRCLR", 0x4A2, 0x00 }, + { "PORTF_DIRTGL", 0x4A3, 0x00 }, + { "PORTF_OUT" , 0x4A4, 0x00 }, + { "PORTF_OUTSET", 0x4A5, 0x00 }, + { "PORTF_OUTCLR", 0x4A6, 0x00 }, + { "PORTF_OUTTGL", 0x4A7, 0x00 }, + { "PORTF_IN" , 0x4A8, 0x00 }, + { "PORTF_INTFLAGS", 0x4A9, 0x00 }, + { "PORTF_PORTCTRL", 0x4AA, 0x00 }, + { "PORTF_PIN0CTRL", 0x4B0, 0x00 }, + { "PORTF_PIN1CTRL", 0x4B1, 0x00 }, + { "PORTF_PIN2CTRL", 0x4B2, 0x00 }, + { "PORTF_PIN3CTRL", 0x4B3, 0x00 }, + { "PORTF_PIN4CTRL", 0x4B4, 0x00 }, + { "PORTF_PIN5CTRL", 0x4B5, 0x00 }, + { "PORTF_PIN6CTRL", 0x4B6, 0x00 }, + { "PORTF_PIN7CTRL", 0x4B7, 0x00 }, + { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 }, + { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 }, + { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 }, + { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 }, + { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 }, + { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 }, + { "ADC0_CTRLA", 0x600, 0x00 }, + { "ADC0_CTRLB", 0x601, 0x00 }, + { "ADC0_CTRLC", 0x602, 0x00 }, + { "ADC0_CTRLD", 0x603, 0x00 }, + { "ADC0_CTRLE", 0x604, 0x00 }, + { "ADC0_SAMPCTRL", 0x605, 0x00 }, + { "ADC0_MUXPOS", 0x606, 0x00 }, + { "ADC0_COMMAND", 0x608, 0x00 }, + { "ADC0_EVCTRL", 0x609, 0x00 }, + { "ADC0_INTCTRL", 0x60A, 0x00 }, + { "ADC0_INTFLAGS", 0x60B, 0x00 }, + { "ADC0_DBGCTRL", 0x60C, 0x00 }, + { "ADC0_TEMP" , 0x60D, 0x00 }, + { "ADC0_RESL" , 0x610, 0x00 }, + { "ADC0_RESH" , 0x611, 0x00 }, + { "ADC0_WINLTL", 0x612, 0x00 }, + { "ADC0_WINLTH", 0x613, 0x00 }, + { "ADC0_WINHTL", 0x614, 0x00 }, + { "ADC0_WINHTH", 0x615, 0x00 }, + { "ADC0_CALIB", 0x616, 0x00 }, + { "AC0_CTRLA" , 0x680, 0x00 }, + { "AC0_MUXCTRLA", 0x682, 0x00 }, + { "AC0_DACREF", 0x684, 0x00 }, + { "AC0_INTCTRL", 0x686, 0x00 }, + { "AC0_STATUS", 0x687, 0x00 }, + { "USART0_RXDATAL", 0x800, 0x00 }, + { "USART0_RXDATAH", 0x801, 0x00 }, + { "USART0_TXDATAL", 0x802, 0x00 }, + { "USART0_TXDATAH", 0x803, 0x00 }, + { "USART0_STATUS", 0x804, 0x00 }, + { "USART0_CTRLA", 0x805, 0x00 }, + { "USART0_CTRLB", 0x806, 0x00 }, + { "USART0_CTRLC", 0x807, 0x00 }, + { "USART0_BAUDL", 0x808, 0x00 }, + { "USART0_BAUDH", 0x809, 0x00 }, + { "USART0_CTRLD", 0x80A, 0x00 }, + { "USART0_DBGCTRL", 0x80B, 0x00 }, + { "USART0_EVCTRL", 0x80C, 0x00 }, + { "USART0_TXPLCTRL", 0x80D, 0x00 }, + { "USART0_RXPLCTRL", 0x80E, 0x00 }, + { "USART1_RXDATAL", 0x820, 0x00 }, + { "USART1_RXDATAH", 0x821, 0x00 }, + { "USART1_TXDATAL", 0x822, 0x00 }, + { "USART1_TXDATAH", 0x823, 0x00 }, + { "USART1_STATUS", 0x824, 0x00 }, + { "USART1_CTRLA", 0x825, 0x00 }, + { "USART1_CTRLB", 0x826, 0x00 }, + { "USART1_CTRLC", 0x827, 0x00 }, + { "USART1_BAUDL", 0x828, 0x00 }, + { "USART1_BAUDH", 0x829, 0x00 }, + { "USART1_CTRLD", 0x82A, 0x00 }, + { "USART1_DBGCTRL", 0x82B, 0x00 }, + { "USART1_EVCTRL", 0x82C, 0x00 }, + { "USART1_TXPLCTRL", 0x82D, 0x00 }, + { "USART1_RXPLCTRL", 0x82E, 0x00 }, + { "USART2_RXDATAL", 0x840, 0x00 }, + { "USART2_RXDATAH", 0x841, 0x00 }, + { "USART2_TXDATAL", 0x842, 0x00 }, + { "USART2_TXDATAH", 0x843, 0x00 }, + { "USART2_STATUS", 0x844, 0x00 }, + { "USART2_CTRLA", 0x845, 0x00 }, + { "USART2_CTRLB", 0x846, 0x00 }, + { "USART2_CTRLC", 0x847, 0x00 }, + { "USART2_BAUDL", 0x848, 0x00 }, + { "USART2_BAUDH", 0x849, 0x00 }, + { "USART2_CTRLD", 0x84A, 0x00 }, + { "USART2_DBGCTRL", 0x84B, 0x00 }, + { "USART2_EVCTRL", 0x84C, 0x00 }, + { "USART2_TXPLCTRL", 0x84D, 0x00 }, + { "USART2_RXPLCTRL", 0x84E, 0x00 }, + { "TWI0_CTRLA", 0x8A0, 0x00 }, + { "TWI0_DUALCTRL", 0x8A1, 0x00 }, + { "TWI0_DBGCTRL", 0x8A2, 0x00 }, + { "TWI0_MCTRLA", 0x8A3, 0x00 }, + { "TWI0_MCTRLB", 0x8A4, 0x00 }, + { "TWI0_MSTATUS", 0x8A5, 0x00 }, + { "TWI0_MBAUD", 0x8A6, 0x00 }, + { "TWI0_MADDR", 0x8A7, 0x00 }, + { "TWI0_MDATA", 0x8A8, 0x00 }, + { "TWI0_SCTRLA", 0x8A9, 0x00 }, + { "TWI0_SCTRLB", 0x8AA, 0x00 }, + { "TWI0_SSTATUS", 0x8AB, 0x00 }, + { "TWI0_SADDR", 0x8AC, 0x00 }, + { "TWI0_SDATA", 0x8AD, 0x00 }, + { "TWI0_SADDRMASK", 0x8AE, 0x00 }, + { "SPI0_CTRLA", 0x8C0, 0x00 }, + { "SPI0_CTRLB", 0x8C1, 0x00 }, + { "SPI0_INTCTRL", 0x8C2, 0x00 }, + { "SPI0_INTFLAGS", 0x8C3, 0x00 }, + { "SPI0_DATA" , 0x8C4, 0x00 }, + { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 }, + { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 }, + { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 }, + { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 }, + { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 }, + { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 }, + { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 }, + { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 }, + { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 }, + { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 }, + { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 }, + { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 }, + { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 }, + { "TCA0_SPLIT_LCNT", 0xA20, 0x00 }, + { "TCA0_SPLIT_HCNT", 0xA21, 0x00 }, + { "TCA0_SPLIT_LPER", 0xA26, 0x00 }, + { "TCA0_SPLIT_HPER", 0xA27, 0x00 }, + { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 }, + { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 }, + { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 }, + { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 }, + { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 }, + { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 }, + { "TCB0_CTRLA", 0xA80, 0x00 }, + { "TCB0_CTRLB", 0xA81, 0x00 }, + { "TCB0_EVCTRL", 0xA84, 0x00 }, + { "TCB0_INTCTRL", 0xA85, 0x00 }, + { "TCB0_INTFLAGS", 0xA86, 0x00 }, + { "TCB0_STATUS", 0xA87, 0x00 }, + { "TCB0_DBGCTRL", 0xA88, 0x00 }, + { "TCB0_TEMP" , 0xA89, 0x00 }, + { "TCB0_CNTL" , 0xA8A, 0x00 }, + { "TCB0_CNTH" , 0xA8B, 0x00 }, + { "TCB0_CCMPL", 0xA8C, 0x00 }, + { "TCB0_CCMPH", 0xA8D, 0x00 }, + { "TCB1_CTRLA", 0xA90, 0x00 }, + { "TCB1_CTRLB", 0xA91, 0x00 }, + { "TCB1_EVCTRL", 0xA94, 0x00 }, + { "TCB1_INTCTRL", 0xA95, 0x00 }, + { "TCB1_INTFLAGS", 0xA96, 0x00 }, + { "TCB1_STATUS", 0xA97, 0x00 }, + { "TCB1_DBGCTRL", 0xA98, 0x00 }, + { "TCB1_TEMP" , 0xA99, 0x00 }, + { "TCB1_CNTL" , 0xA9A, 0x00 }, + { "TCB1_CNTH" , 0xA9B, 0x00 }, + { "TCB1_CCMPL", 0xA9C, 0x00 }, + { "TCB1_CCMPH", 0xA9D, 0x00 }, + { "TCB2_CTRLA", 0xAA0, 0x00 }, + { "TCB2_CTRLB", 0xAA1, 0x00 }, + { "TCB2_EVCTRL", 0xAA4, 0x00 }, + { "TCB2_INTCTRL", 0xAA5, 0x00 }, + { "TCB2_INTFLAGS", 0xAA6, 0x00 }, + { "TCB2_STATUS", 0xAA7, 0x00 }, + { "TCB2_DBGCTRL", 0xAA8, 0x00 }, + { "TCB2_TEMP" , 0xAA9, 0x00 }, + { "TCB2_CNTL" , 0xAAA, 0x00 }, + { "TCB2_CNTH" , 0xAAB, 0x00 }, + { "TCB2_CCMPL", 0xAAC, 0x00 }, + { "TCB2_CCMPH", 0xAAD, 0x00 }, + { "SYSCFG_REVID", 0xF01, 0x00 }, + { "SYSCFG_EXTBRK", 0xF02, 0x00 }, + { "SYSCFG_OCDM", 0xF18, 0x00 }, + { "SYSCFG_OCDMS", 0xF19, 0x00 }, + { "NVMCTRL_CTRLA", 0x1000, 0x00 }, + { "NVMCTRL_CTRLB", 0x1001, 0x00 }, + { "NVMCTRL_STATUS", 0x1002, 0x00 }, + { "NVMCTRL_INTCTRL", 0x1003, 0x00 }, + { "NVMCTRL_INTFLAGS", 0x1004, 0x00 }, + { "NVMCTRL_DATAL", 0x1006, 0x00 }, + { "NVMCTRL_DATAH", 0x1007, 0x00 }, + { "NVMCTRL_ADDRL", 0x1008, 0x00 }, + { "NVMCTRL_ADDRH", 0x1009, 0x00 }, + { "SIGROW_DEVICEID0", 0x1100, 0x00 }, + { "SIGROW_DEVICEID1", 0x1101, 0x00 }, + { "SIGROW_DEVICEID2", 0x1102, 0x00 }, + { "SIGROW_SERNUM0", 0x1103, 0x00 }, + { "SIGROW_SERNUM1", 0x1104, 0x00 }, + { "SIGROW_SERNUM2", 0x1105, 0x00 }, + { "SIGROW_SERNUM3", 0x1106, 0x00 }, + { "SIGROW_SERNUM4", 0x1107, 0x00 }, + { "SIGROW_SERNUM5", 0x1108, 0x00 }, + { "SIGROW_SERNUM6", 0x1109, 0x00 }, + { "SIGROW_SERNUM7", 0x110A, 0x00 }, + { "SIGROW_SERNUM8", 0x110B, 0x00 }, + { "SIGROW_SERNUM9", 0x110C, 0x00 }, + { "SIGROW_OSCCAL32K", 0x1114, 0x00 }, + { "SIGROW_OSCCAL16M0", 0x1118, 0x00 }, + { "SIGROW_OSCCAL16M1", 0x1119, 0x00 }, + { "SIGROW_OSCCAL20M0", 0x111A, 0x00 }, + { "SIGROW_OSCCAL20M1", 0x111B, 0x00 }, + { "SIGROW_TEMPSENSE0", 0x1120, 0x00 }, + { "SIGROW_TEMPSENSE1", 0x1121, 0x00 }, + { "SIGROW_OSC16ERR3V", 0x1122, 0x00 }, + { "SIGROW_OSC16ERR5V", 0x1123, 0x00 }, + { "SIGROW_OSC20ERR3V", 0x1124, 0x00 }, + { "SIGROW_OSC20ERR5V", 0x1125, 0x00 }, + { "SIGROW_CHECKSUM1", 0x112F, 0x00 }, + { "FUSE_WDTCFG", 0x1280, 0x00 }, + { "FUSE_BODCFG", 0x1281, 0x00 }, + { "FUSE_OSCCFG", 0x1282, 0x00 }, + { "FUSE_SYSCFG0", 0x1285, 0x00 }, + { "FUSE_SYSCFG1", 0x1286, 0x00 }, + { "FUSE_APPEND", 0x1287, 0x00 }, + { "FUSE_BOOTEND", 0x1288, 0x00 }, + { "LOCKBIT_LOCKBIT", 0x128A, 0x00 }, + { "USERROW_USERROW0", 0x1300, 0x00 }, + { "USERROW_USERROW1", 0x1301, 0x00 }, + { "USERROW_USERROW2", 0x1302, 0x00 }, + { "USERROW_USERROW3", 0x1303, 0x00 }, + { "USERROW_USERROW4", 0x1304, 0x00 }, + { "USERROW_USERROW5", 0x1305, 0x00 }, + { "USERROW_USERROW6", 0x1306, 0x00 }, + { "USERROW_USERROW7", 0x1307, 0x00 }, + { "USERROW_USERROW8", 0x1308, 0x00 }, + { "USERROW_USERROW9", 0x1309, 0x00 }, + { "USERROW_USERROW10", 0x130A, 0x00 }, + { "USERROW_USERROW11", 0x130B, 0x00 }, + { "USERROW_USERROW12", 0x130C, 0x00 }, + { "USERROW_USERROW13", 0x130D, 0x00 }, + { "USERROW_USERROW14", 0x130E, 0x00 }, + { "USERROW_USERROW15", 0x130F, 0x00 }, + { "USERROW_USERROW16", 0x1310, 0x00 }, + { "USERROW_USERROW17", 0x1311, 0x00 }, + { "USERROW_USERROW18", 0x1312, 0x00 }, + { "USERROW_USERROW19", 0x1313, 0x00 }, + { "USERROW_USERROW20", 0x1314, 0x00 }, + { "USERROW_USERROW21", 0x1315, 0x00 }, + { "USERROW_USERROW22", 0x1316, 0x00 }, + { "USERROW_USERROW23", 0x1317, 0x00 }, + { "USERROW_USERROW24", 0x1318, 0x00 }, + { "USERROW_USERROW25", 0x1319, 0x00 }, + { "USERROW_USERROW26", 0x131A, 0x00 }, + { "USERROW_USERROW27", 0x131B, 0x00 }, + { "USERROW_USERROW28", 0x131C, 0x00 }, + { "USERROW_USERROW29", 0x131D, 0x00 }, + { "USERROW_USERROW30", 0x131E, 0x00 }, + { "USERROW_USERROW31", 0x131F, 0x00 }, + { "USERROW_USERROW32", 0x1320, 0x00 }, + { "USERROW_USERROW33", 0x1321, 0x00 }, + { "USERROW_USERROW34", 0x1322, 0x00 }, + { "USERROW_USERROW35", 0x1323, 0x00 }, + { "USERROW_USERROW36", 0x1324, 0x00 }, + { "USERROW_USERROW37", 0x1325, 0x00 }, + { "USERROW_USERROW38", 0x1326, 0x00 }, + { "USERROW_USERROW39", 0x1327, 0x00 }, + { "USERROW_USERROW40", 0x1328, 0x00 }, + { "USERROW_USERROW41", 0x1329, 0x00 }, + { "USERROW_USERROW42", 0x132A, 0x00 }, + { "USERROW_USERROW43", 0x132B, 0x00 }, + { "USERROW_USERROW44", 0x132C, 0x00 }, + { "USERROW_USERROW45", 0x132D, 0x00 }, + { "USERROW_USERROW46", 0x132E, 0x00 }, + { "USERROW_USERROW47", 0x132F, 0x00 }, + { "USERROW_USERROW48", 0x1330, 0x00 }, + { "USERROW_USERROW49", 0x1331, 0x00 }, + { "USERROW_USERROW50", 0x1332, 0x00 }, + { "USERROW_USERROW51", 0x1333, 0x00 }, + { "USERROW_USERROW52", 0x1334, 0x00 }, + { "USERROW_USERROW53", 0x1335, 0x00 }, + { "USERROW_USERROW54", 0x1336, 0x00 }, + { "USERROW_USERROW55", 0x1337, 0x00 }, + { "USERROW_USERROW56", 0x1338, 0x00 }, + { "USERROW_USERROW57", 0x1339, 0x00 }, + { "USERROW_USERROW58", 0x133A, 0x00 }, + { "USERROW_USERROW59", 0x133B, 0x00 }, + { "USERROW_USERROW60", 0x133C, 0x00 }, + { "USERROW_USERROW61", 0x133D, 0x00 }, + { "USERROW_USERROW62", 0x133E, 0x00 }, + { "USERROW_USERROW63", 0x133F, 0x00 }, + { 0, 0, 0} +}; + + +gdb_io_reg_def_type atmega4808_io_registers[] = +{ + { "VPORTA_DIR", 0x0, 0x00 }, + { "VPORTA_OUT", 0x1, 0x00 }, + { "VPORTA_IN" , 0x2, 0x00 }, + { "VPORTA_INTFLAGS", 0x3, 0x00 }, + { "VPORTB_DIR", 0x4, 0x00 }, + { "VPORTB_OUT", 0x5, 0x00 }, + { "VPORTB_IN" , 0x6, 0x00 }, + { "VPORTB_INTFLAGS", 0x7, 0x00 }, + { "VPORTC_DIR", 0x8, 0x00 }, + { "VPORTC_OUT", 0x9, 0x00 }, + { "VPORTC_IN" , 0xA, 0x00 }, + { "VPORTC_INTFLAGS", 0xB, 0x00 }, + { "VPORTD_DIR", 0xC, 0x00 }, + { "VPORTD_OUT", 0xD, 0x00 }, + { "VPORTD_IN" , 0xE, 0x00 }, + { "VPORTD_INTFLAGS", 0xF, 0x00 }, + { "VPORTE_DIR", 0x10, 0x00 }, + { "VPORTE_OUT", 0x11, 0x00 }, + { "VPORTE_IN" , 0x12, 0x00 }, + { "VPORTE_INTFLAGS", 0x13, 0x00 }, + { "VPORTF_DIR", 0x14, 0x00 }, + { "VPORTF_OUT", 0x15, 0x00 }, + { "VPORTF_IN" , 0x16, 0x00 }, + { "VPORTF_INTFLAGS", 0x17, 0x00 }, + { "GPIO_GPIO0", 0x1C, 0x00 }, + { "GPIO_GPIO1", 0x1D, 0x00 }, + { "GPIO_GPIO2", 0x1E, 0x00 }, + { "GPIO_GPIO3", 0x1F, 0x00 }, + { "CPU_CCP" , 0x34, 0x00 }, + { "CPU_SPL" , 0x3D, 0x00 }, + { "CPU_SPH" , 0x3E, 0x00 }, + { "CPU_SREG" , 0x3F, 0x00 }, + { "RSTCTRL_RSTFR", 0x40, 0x00 }, + { "RSTCTRL_SWRR", 0x41, 0x00 }, + { "SLPCTRL_CTRLA", 0x50, 0x00 }, + { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 }, + { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 }, + { "CLKCTRL_MCLKLOCK", 0x62, 0x00 }, + { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 }, + { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 }, + { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 }, + { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 }, + { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 }, + { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 }, + { "BOD_CTRLA" , 0x80, 0x00 }, + { "BOD_CTRLB" , 0x81, 0x00 }, + { "BOD_VLMCTRLA", 0x88, 0x00 }, + { "BOD_INTCTRL", 0x89, 0x00 }, + { "BOD_INTFLAGS", 0x8A, 0x00 }, + { "BOD_STATUS", 0x8B, 0x00 }, + { "VREF_CTRLA", 0xA0, 0x00 }, + { "VREF_CTRLB", 0xA1, 0x00 }, + { "WDT_CTRLA" , 0x100, 0x00 }, + { "WDT_STATUS", 0x101, 0x00 }, + { "CPUINT_CTRLA", 0x110, 0x00 }, + { "CPUINT_STATUS", 0x111, 0x00 }, + { "CPUINT_LVL0PRI", 0x112, 0x00 }, + { "CPUINT_LVL1VEC", 0x113, 0x00 }, + { "CRCSCAN_CTRLA", 0x120, 0x00 }, + { "CRCSCAN_CTRLB", 0x121, 0x00 }, + { "CRCSCAN_STATUS", 0x122, 0x00 }, + { "RTC_CTRLA" , 0x140, 0x00 }, + { "RTC_STATUS", 0x141, 0x00 }, + { "RTC_INTCTRL", 0x142, 0x00 }, + { "RTC_INTFLAGS", 0x143, 0x00 }, + { "RTC_TEMP" , 0x144, 0x00 }, + { "RTC_DBGCTRL", 0x145, 0x00 }, + { "RTC_CALIB" , 0x146, 0x00 }, + { "RTC_CLKSEL", 0x147, 0x00 }, + { "RTC_CNTL" , 0x148, 0x00 }, + { "RTC_CNTH" , 0x149, 0x00 }, + { "RTC_PERL" , 0x14A, 0x00 }, + { "RTC_PERH" , 0x14B, 0x00 }, + { "RTC_CMPL" , 0x14C, 0x00 }, + { "RTC_CMPH" , 0x14D, 0x00 }, + { "RTC_PITCTRLA", 0x150, 0x00 }, + { "RTC_PITSTATUS", 0x151, 0x00 }, + { "RTC_PITINTCTRL", 0x152, 0x00 }, + { "RTC_PITINTFLAGS", 0x153, 0x00 }, + { "RTC_PITDBGCTRL", 0x155, 0x00 }, + { "EVSYS_STROBE", 0x180, 0x00 }, + { "EVSYS_CHANNEL0", 0x190, 0x00 }, + { "EVSYS_CHANNEL1", 0x191, 0x00 }, + { "EVSYS_CHANNEL2", 0x192, 0x00 }, + { "EVSYS_CHANNEL3", 0x193, 0x00 }, + { "EVSYS_CHANNEL4", 0x194, 0x00 }, + { "EVSYS_CHANNEL5", 0x195, 0x00 }, + { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 }, + { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 }, + { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 }, + { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 }, + { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 }, + { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 }, + { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 }, + { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 }, + { "EVSYS_USERADC0", 0x1A8, 0x00 }, + { "EVSYS_USEREVOUTA", 0x1A9, 0x00 }, + { "EVSYS_USEREVOUTB", 0x1AA, 0x00 }, + { "EVSYS_USEREVOUTC", 0x1AB, 0x00 }, + { "EVSYS_USEREVOUTD", 0x1AC, 0x00 }, + { "EVSYS_USEREVOUTE", 0x1AD, 0x00 }, + { "EVSYS_USEREVOUTF", 0x1AE, 0x00 }, + { "EVSYS_USERUSART0", 0x1AF, 0x00 }, + { "EVSYS_USERUSART1", 0x1B0, 0x00 }, + { "EVSYS_USERUSART2", 0x1B1, 0x00 }, + { "EVSYS_USERUSART3", 0x1B2, 0x00 }, + { "EVSYS_USERTCA0", 0x1B3, 0x00 }, + { "EVSYS_USERTCB0", 0x1B4, 0x00 }, + { "EVSYS_USERTCB1", 0x1B5, 0x00 }, + { "EVSYS_USERTCB2", 0x1B6, 0x00 }, + { "EVSYS_USERTCB3", 0x1B7, 0x00 }, + { "CCL_CTRLA" , 0x1C0, 0x00 }, + { "CCL_SEQCTRL0", 0x1C1, 0x00 }, + { "CCL_SEQCTRL1", 0x1C2, 0x00 }, + { "CCL_INTCTRL0", 0x1C5, 0x00 }, + { "CCL_INTFLAGS", 0x1C7, 0x00 }, + { "CCL_LUT0CTRLA", 0x1C8, 0x00 }, + { "CCL_LUT0CTRLB", 0x1C9, 0x00 }, + { "CCL_LUT0CTRLC", 0x1CA, 0x00 }, + { "CCL_TRUTH0", 0x1CB, 0x00 }, + { "CCL_LUT1CTRLA", 0x1CC, 0x00 }, + { "CCL_LUT1CTRLB", 0x1CD, 0x00 }, + { "CCL_LUT1CTRLC", 0x1CE, 0x00 }, + { "CCL_TRUTH1", 0x1CF, 0x00 }, + { "CCL_LUT2CTRLA", 0x1D0, 0x00 }, + { "CCL_LUT2CTRLB", 0x1D1, 0x00 }, + { "CCL_LUT2CTRLC", 0x1D2, 0x00 }, + { "CCL_TRUTH2", 0x1D3, 0x00 }, + { "CCL_LUT3CTRLA", 0x1D4, 0x00 }, + { "CCL_LUT3CTRLB", 0x1D5, 0x00 }, + { "CCL_LUT3CTRLC", 0x1D6, 0x00 }, + { "CCL_TRUTH3", 0x1D7, 0x00 }, + { "PORTA_DIR" , 0x400, 0x00 }, + { "PORTA_DIRSET", 0x401, 0x00 }, + { "PORTA_DIRCLR", 0x402, 0x00 }, + { "PORTA_DIRTGL", 0x403, 0x00 }, + { "PORTA_OUT" , 0x404, 0x00 }, + { "PORTA_OUTSET", 0x405, 0x00 }, + { "PORTA_OUTCLR", 0x406, 0x00 }, + { "PORTA_OUTTGL", 0x407, 0x00 }, + { "PORTA_IN" , 0x408, 0x00 }, + { "PORTA_INTFLAGS", 0x409, 0x00 }, + { "PORTA_PORTCTRL", 0x40A, 0x00 }, + { "PORTA_PIN0CTRL", 0x410, 0x00 }, + { "PORTA_PIN1CTRL", 0x411, 0x00 }, + { "PORTA_PIN2CTRL", 0x412, 0x00 }, + { "PORTA_PIN3CTRL", 0x413, 0x00 }, + { "PORTA_PIN4CTRL", 0x414, 0x00 }, + { "PORTA_PIN5CTRL", 0x415, 0x00 }, + { "PORTA_PIN6CTRL", 0x416, 0x00 }, + { "PORTA_PIN7CTRL", 0x417, 0x00 }, + { "PORTB_DIR" , 0x420, 0x00 }, + { "PORTB_DIRSET", 0x421, 0x00 }, + { "PORTB_DIRCLR", 0x422, 0x00 }, + { "PORTB_DIRTGL", 0x423, 0x00 }, + { "PORTB_OUT" , 0x424, 0x00 }, + { "PORTB_OUTSET", 0x425, 0x00 }, + { "PORTB_OUTCLR", 0x426, 0x00 }, + { "PORTB_OUTTGL", 0x427, 0x00 }, + { "PORTB_IN" , 0x428, 0x00 }, + { "PORTB_INTFLAGS", 0x429, 0x00 }, + { "PORTB_PORTCTRL", 0x42A, 0x00 }, + { "PORTB_PIN0CTRL", 0x430, 0x00 }, + { "PORTB_PIN1CTRL", 0x431, 0x00 }, + { "PORTB_PIN2CTRL", 0x432, 0x00 }, + { "PORTB_PIN3CTRL", 0x433, 0x00 }, + { "PORTB_PIN4CTRL", 0x434, 0x00 }, + { "PORTB_PIN5CTRL", 0x435, 0x00 }, + { "PORTB_PIN6CTRL", 0x436, 0x00 }, + { "PORTB_PIN7CTRL", 0x437, 0x00 }, + { "PORTC_DIR" , 0x440, 0x00 }, + { "PORTC_DIRSET", 0x441, 0x00 }, + { "PORTC_DIRCLR", 0x442, 0x00 }, + { "PORTC_DIRTGL", 0x443, 0x00 }, + { "PORTC_OUT" , 0x444, 0x00 }, + { "PORTC_OUTSET", 0x445, 0x00 }, + { "PORTC_OUTCLR", 0x446, 0x00 }, + { "PORTC_OUTTGL", 0x447, 0x00 }, + { "PORTC_IN" , 0x448, 0x00 }, + { "PORTC_INTFLAGS", 0x449, 0x00 }, + { "PORTC_PORTCTRL", 0x44A, 0x00 }, + { "PORTC_PIN0CTRL", 0x450, 0x00 }, + { "PORTC_PIN1CTRL", 0x451, 0x00 }, + { "PORTC_PIN2CTRL", 0x452, 0x00 }, + { "PORTC_PIN3CTRL", 0x453, 0x00 }, + { "PORTC_PIN4CTRL", 0x454, 0x00 }, + { "PORTC_PIN5CTRL", 0x455, 0x00 }, + { "PORTC_PIN6CTRL", 0x456, 0x00 }, + { "PORTC_PIN7CTRL", 0x457, 0x00 }, + { "PORTD_DIR" , 0x460, 0x00 }, + { "PORTD_DIRSET", 0x461, 0x00 }, + { "PORTD_DIRCLR", 0x462, 0x00 }, + { "PORTD_DIRTGL", 0x463, 0x00 }, + { "PORTD_OUT" , 0x464, 0x00 }, + { "PORTD_OUTSET", 0x465, 0x00 }, + { "PORTD_OUTCLR", 0x466, 0x00 }, + { "PORTD_OUTTGL", 0x467, 0x00 }, + { "PORTD_IN" , 0x468, 0x00 }, + { "PORTD_INTFLAGS", 0x469, 0x00 }, + { "PORTD_PORTCTRL", 0x46A, 0x00 }, + { "PORTD_PIN0CTRL", 0x470, 0x00 }, + { "PORTD_PIN1CTRL", 0x471, 0x00 }, + { "PORTD_PIN2CTRL", 0x472, 0x00 }, + { "PORTD_PIN3CTRL", 0x473, 0x00 }, + { "PORTD_PIN4CTRL", 0x474, 0x00 }, + { "PORTD_PIN5CTRL", 0x475, 0x00 }, + { "PORTD_PIN6CTRL", 0x476, 0x00 }, + { "PORTD_PIN7CTRL", 0x477, 0x00 }, + { "PORTE_DIR" , 0x480, 0x00 }, + { "PORTE_DIRSET", 0x481, 0x00 }, + { "PORTE_DIRCLR", 0x482, 0x00 }, + { "PORTE_DIRTGL", 0x483, 0x00 }, + { "PORTE_OUT" , 0x484, 0x00 }, + { "PORTE_OUTSET", 0x485, 0x00 }, + { "PORTE_OUTCLR", 0x486, 0x00 }, + { "PORTE_OUTTGL", 0x487, 0x00 }, + { "PORTE_IN" , 0x488, 0x00 }, + { "PORTE_INTFLAGS", 0x489, 0x00 }, + { "PORTE_PORTCTRL", 0x48A, 0x00 }, + { "PORTE_PIN0CTRL", 0x490, 0x00 }, + { "PORTE_PIN1CTRL", 0x491, 0x00 }, + { "PORTE_PIN2CTRL", 0x492, 0x00 }, + { "PORTE_PIN3CTRL", 0x493, 0x00 }, + { "PORTE_PIN4CTRL", 0x494, 0x00 }, + { "PORTE_PIN5CTRL", 0x495, 0x00 }, + { "PORTE_PIN6CTRL", 0x496, 0x00 }, + { "PORTE_PIN7CTRL", 0x497, 0x00 }, + { "PORTF_DIR" , 0x4A0, 0x00 }, + { "PORTF_DIRSET", 0x4A1, 0x00 }, + { "PORTF_DIRCLR", 0x4A2, 0x00 }, + { "PORTF_DIRTGL", 0x4A3, 0x00 }, + { "PORTF_OUT" , 0x4A4, 0x00 }, + { "PORTF_OUTSET", 0x4A5, 0x00 }, + { "PORTF_OUTCLR", 0x4A6, 0x00 }, + { "PORTF_OUTTGL", 0x4A7, 0x00 }, + { "PORTF_IN" , 0x4A8, 0x00 }, + { "PORTF_INTFLAGS", 0x4A9, 0x00 }, + { "PORTF_PORTCTRL", 0x4AA, 0x00 }, + { "PORTF_PIN0CTRL", 0x4B0, 0x00 }, + { "PORTF_PIN1CTRL", 0x4B1, 0x00 }, + { "PORTF_PIN2CTRL", 0x4B2, 0x00 }, + { "PORTF_PIN3CTRL", 0x4B3, 0x00 }, + { "PORTF_PIN4CTRL", 0x4B4, 0x00 }, + { "PORTF_PIN5CTRL", 0x4B5, 0x00 }, + { "PORTF_PIN6CTRL", 0x4B6, 0x00 }, + { "PORTF_PIN7CTRL", 0x4B7, 0x00 }, + { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 }, + { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 }, + { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 }, + { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 }, + { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 }, + { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 }, + { "ADC0_CTRLA", 0x600, 0x00 }, + { "ADC0_CTRLB", 0x601, 0x00 }, + { "ADC0_CTRLC", 0x602, 0x00 }, + { "ADC0_CTRLD", 0x603, 0x00 }, + { "ADC0_CTRLE", 0x604, 0x00 }, + { "ADC0_SAMPCTRL", 0x605, 0x00 }, + { "ADC0_MUXPOS", 0x606, 0x00 }, + { "ADC0_COMMAND", 0x608, 0x00 }, + { "ADC0_EVCTRL", 0x609, 0x00 }, + { "ADC0_INTCTRL", 0x60A, 0x00 }, + { "ADC0_INTFLAGS", 0x60B, 0x00 }, + { "ADC0_DBGCTRL", 0x60C, 0x00 }, + { "ADC0_TEMP" , 0x60D, 0x00 }, + { "ADC0_RESL" , 0x610, 0x00 }, + { "ADC0_RESH" , 0x611, 0x00 }, + { "ADC0_WINLTL", 0x612, 0x00 }, + { "ADC0_WINLTH", 0x613, 0x00 }, + { "ADC0_WINHTL", 0x614, 0x00 }, + { "ADC0_WINHTH", 0x615, 0x00 }, + { "ADC0_CALIB", 0x616, 0x00 }, + { "AC0_CTRLA" , 0x680, 0x00 }, + { "AC0_MUXCTRLA", 0x682, 0x00 }, + { "AC0_DACREF", 0x684, 0x00 }, + { "AC0_INTCTRL", 0x686, 0x00 }, + { "AC0_STATUS", 0x687, 0x00 }, + { "USART0_RXDATAL", 0x800, 0x00 }, + { "USART0_RXDATAH", 0x801, 0x00 }, + { "USART0_TXDATAL", 0x802, 0x00 }, + { "USART0_TXDATAH", 0x803, 0x00 }, + { "USART0_STATUS", 0x804, 0x00 }, + { "USART0_CTRLA", 0x805, 0x00 }, + { "USART0_CTRLB", 0x806, 0x00 }, + { "USART0_CTRLC", 0x807, 0x00 }, + { "USART0_BAUDL", 0x808, 0x00 }, + { "USART0_BAUDH", 0x809, 0x00 }, + { "USART0_CTRLD", 0x80A, 0x00 }, + { "USART0_DBGCTRL", 0x80B, 0x00 }, + { "USART0_EVCTRL", 0x80C, 0x00 }, + { "USART0_TXPLCTRL", 0x80D, 0x00 }, + { "USART0_RXPLCTRL", 0x80E, 0x00 }, + { "USART1_RXDATAL", 0x820, 0x00 }, + { "USART1_RXDATAH", 0x821, 0x00 }, + { "USART1_TXDATAL", 0x822, 0x00 }, + { "USART1_TXDATAH", 0x823, 0x00 }, + { "USART1_STATUS", 0x824, 0x00 }, + { "USART1_CTRLA", 0x825, 0x00 }, + { "USART1_CTRLB", 0x826, 0x00 }, + { "USART1_CTRLC", 0x827, 0x00 }, + { "USART1_BAUDL", 0x828, 0x00 }, + { "USART1_BAUDH", 0x829, 0x00 }, + { "USART1_CTRLD", 0x82A, 0x00 }, + { "USART1_DBGCTRL", 0x82B, 0x00 }, + { "USART1_EVCTRL", 0x82C, 0x00 }, + { "USART1_TXPLCTRL", 0x82D, 0x00 }, + { "USART1_RXPLCTRL", 0x82E, 0x00 }, + { "USART2_RXDATAL", 0x840, 0x00 }, + { "USART2_RXDATAH", 0x841, 0x00 }, + { "USART2_TXDATAL", 0x842, 0x00 }, + { "USART2_TXDATAH", 0x843, 0x00 }, + { "USART2_STATUS", 0x844, 0x00 }, + { "USART2_CTRLA", 0x845, 0x00 }, + { "USART2_CTRLB", 0x846, 0x00 }, + { "USART2_CTRLC", 0x847, 0x00 }, + { "USART2_BAUDL", 0x848, 0x00 }, + { "USART2_BAUDH", 0x849, 0x00 }, + { "USART2_CTRLD", 0x84A, 0x00 }, + { "USART2_DBGCTRL", 0x84B, 0x00 }, + { "USART2_EVCTRL", 0x84C, 0x00 }, + { "USART2_TXPLCTRL", 0x84D, 0x00 }, + { "USART2_RXPLCTRL", 0x84E, 0x00 }, + { "TWI0_CTRLA", 0x8A0, 0x00 }, + { "TWI0_DUALCTRL", 0x8A1, 0x00 }, + { "TWI0_DBGCTRL", 0x8A2, 0x00 }, + { "TWI0_MCTRLA", 0x8A3, 0x00 }, + { "TWI0_MCTRLB", 0x8A4, 0x00 }, + { "TWI0_MSTATUS", 0x8A5, 0x00 }, + { "TWI0_MBAUD", 0x8A6, 0x00 }, + { "TWI0_MADDR", 0x8A7, 0x00 }, + { "TWI0_MDATA", 0x8A8, 0x00 }, + { "TWI0_SCTRLA", 0x8A9, 0x00 }, + { "TWI0_SCTRLB", 0x8AA, 0x00 }, + { "TWI0_SSTATUS", 0x8AB, 0x00 }, + { "TWI0_SADDR", 0x8AC, 0x00 }, + { "TWI0_SDATA", 0x8AD, 0x00 }, + { "TWI0_SADDRMASK", 0x8AE, 0x00 }, + { "SPI0_CTRLA", 0x8C0, 0x00 }, + { "SPI0_CTRLB", 0x8C1, 0x00 }, + { "SPI0_INTCTRL", 0x8C2, 0x00 }, + { "SPI0_INTFLAGS", 0x8C3, 0x00 }, + { "SPI0_DATA" , 0x8C4, 0x00 }, + { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 }, + { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 }, + { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 }, + { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 }, + { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 }, + { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 }, + { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 }, + { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 }, + { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 }, + { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 }, + { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 }, + { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 }, + { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 }, + { "TCA0_SPLIT_LCNT", 0xA20, 0x00 }, + { "TCA0_SPLIT_HCNT", 0xA21, 0x00 }, + { "TCA0_SPLIT_LPER", 0xA26, 0x00 }, + { "TCA0_SPLIT_HPER", 0xA27, 0x00 }, + { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 }, + { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 }, + { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 }, + { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 }, + { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 }, + { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 }, + { "TCB0_CTRLA", 0xA80, 0x00 }, + { "TCB0_CTRLB", 0xA81, 0x00 }, + { "TCB0_EVCTRL", 0xA84, 0x00 }, + { "TCB0_INTCTRL", 0xA85, 0x00 }, + { "TCB0_INTFLAGS", 0xA86, 0x00 }, + { "TCB0_STATUS", 0xA87, 0x00 }, + { "TCB0_DBGCTRL", 0xA88, 0x00 }, + { "TCB0_TEMP" , 0xA89, 0x00 }, + { "TCB0_CNTL" , 0xA8A, 0x00 }, + { "TCB0_CNTH" , 0xA8B, 0x00 }, + { "TCB0_CCMPL", 0xA8C, 0x00 }, + { "TCB0_CCMPH", 0xA8D, 0x00 }, + { "TCB1_CTRLA", 0xA90, 0x00 }, + { "TCB1_CTRLB", 0xA91, 0x00 }, + { "TCB1_EVCTRL", 0xA94, 0x00 }, + { "TCB1_INTCTRL", 0xA95, 0x00 }, + { "TCB1_INTFLAGS", 0xA96, 0x00 }, + { "TCB1_STATUS", 0xA97, 0x00 }, + { "TCB1_DBGCTRL", 0xA98, 0x00 }, + { "TCB1_TEMP" , 0xA99, 0x00 }, + { "TCB1_CNTL" , 0xA9A, 0x00 }, + { "TCB1_CNTH" , 0xA9B, 0x00 }, + { "TCB1_CCMPL", 0xA9C, 0x00 }, + { "TCB1_CCMPH", 0xA9D, 0x00 }, + { "TCB2_CTRLA", 0xAA0, 0x00 }, + { "TCB2_CTRLB", 0xAA1, 0x00 }, + { "TCB2_EVCTRL", 0xAA4, 0x00 }, + { "TCB2_INTCTRL", 0xAA5, 0x00 }, + { "TCB2_INTFLAGS", 0xAA6, 0x00 }, + { "TCB2_STATUS", 0xAA7, 0x00 }, + { "TCB2_DBGCTRL", 0xAA8, 0x00 }, + { "TCB2_TEMP" , 0xAA9, 0x00 }, + { "TCB2_CNTL" , 0xAAA, 0x00 }, + { "TCB2_CNTH" , 0xAAB, 0x00 }, + { "TCB2_CCMPL", 0xAAC, 0x00 }, + { "TCB2_CCMPH", 0xAAD, 0x00 }, + { "SYSCFG_REVID", 0xF01, 0x00 }, + { "SYSCFG_EXTBRK", 0xF02, 0x00 }, + { "SYSCFG_OCDM", 0xF18, 0x00 }, + { "SYSCFG_OCDMS", 0xF19, 0x00 }, + { "NVMCTRL_CTRLA", 0x1000, 0x00 }, + { "NVMCTRL_CTRLB", 0x1001, 0x00 }, + { "NVMCTRL_STATUS", 0x1002, 0x00 }, + { "NVMCTRL_INTCTRL", 0x1003, 0x00 }, + { "NVMCTRL_INTFLAGS", 0x1004, 0x00 }, + { "NVMCTRL_DATAL", 0x1006, 0x00 }, + { "NVMCTRL_DATAH", 0x1007, 0x00 }, + { "NVMCTRL_ADDRL", 0x1008, 0x00 }, + { "NVMCTRL_ADDRH", 0x1009, 0x00 }, + { "SIGROW_DEVICEID0", 0x1100, 0x00 }, + { "SIGROW_DEVICEID1", 0x1101, 0x00 }, + { "SIGROW_DEVICEID2", 0x1102, 0x00 }, + { "SIGROW_SERNUM0", 0x1103, 0x00 }, + { "SIGROW_SERNUM1", 0x1104, 0x00 }, + { "SIGROW_SERNUM2", 0x1105, 0x00 }, + { "SIGROW_SERNUM3", 0x1106, 0x00 }, + { "SIGROW_SERNUM4", 0x1107, 0x00 }, + { "SIGROW_SERNUM5", 0x1108, 0x00 }, + { "SIGROW_SERNUM6", 0x1109, 0x00 }, + { "SIGROW_SERNUM7", 0x110A, 0x00 }, + { "SIGROW_SERNUM8", 0x110B, 0x00 }, + { "SIGROW_SERNUM9", 0x110C, 0x00 }, + { "SIGROW_OSCCAL32K", 0x1114, 0x00 }, + { "SIGROW_OSCCAL16M0", 0x1118, 0x00 }, + { "SIGROW_OSCCAL16M1", 0x1119, 0x00 }, + { "SIGROW_OSCCAL20M0", 0x111A, 0x00 }, + { "SIGROW_OSCCAL20M1", 0x111B, 0x00 }, + { "SIGROW_TEMPSENSE0", 0x1120, 0x00 }, + { "SIGROW_TEMPSENSE1", 0x1121, 0x00 }, + { "SIGROW_OSC16ERR3V", 0x1122, 0x00 }, + { "SIGROW_OSC16ERR5V", 0x1123, 0x00 }, + { "SIGROW_OSC20ERR3V", 0x1124, 0x00 }, + { "SIGROW_OSC20ERR5V", 0x1125, 0x00 }, + { "SIGROW_CHECKSUM1", 0x112F, 0x00 }, + { "FUSE_WDTCFG", 0x1280, 0x00 }, + { "FUSE_BODCFG", 0x1281, 0x00 }, + { "FUSE_OSCCFG", 0x1282, 0x00 }, + { "FUSE_SYSCFG0", 0x1285, 0x00 }, + { "FUSE_SYSCFG1", 0x1286, 0x00 }, + { "FUSE_APPEND", 0x1287, 0x00 }, + { "FUSE_BOOTEND", 0x1288, 0x00 }, + { "LOCKBIT_LOCKBIT", 0x128A, 0x00 }, + { "USERROW_USERROW0", 0x1300, 0x00 }, + { "USERROW_USERROW1", 0x1301, 0x00 }, + { "USERROW_USERROW2", 0x1302, 0x00 }, + { "USERROW_USERROW3", 0x1303, 0x00 }, + { "USERROW_USERROW4", 0x1304, 0x00 }, + { "USERROW_USERROW5", 0x1305, 0x00 }, + { "USERROW_USERROW6", 0x1306, 0x00 }, + { "USERROW_USERROW7", 0x1307, 0x00 }, + { "USERROW_USERROW8", 0x1308, 0x00 }, + { "USERROW_USERROW9", 0x1309, 0x00 }, + { "USERROW_USERROW10", 0x130A, 0x00 }, + { "USERROW_USERROW11", 0x130B, 0x00 }, + { "USERROW_USERROW12", 0x130C, 0x00 }, + { "USERROW_USERROW13", 0x130D, 0x00 }, + { "USERROW_USERROW14", 0x130E, 0x00 }, + { "USERROW_USERROW15", 0x130F, 0x00 }, + { "USERROW_USERROW16", 0x1310, 0x00 }, + { "USERROW_USERROW17", 0x1311, 0x00 }, + { "USERROW_USERROW18", 0x1312, 0x00 }, + { "USERROW_USERROW19", 0x1313, 0x00 }, + { "USERROW_USERROW20", 0x1314, 0x00 }, + { "USERROW_USERROW21", 0x1315, 0x00 }, + { "USERROW_USERROW22", 0x1316, 0x00 }, + { "USERROW_USERROW23", 0x1317, 0x00 }, + { "USERROW_USERROW24", 0x1318, 0x00 }, + { "USERROW_USERROW25", 0x1319, 0x00 }, + { "USERROW_USERROW26", 0x131A, 0x00 }, + { "USERROW_USERROW27", 0x131B, 0x00 }, + { "USERROW_USERROW28", 0x131C, 0x00 }, + { "USERROW_USERROW29", 0x131D, 0x00 }, + { "USERROW_USERROW30", 0x131E, 0x00 }, + { "USERROW_USERROW31", 0x131F, 0x00 }, + { "USERROW_USERROW32", 0x1320, 0x00 }, + { "USERROW_USERROW33", 0x1321, 0x00 }, + { "USERROW_USERROW34", 0x1322, 0x00 }, + { "USERROW_USERROW35", 0x1323, 0x00 }, + { "USERROW_USERROW36", 0x1324, 0x00 }, + { "USERROW_USERROW37", 0x1325, 0x00 }, + { "USERROW_USERROW38", 0x1326, 0x00 }, + { "USERROW_USERROW39", 0x1327, 0x00 }, + { "USERROW_USERROW40", 0x1328, 0x00 }, + { "USERROW_USERROW41", 0x1329, 0x00 }, + { "USERROW_USERROW42", 0x132A, 0x00 }, + { "USERROW_USERROW43", 0x132B, 0x00 }, + { "USERROW_USERROW44", 0x132C, 0x00 }, + { "USERROW_USERROW45", 0x132D, 0x00 }, + { "USERROW_USERROW46", 0x132E, 0x00 }, + { "USERROW_USERROW47", 0x132F, 0x00 }, + { "USERROW_USERROW48", 0x1330, 0x00 }, + { "USERROW_USERROW49", 0x1331, 0x00 }, + { "USERROW_USERROW50", 0x1332, 0x00 }, + { "USERROW_USERROW51", 0x1333, 0x00 }, + { "USERROW_USERROW52", 0x1334, 0x00 }, + { "USERROW_USERROW53", 0x1335, 0x00 }, + { "USERROW_USERROW54", 0x1336, 0x00 }, + { "USERROW_USERROW55", 0x1337, 0x00 }, + { "USERROW_USERROW56", 0x1338, 0x00 }, + { "USERROW_USERROW57", 0x1339, 0x00 }, + { "USERROW_USERROW58", 0x133A, 0x00 }, + { "USERROW_USERROW59", 0x133B, 0x00 }, + { "USERROW_USERROW60", 0x133C, 0x00 }, + { "USERROW_USERROW61", 0x133D, 0x00 }, + { "USERROW_USERROW62", 0x133E, 0x00 }, + { "USERROW_USERROW63", 0x133F, 0x00 }, + { 0, 0, 0} +}; + + +gdb_io_reg_def_type atmega4809_io_registers[] = +{ + { "VPORTA_DIR", 0x0, 0x00 }, + { "VPORTA_OUT", 0x1, 0x00 }, + { "VPORTA_IN" , 0x2, 0x00 }, + { "VPORTA_INTFLAGS", 0x3, 0x00 }, + { "VPORTB_DIR", 0x4, 0x00 }, + { "VPORTB_OUT", 0x5, 0x00 }, + { "VPORTB_IN" , 0x6, 0x00 }, + { "VPORTB_INTFLAGS", 0x7, 0x00 }, + { "VPORTC_DIR", 0x8, 0x00 }, + { "VPORTC_OUT", 0x9, 0x00 }, + { "VPORTC_IN" , 0xA, 0x00 }, + { "VPORTC_INTFLAGS", 0xB, 0x00 }, + { "VPORTD_DIR", 0xC, 0x00 }, + { "VPORTD_OUT", 0xD, 0x00 }, + { "VPORTD_IN" , 0xE, 0x00 }, + { "VPORTD_INTFLAGS", 0xF, 0x00 }, + { "VPORTE_DIR", 0x10, 0x00 }, + { "VPORTE_OUT", 0x11, 0x00 }, + { "VPORTE_IN" , 0x12, 0x00 }, + { "VPORTE_INTFLAGS", 0x13, 0x00 }, + { "VPORTF_DIR", 0x14, 0x00 }, + { "VPORTF_OUT", 0x15, 0x00 }, + { "VPORTF_IN" , 0x16, 0x00 }, + { "VPORTF_INTFLAGS", 0x17, 0x00 }, + { "GPIO_GPIO0", 0x1C, 0x00 }, + { "GPIO_GPIO1", 0x1D, 0x00 }, + { "GPIO_GPIO2", 0x1E, 0x00 }, + { "GPIO_GPIO3", 0x1F, 0x00 }, + { "CPU_CCP" , 0x34, 0x00 }, + { "CPU_SPL" , 0x3D, 0x00 }, + { "CPU_SPH" , 0x3E, 0x00 }, + { "CPU_SREG" , 0x3F, 0x00 }, + { "RSTCTRL_RSTFR", 0x40, 0x00 }, + { "RSTCTRL_SWRR", 0x41, 0x00 }, + { "SLPCTRL_CTRLA", 0x50, 0x00 }, + { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 }, + { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 }, + { "CLKCTRL_MCLKLOCK", 0x62, 0x00 }, + { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 }, + { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 }, + { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 }, + { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 }, + { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 }, + { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 }, + { "BOD_CTRLA" , 0x80, 0x00 }, + { "BOD_CTRLB" , 0x81, 0x00 }, + { "BOD_VLMCTRLA", 0x88, 0x00 }, + { "BOD_INTCTRL", 0x89, 0x00 }, + { "BOD_INTFLAGS", 0x8A, 0x00 }, + { "BOD_STATUS", 0x8B, 0x00 }, + { "VREF_CTRLA", 0xA0, 0x00 }, + { "VREF_CTRLB", 0xA1, 0x00 }, + { "WDT_CTRLA" , 0x100, 0x00 }, + { "WDT_STATUS", 0x101, 0x00 }, + { "CPUINT_CTRLA", 0x110, 0x00 }, + { "CPUINT_STATUS", 0x111, 0x00 }, + { "CPUINT_LVL0PRI", 0x112, 0x00 }, + { "CPUINT_LVL1VEC", 0x113, 0x00 }, + { "CRCSCAN_CTRLA", 0x120, 0x00 }, + { "CRCSCAN_CTRLB", 0x121, 0x00 }, + { "CRCSCAN_STATUS", 0x122, 0x00 }, + { "RTC_CTRLA" , 0x140, 0x00 }, + { "RTC_STATUS", 0x141, 0x00 }, + { "RTC_INTCTRL", 0x142, 0x00 }, + { "RTC_INTFLAGS", 0x143, 0x00 }, + { "RTC_TEMP" , 0x144, 0x00 }, + { "RTC_DBGCTRL", 0x145, 0x00 }, + { "RTC_CALIB" , 0x146, 0x00 }, + { "RTC_CLKSEL", 0x147, 0x00 }, + { "RTC_CNTL" , 0x148, 0x00 }, + { "RTC_CNTH" , 0x149, 0x00 }, + { "RTC_PERL" , 0x14A, 0x00 }, + { "RTC_PERH" , 0x14B, 0x00 }, + { "RTC_CMPL" , 0x14C, 0x00 }, + { "RTC_CMPH" , 0x14D, 0x00 }, + { "RTC_PITCTRLA", 0x150, 0x00 }, + { "RTC_PITSTATUS", 0x151, 0x00 }, + { "RTC_PITINTCTRL", 0x152, 0x00 }, + { "RTC_PITINTFLAGS", 0x153, 0x00 }, + { "RTC_PITDBGCTRL", 0x155, 0x00 }, + { "EVSYS_STROBE", 0x180, 0x00 }, + { "EVSYS_CHANNEL0", 0x190, 0x00 }, + { "EVSYS_CHANNEL1", 0x191, 0x00 }, + { "EVSYS_CHANNEL2", 0x192, 0x00 }, + { "EVSYS_CHANNEL3", 0x193, 0x00 }, + { "EVSYS_CHANNEL4", 0x194, 0x00 }, + { "EVSYS_CHANNEL5", 0x195, 0x00 }, + { "EVSYS_CHANNEL6", 0x196, 0x00 }, + { "EVSYS_CHANNEL7", 0x197, 0x00 }, + { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 }, + { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 }, + { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 }, + { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 }, + { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 }, + { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 }, + { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 }, + { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 }, + { "EVSYS_USERADC0", 0x1A8, 0x00 }, + { "EVSYS_USEREVOUTA", 0x1A9, 0x00 }, + { "EVSYS_USEREVOUTB", 0x1AA, 0x00 }, + { "EVSYS_USEREVOUTC", 0x1AB, 0x00 }, + { "EVSYS_USEREVOUTD", 0x1AC, 0x00 }, + { "EVSYS_USEREVOUTE", 0x1AD, 0x00 }, + { "EVSYS_USEREVOUTF", 0x1AE, 0x00 }, + { "EVSYS_USERUSART0", 0x1AF, 0x00 }, + { "EVSYS_USERUSART1", 0x1B0, 0x00 }, + { "EVSYS_USERUSART2", 0x1B1, 0x00 }, + { "EVSYS_USERUSART3", 0x1B2, 0x00 }, + { "EVSYS_USERTCA0", 0x1B3, 0x00 }, + { "EVSYS_USERTCB0", 0x1B4, 0x00 }, + { "EVSYS_USERTCB1", 0x1B5, 0x00 }, + { "EVSYS_USERTCB2", 0x1B6, 0x00 }, + { "EVSYS_USERTCB3", 0x1B7, 0x00 }, + { "CCL_CTRLA" , 0x1C0, 0x00 }, + { "CCL_SEQCTRL0", 0x1C1, 0x00 }, + { "CCL_SEQCTRL1", 0x1C2, 0x00 }, + { "CCL_INTCTRL0", 0x1C5, 0x00 }, + { "CCL_INTFLAGS", 0x1C7, 0x00 }, + { "CCL_LUT0CTRLA", 0x1C8, 0x00 }, + { "CCL_LUT0CTRLB", 0x1C9, 0x00 }, + { "CCL_LUT0CTRLC", 0x1CA, 0x00 }, + { "CCL_TRUTH0", 0x1CB, 0x00 }, + { "CCL_LUT1CTRLA", 0x1CC, 0x00 }, + { "CCL_LUT1CTRLB", 0x1CD, 0x00 }, + { "CCL_LUT1CTRLC", 0x1CE, 0x00 }, + { "CCL_TRUTH1", 0x1CF, 0x00 }, + { "CCL_LUT2CTRLA", 0x1D0, 0x00 }, + { "CCL_LUT2CTRLB", 0x1D1, 0x00 }, + { "CCL_LUT2CTRLC", 0x1D2, 0x00 }, + { "CCL_TRUTH2", 0x1D3, 0x00 }, + { "CCL_LUT3CTRLA", 0x1D4, 0x00 }, + { "CCL_LUT3CTRLB", 0x1D5, 0x00 }, + { "CCL_LUT3CTRLC", 0x1D6, 0x00 }, + { "CCL_TRUTH3", 0x1D7, 0x00 }, + { "PORTA_DIR" , 0x400, 0x00 }, + { "PORTA_DIRSET", 0x401, 0x00 }, + { "PORTA_DIRCLR", 0x402, 0x00 }, + { "PORTA_DIRTGL", 0x403, 0x00 }, + { "PORTA_OUT" , 0x404, 0x00 }, + { "PORTA_OUTSET", 0x405, 0x00 }, + { "PORTA_OUTCLR", 0x406, 0x00 }, + { "PORTA_OUTTGL", 0x407, 0x00 }, + { "PORTA_IN" , 0x408, 0x00 }, + { "PORTA_INTFLAGS", 0x409, 0x00 }, + { "PORTA_PORTCTRL", 0x40A, 0x00 }, + { "PORTA_PIN0CTRL", 0x410, 0x00 }, + { "PORTA_PIN1CTRL", 0x411, 0x00 }, + { "PORTA_PIN2CTRL", 0x412, 0x00 }, + { "PORTA_PIN3CTRL", 0x413, 0x00 }, + { "PORTA_PIN4CTRL", 0x414, 0x00 }, + { "PORTA_PIN5CTRL", 0x415, 0x00 }, + { "PORTA_PIN6CTRL", 0x416, 0x00 }, + { "PORTA_PIN7CTRL", 0x417, 0x00 }, + { "PORTB_DIR" , 0x420, 0x00 }, + { "PORTB_DIRSET", 0x421, 0x00 }, + { "PORTB_DIRCLR", 0x422, 0x00 }, + { "PORTB_DIRTGL", 0x423, 0x00 }, + { "PORTB_OUT" , 0x424, 0x00 }, + { "PORTB_OUTSET", 0x425, 0x00 }, + { "PORTB_OUTCLR", 0x426, 0x00 }, + { "PORTB_OUTTGL", 0x427, 0x00 }, + { "PORTB_IN" , 0x428, 0x00 }, + { "PORTB_INTFLAGS", 0x429, 0x00 }, + { "PORTB_PORTCTRL", 0x42A, 0x00 }, + { "PORTB_PIN0CTRL", 0x430, 0x00 }, + { "PORTB_PIN1CTRL", 0x431, 0x00 }, + { "PORTB_PIN2CTRL", 0x432, 0x00 }, + { "PORTB_PIN3CTRL", 0x433, 0x00 }, + { "PORTB_PIN4CTRL", 0x434, 0x00 }, + { "PORTB_PIN5CTRL", 0x435, 0x00 }, + { "PORTB_PIN6CTRL", 0x436, 0x00 }, + { "PORTB_PIN7CTRL", 0x437, 0x00 }, + { "PORTC_DIR" , 0x440, 0x00 }, + { "PORTC_DIRSET", 0x441, 0x00 }, + { "PORTC_DIRCLR", 0x442, 0x00 }, + { "PORTC_DIRTGL", 0x443, 0x00 }, + { "PORTC_OUT" , 0x444, 0x00 }, + { "PORTC_OUTSET", 0x445, 0x00 }, + { "PORTC_OUTCLR", 0x446, 0x00 }, + { "PORTC_OUTTGL", 0x447, 0x00 }, + { "PORTC_IN" , 0x448, 0x00 }, + { "PORTC_INTFLAGS", 0x449, 0x00 }, + { "PORTC_PORTCTRL", 0x44A, 0x00 }, + { "PORTC_PIN0CTRL", 0x450, 0x00 }, + { "PORTC_PIN1CTRL", 0x451, 0x00 }, + { "PORTC_PIN2CTRL", 0x452, 0x00 }, + { "PORTC_PIN3CTRL", 0x453, 0x00 }, + { "PORTC_PIN4CTRL", 0x454, 0x00 }, + { "PORTC_PIN5CTRL", 0x455, 0x00 }, + { "PORTC_PIN6CTRL", 0x456, 0x00 }, + { "PORTC_PIN7CTRL", 0x457, 0x00 }, + { "PORTD_DIR" , 0x460, 0x00 }, + { "PORTD_DIRSET", 0x461, 0x00 }, + { "PORTD_DIRCLR", 0x462, 0x00 }, + { "PORTD_DIRTGL", 0x463, 0x00 }, + { "PORTD_OUT" , 0x464, 0x00 }, + { "PORTD_OUTSET", 0x465, 0x00 }, + { "PORTD_OUTCLR", 0x466, 0x00 }, + { "PORTD_OUTTGL", 0x467, 0x00 }, + { "PORTD_IN" , 0x468, 0x00 }, + { "PORTD_INTFLAGS", 0x469, 0x00 }, + { "PORTD_PORTCTRL", 0x46A, 0x00 }, + { "PORTD_PIN0CTRL", 0x470, 0x00 }, + { "PORTD_PIN1CTRL", 0x471, 0x00 }, + { "PORTD_PIN2CTRL", 0x472, 0x00 }, + { "PORTD_PIN3CTRL", 0x473, 0x00 }, + { "PORTD_PIN4CTRL", 0x474, 0x00 }, + { "PORTD_PIN5CTRL", 0x475, 0x00 }, + { "PORTD_PIN6CTRL", 0x476, 0x00 }, + { "PORTD_PIN7CTRL", 0x477, 0x00 }, + { "PORTE_DIR" , 0x480, 0x00 }, + { "PORTE_DIRSET", 0x481, 0x00 }, + { "PORTE_DIRCLR", 0x482, 0x00 }, + { "PORTE_DIRTGL", 0x483, 0x00 }, + { "PORTE_OUT" , 0x484, 0x00 }, + { "PORTE_OUTSET", 0x485, 0x00 }, + { "PORTE_OUTCLR", 0x486, 0x00 }, + { "PORTE_OUTTGL", 0x487, 0x00 }, + { "PORTE_IN" , 0x488, 0x00 }, + { "PORTE_INTFLAGS", 0x489, 0x00 }, + { "PORTE_PORTCTRL", 0x48A, 0x00 }, + { "PORTE_PIN0CTRL", 0x490, 0x00 }, + { "PORTE_PIN1CTRL", 0x491, 0x00 }, + { "PORTE_PIN2CTRL", 0x492, 0x00 }, + { "PORTE_PIN3CTRL", 0x493, 0x00 }, + { "PORTE_PIN4CTRL", 0x494, 0x00 }, + { "PORTE_PIN5CTRL", 0x495, 0x00 }, + { "PORTE_PIN6CTRL", 0x496, 0x00 }, + { "PORTE_PIN7CTRL", 0x497, 0x00 }, + { "PORTF_DIR" , 0x4A0, 0x00 }, + { "PORTF_DIRSET", 0x4A1, 0x00 }, + { "PORTF_DIRCLR", 0x4A2, 0x00 }, + { "PORTF_DIRTGL", 0x4A3, 0x00 }, + { "PORTF_OUT" , 0x4A4, 0x00 }, + { "PORTF_OUTSET", 0x4A5, 0x00 }, + { "PORTF_OUTCLR", 0x4A6, 0x00 }, + { "PORTF_OUTTGL", 0x4A7, 0x00 }, + { "PORTF_IN" , 0x4A8, 0x00 }, + { "PORTF_INTFLAGS", 0x4A9, 0x00 }, + { "PORTF_PORTCTRL", 0x4AA, 0x00 }, + { "PORTF_PIN0CTRL", 0x4B0, 0x00 }, + { "PORTF_PIN1CTRL", 0x4B1, 0x00 }, + { "PORTF_PIN2CTRL", 0x4B2, 0x00 }, + { "PORTF_PIN3CTRL", 0x4B3, 0x00 }, + { "PORTF_PIN4CTRL", 0x4B4, 0x00 }, + { "PORTF_PIN5CTRL", 0x4B5, 0x00 }, + { "PORTF_PIN6CTRL", 0x4B6, 0x00 }, + { "PORTF_PIN7CTRL", 0x4B7, 0x00 }, + { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 }, + { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 }, + { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 }, + { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 }, + { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 }, + { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 }, + { "ADC0_CTRLA", 0x600, 0x00 }, + { "ADC0_CTRLB", 0x601, 0x00 }, + { "ADC0_CTRLC", 0x602, 0x00 }, + { "ADC0_CTRLD", 0x603, 0x00 }, + { "ADC0_CTRLE", 0x604, 0x00 }, + { "ADC0_SAMPCTRL", 0x605, 0x00 }, + { "ADC0_MUXPOS", 0x606, 0x00 }, + { "ADC0_COMMAND", 0x608, 0x00 }, + { "ADC0_EVCTRL", 0x609, 0x00 }, + { "ADC0_INTCTRL", 0x60A, 0x00 }, + { "ADC0_INTFLAGS", 0x60B, 0x00 }, + { "ADC0_DBGCTRL", 0x60C, 0x00 }, + { "ADC0_TEMP" , 0x60D, 0x00 }, + { "ADC0_RESL" , 0x610, 0x00 }, + { "ADC0_RESH" , 0x611, 0x00 }, + { "ADC0_WINLTL", 0x612, 0x00 }, + { "ADC0_WINLTH", 0x613, 0x00 }, + { "ADC0_WINHTL", 0x614, 0x00 }, + { "ADC0_WINHTH", 0x615, 0x00 }, + { "ADC0_CALIB", 0x616, 0x00 }, + { "AC0_CTRLA" , 0x680, 0x00 }, + { "AC0_MUXCTRLA", 0x682, 0x00 }, + { "AC0_DACREF", 0x684, 0x00 }, + { "AC0_INTCTRL", 0x686, 0x00 }, + { "AC0_STATUS", 0x687, 0x00 }, + { "USART0_RXDATAL", 0x800, 0x00 }, + { "USART0_RXDATAH", 0x801, 0x00 }, + { "USART0_TXDATAL", 0x802, 0x00 }, + { "USART0_TXDATAH", 0x803, 0x00 }, + { "USART0_STATUS", 0x804, 0x00 }, + { "USART0_CTRLA", 0x805, 0x00 }, + { "USART0_CTRLB", 0x806, 0x00 }, + { "USART0_CTRLC", 0x807, 0x00 }, + { "USART0_BAUDL", 0x808, 0x00 }, + { "USART0_BAUDH", 0x809, 0x00 }, + { "USART0_CTRLD", 0x80A, 0x00 }, + { "USART0_DBGCTRL", 0x80B, 0x00 }, + { "USART0_EVCTRL", 0x80C, 0x00 }, + { "USART0_TXPLCTRL", 0x80D, 0x00 }, + { "USART0_RXPLCTRL", 0x80E, 0x00 }, + { "USART1_RXDATAL", 0x820, 0x00 }, + { "USART1_RXDATAH", 0x821, 0x00 }, + { "USART1_TXDATAL", 0x822, 0x00 }, + { "USART1_TXDATAH", 0x823, 0x00 }, + { "USART1_STATUS", 0x824, 0x00 }, + { "USART1_CTRLA", 0x825, 0x00 }, + { "USART1_CTRLB", 0x826, 0x00 }, + { "USART1_CTRLC", 0x827, 0x00 }, + { "USART1_BAUDL", 0x828, 0x00 }, + { "USART1_BAUDH", 0x829, 0x00 }, + { "USART1_CTRLD", 0x82A, 0x00 }, + { "USART1_DBGCTRL", 0x82B, 0x00 }, + { "USART1_EVCTRL", 0x82C, 0x00 }, + { "USART1_TXPLCTRL", 0x82D, 0x00 }, + { "USART1_RXPLCTRL", 0x82E, 0x00 }, + { "USART2_RXDATAL", 0x840, 0x00 }, + { "USART2_RXDATAH", 0x841, 0x00 }, + { "USART2_TXDATAL", 0x842, 0x00 }, + { "USART2_TXDATAH", 0x843, 0x00 }, + { "USART2_STATUS", 0x844, 0x00 }, + { "USART2_CTRLA", 0x845, 0x00 }, + { "USART2_CTRLB", 0x846, 0x00 }, + { "USART2_CTRLC", 0x847, 0x00 }, + { "USART2_BAUDL", 0x848, 0x00 }, + { "USART2_BAUDH", 0x849, 0x00 }, + { "USART2_CTRLD", 0x84A, 0x00 }, + { "USART2_DBGCTRL", 0x84B, 0x00 }, + { "USART2_EVCTRL", 0x84C, 0x00 }, + { "USART2_TXPLCTRL", 0x84D, 0x00 }, + { "USART2_RXPLCTRL", 0x84E, 0x00 }, + { "USART3_RXDATAL", 0x860, 0x00 }, + { "USART3_RXDATAH", 0x861, 0x00 }, + { "USART3_TXDATAL", 0x862, 0x00 }, + { "USART3_TXDATAH", 0x863, 0x00 }, + { "USART3_STATUS", 0x864, 0x00 }, + { "USART3_CTRLA", 0x865, 0x00 }, + { "USART3_CTRLB", 0x866, 0x00 }, + { "USART3_CTRLC", 0x867, 0x00 }, + { "USART3_BAUDL", 0x868, 0x00 }, + { "USART3_BAUDH", 0x869, 0x00 }, + { "USART3_CTRLD", 0x86A, 0x00 }, + { "USART3_DBGCTRL", 0x86B, 0x00 }, + { "USART3_EVCTRL", 0x86C, 0x00 }, + { "USART3_TXPLCTRL", 0x86D, 0x00 }, + { "USART3_RXPLCTRL", 0x86E, 0x00 }, + { "TWI0_CTRLA", 0x8A0, 0x00 }, + { "TWI0_DUALCTRL", 0x8A1, 0x00 }, + { "TWI0_DBGCTRL", 0x8A2, 0x00 }, + { "TWI0_MCTRLA", 0x8A3, 0x00 }, + { "TWI0_MCTRLB", 0x8A4, 0x00 }, + { "TWI0_MSTATUS", 0x8A5, 0x00 }, + { "TWI0_MBAUD", 0x8A6, 0x00 }, + { "TWI0_MADDR", 0x8A7, 0x00 }, + { "TWI0_MDATA", 0x8A8, 0x00 }, + { "TWI0_SCTRLA", 0x8A9, 0x00 }, + { "TWI0_SCTRLB", 0x8AA, 0x00 }, + { "TWI0_SSTATUS", 0x8AB, 0x00 }, + { "TWI0_SADDR", 0x8AC, 0x00 }, + { "TWI0_SDATA", 0x8AD, 0x00 }, + { "TWI0_SADDRMASK", 0x8AE, 0x00 }, + { "SPI0_CTRLA", 0x8C0, 0x00 }, + { "SPI0_CTRLB", 0x8C1, 0x00 }, + { "SPI0_INTCTRL", 0x8C2, 0x00 }, + { "SPI0_INTFLAGS", 0x8C3, 0x00 }, + { "SPI0_DATA" , 0x8C4, 0x00 }, + { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 }, + { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 }, + { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 }, + { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 }, + { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 }, + { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 }, + { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 }, + { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 }, + { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 }, + { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 }, + { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 }, + { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 }, + { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 }, + { "TCA0_SPLIT_LCNT", 0xA20, 0x00 }, + { "TCA0_SPLIT_HCNT", 0xA21, 0x00 }, + { "TCA0_SPLIT_LPER", 0xA26, 0x00 }, + { "TCA0_SPLIT_HPER", 0xA27, 0x00 }, + { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 }, + { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 }, + { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 }, + { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 }, + { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 }, + { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 }, + { "TCB0_CTRLA", 0xA80, 0x00 }, + { "TCB0_CTRLB", 0xA81, 0x00 }, + { "TCB0_EVCTRL", 0xA84, 0x00 }, + { "TCB0_INTCTRL", 0xA85, 0x00 }, + { "TCB0_INTFLAGS", 0xA86, 0x00 }, + { "TCB0_STATUS", 0xA87, 0x00 }, + { "TCB0_DBGCTRL", 0xA88, 0x00 }, + { "TCB0_TEMP" , 0xA89, 0x00 }, + { "TCB0_CNTL" , 0xA8A, 0x00 }, + { "TCB0_CNTH" , 0xA8B, 0x00 }, + { "TCB0_CCMPL", 0xA8C, 0x00 }, + { "TCB0_CCMPH", 0xA8D, 0x00 }, + { "TCB1_CTRLA", 0xA90, 0x00 }, + { "TCB1_CTRLB", 0xA91, 0x00 }, + { "TCB1_EVCTRL", 0xA94, 0x00 }, + { "TCB1_INTCTRL", 0xA95, 0x00 }, + { "TCB1_INTFLAGS", 0xA96, 0x00 }, + { "TCB1_STATUS", 0xA97, 0x00 }, + { "TCB1_DBGCTRL", 0xA98, 0x00 }, + { "TCB1_TEMP" , 0xA99, 0x00 }, + { "TCB1_CNTL" , 0xA9A, 0x00 }, + { "TCB1_CNTH" , 0xA9B, 0x00 }, + { "TCB1_CCMPL", 0xA9C, 0x00 }, + { "TCB1_CCMPH", 0xA9D, 0x00 }, + { "TCB2_CTRLA", 0xAA0, 0x00 }, + { "TCB2_CTRLB", 0xAA1, 0x00 }, + { "TCB2_EVCTRL", 0xAA4, 0x00 }, + { "TCB2_INTCTRL", 0xAA5, 0x00 }, + { "TCB2_INTFLAGS", 0xAA6, 0x00 }, + { "TCB2_STATUS", 0xAA7, 0x00 }, + { "TCB2_DBGCTRL", 0xAA8, 0x00 }, + { "TCB2_TEMP" , 0xAA9, 0x00 }, + { "TCB2_CNTL" , 0xAAA, 0x00 }, + { "TCB2_CNTH" , 0xAAB, 0x00 }, + { "TCB2_CCMPL", 0xAAC, 0x00 }, + { "TCB2_CCMPH", 0xAAD, 0x00 }, + { "TCB3_CTRLA", 0xAB0, 0x00 }, + { "TCB3_CTRLB", 0xAB1, 0x00 }, + { "TCB3_EVCTRL", 0xAB4, 0x00 }, + { "TCB3_INTCTRL", 0xAB5, 0x00 }, + { "TCB3_INTFLAGS", 0xAB6, 0x00 }, + { "TCB3_STATUS", 0xAB7, 0x00 }, + { "TCB3_DBGCTRL", 0xAB8, 0x00 }, + { "TCB3_TEMP" , 0xAB9, 0x00 }, + { "TCB3_CNTL" , 0xABA, 0x00 }, + { "TCB3_CNTH" , 0xABB, 0x00 }, + { "TCB3_CCMPL", 0xABC, 0x00 }, + { "TCB3_CCMPH", 0xABD, 0x00 }, + { "SYSCFG_REVID", 0xF01, 0x00 }, + { "SYSCFG_EXTBRK", 0xF02, 0x00 }, + { "SYSCFG_OCDM", 0xF18, 0x00 }, + { "SYSCFG_OCDMS", 0xF19, 0x00 }, + { "NVMCTRL_CTRLA", 0x1000, 0x00 }, + { "NVMCTRL_CTRLB", 0x1001, 0x00 }, + { "NVMCTRL_STATUS", 0x1002, 0x00 }, + { "NVMCTRL_INTCTRL", 0x1003, 0x00 }, + { "NVMCTRL_INTFLAGS", 0x1004, 0x00 }, + { "NVMCTRL_DATAL", 0x1006, 0x00 }, + { "NVMCTRL_DATAH", 0x1007, 0x00 }, + { "NVMCTRL_ADDRL", 0x1008, 0x00 }, + { "NVMCTRL_ADDRH", 0x1009, 0x00 }, + { "SIGROW_DEVICEID0", 0x1100, 0x00 }, + { "SIGROW_DEVICEID1", 0x1101, 0x00 }, + { "SIGROW_DEVICEID2", 0x1102, 0x00 }, + { "SIGROW_SERNUM0", 0x1103, 0x00 }, + { "SIGROW_SERNUM1", 0x1104, 0x00 }, + { "SIGROW_SERNUM2", 0x1105, 0x00 }, + { "SIGROW_SERNUM3", 0x1106, 0x00 }, + { "SIGROW_SERNUM4", 0x1107, 0x00 }, + { "SIGROW_SERNUM5", 0x1108, 0x00 }, + { "SIGROW_SERNUM6", 0x1109, 0x00 }, + { "SIGROW_SERNUM7", 0x110A, 0x00 }, + { "SIGROW_SERNUM8", 0x110B, 0x00 }, + { "SIGROW_SERNUM9", 0x110C, 0x00 }, + { "SIGROW_OSCCAL32K", 0x1114, 0x00 }, + { "SIGROW_OSCCAL16M0", 0x1118, 0x00 }, + { "SIGROW_OSCCAL16M1", 0x1119, 0x00 }, + { "SIGROW_OSCCAL20M0", 0x111A, 0x00 }, + { "SIGROW_OSCCAL20M1", 0x111B, 0x00 }, + { "SIGROW_TEMPSENSE0", 0x1120, 0x00 }, + { "SIGROW_TEMPSENSE1", 0x1121, 0x00 }, + { "SIGROW_OSC16ERR3V", 0x1122, 0x00 }, + { "SIGROW_OSC16ERR5V", 0x1123, 0x00 }, + { "SIGROW_OSC20ERR3V", 0x1124, 0x00 }, + { "SIGROW_OSC20ERR5V", 0x1125, 0x00 }, + { "SIGROW_CHECKSUM1", 0x112F, 0x00 }, + { "FUSE_WDTCFG", 0x1280, 0x00 }, + { "FUSE_BODCFG", 0x1281, 0x00 }, + { "FUSE_OSCCFG", 0x1282, 0x00 }, + { "FUSE_SYSCFG0", 0x1285, 0x00 }, + { "FUSE_SYSCFG1", 0x1286, 0x00 }, + { "FUSE_APPEND", 0x1287, 0x00 }, + { "FUSE_BOOTEND", 0x1288, 0x00 }, + { "LOCKBIT_LOCKBIT", 0x128A, 0x00 }, + { "USERROW_USERROW0", 0x1300, 0x00 }, + { "USERROW_USERROW1", 0x1301, 0x00 }, + { "USERROW_USERROW2", 0x1302, 0x00 }, + { "USERROW_USERROW3", 0x1303, 0x00 }, + { "USERROW_USERROW4", 0x1304, 0x00 }, + { "USERROW_USERROW5", 0x1305, 0x00 }, + { "USERROW_USERROW6", 0x1306, 0x00 }, + { "USERROW_USERROW7", 0x1307, 0x00 }, + { "USERROW_USERROW8", 0x1308, 0x00 }, + { "USERROW_USERROW9", 0x1309, 0x00 }, + { "USERROW_USERROW10", 0x130A, 0x00 }, + { "USERROW_USERROW11", 0x130B, 0x00 }, + { "USERROW_USERROW12", 0x130C, 0x00 }, + { "USERROW_USERROW13", 0x130D, 0x00 }, + { "USERROW_USERROW14", 0x130E, 0x00 }, + { "USERROW_USERROW15", 0x130F, 0x00 }, + { "USERROW_USERROW16", 0x1310, 0x00 }, + { "USERROW_USERROW17", 0x1311, 0x00 }, + { "USERROW_USERROW18", 0x1312, 0x00 }, + { "USERROW_USERROW19", 0x1313, 0x00 }, + { "USERROW_USERROW20", 0x1314, 0x00 }, + { "USERROW_USERROW21", 0x1315, 0x00 }, + { "USERROW_USERROW22", 0x1316, 0x00 }, + { "USERROW_USERROW23", 0x1317, 0x00 }, + { "USERROW_USERROW24", 0x1318, 0x00 }, + { "USERROW_USERROW25", 0x1319, 0x00 }, + { "USERROW_USERROW26", 0x131A, 0x00 }, + { "USERROW_USERROW27", 0x131B, 0x00 }, + { "USERROW_USERROW28", 0x131C, 0x00 }, + { "USERROW_USERROW29", 0x131D, 0x00 }, + { "USERROW_USERROW30", 0x131E, 0x00 }, + { "USERROW_USERROW31", 0x131F, 0x00 }, + { "USERROW_USERROW32", 0x1320, 0x00 }, + { "USERROW_USERROW33", 0x1321, 0x00 }, + { "USERROW_USERROW34", 0x1322, 0x00 }, + { "USERROW_USERROW35", 0x1323, 0x00 }, + { "USERROW_USERROW36", 0x1324, 0x00 }, + { "USERROW_USERROW37", 0x1325, 0x00 }, + { "USERROW_USERROW38", 0x1326, 0x00 }, + { "USERROW_USERROW39", 0x1327, 0x00 }, + { "USERROW_USERROW40", 0x1328, 0x00 }, + { "USERROW_USERROW41", 0x1329, 0x00 }, + { "USERROW_USERROW42", 0x132A, 0x00 }, + { "USERROW_USERROW43", 0x132B, 0x00 }, + { "USERROW_USERROW44", 0x132C, 0x00 }, + { "USERROW_USERROW45", 0x132D, 0x00 }, + { "USERROW_USERROW46", 0x132E, 0x00 }, + { "USERROW_USERROW47", 0x132F, 0x00 }, + { "USERROW_USERROW48", 0x1330, 0x00 }, + { "USERROW_USERROW49", 0x1331, 0x00 }, + { "USERROW_USERROW50", 0x1332, 0x00 }, + { "USERROW_USERROW51", 0x1333, 0x00 }, + { "USERROW_USERROW52", 0x1334, 0x00 }, + { "USERROW_USERROW53", 0x1335, 0x00 }, + { "USERROW_USERROW54", 0x1336, 0x00 }, + { "USERROW_USERROW55", 0x1337, 0x00 }, + { "USERROW_USERROW56", 0x1338, 0x00 }, + { "USERROW_USERROW57", 0x1339, 0x00 }, + { "USERROW_USERROW58", 0x133A, 0x00 }, + { "USERROW_USERROW59", 0x133B, 0x00 }, + { "USERROW_USERROW60", 0x133C, 0x00 }, + { "USERROW_USERROW61", 0x133D, 0x00 }, + { "USERROW_USERROW62", 0x133E, 0x00 }, + { "USERROW_USERROW63", 0x133F, 0x00 }, + { 0, 0, 0} +}; + + gdb_io_reg_def_type atmega644p_io_registers[] = { { "PINA", 0x20, 0x00 }, diff --git a/src/ioreg.h b/src/ioreg.h index 8f5066d..f37118d 100644 --- a/src/ioreg.h +++ b/src/ioreg.h @@ -98,6 +98,9 @@ extern gdb_io_reg_def_type atmega32hvb_io_registers[]; extern gdb_io_reg_def_type atmega32u4_io_registers[]; extern gdb_io_reg_def_type atmega406_io_registers[]; extern gdb_io_reg_def_type atmega48p_io_registers[]; +extern gdb_io_reg_def_type atmega3208_io_registers[]; +extern gdb_io_reg_def_type atmega4808_io_registers[]; +extern gdb_io_reg_def_type atmega4809_io_registers[]; extern gdb_io_reg_def_type atmega644p_io_registers[]; extern gdb_io_reg_def_type atmega88p_io_registers[]; extern gdb_io_reg_def_type attiny167_io_registers[]; diff --git a/src/jtag.h b/src/jtag.h index 3f4f358..c27be33 100644 --- a/src/jtag.h +++ b/src/jtag.h @@ -190,6 +190,15 @@ typedef struct { unsigned char osccal_address; } jtag3_device_desc_type; +/* UPDI device descriptor */ +struct updi_device_desc { + unsigned char prog_base[2]; + unsigned char flash_page_size; + unsigned char eeprom_page_size; + unsigned char nvm_base_addr[2]; + unsigned char ocd_base_addr[2]; +}; + #define fill_b4(u) \ { ((u) & 0xffUL), (((u) & 0xff00UL) >> 8), \ (((u) & 0xff0000UL) >> 16), (((u) & 0xff000000UL) >> 24) } @@ -233,6 +242,8 @@ typedef struct { xmega_device_desc_type dev_desc3; // Device descriptor to download for // Xmega devices in new (7+) firmware // JTAGICE mkII and AVR Dragon + updi_device_desc dev_desc4; // Device descriptor to download to + // UPDI device } jtag_device_def_type; extern jtag_device_def_type deviceDefinitions[]; @@ -752,7 +763,7 @@ typedef struct { #define JTAG_EOM 0x20, 0x20 enum debugproto { - PROTO_JTAG, PROTO_DW, PROTO_PDI, + PROTO_JTAG, PROTO_DW, PROTO_PDI, PROTO_UPDI }; class jtag diff --git a/src/jtag2io.cc b/src/jtag2io.cc index 86ae19e..507c759 100644 --- a/src/jtag2io.cc +++ b/src/jtag2io.cc @@ -605,6 +605,8 @@ void jtag2::startJtagLink(void) val = EMULATOR_MODE_PDI; protoName = "PDI"; break; + default: + break; } try { diff --git a/src/jtag3.h b/src/jtag3.h index 51914f0..267cd4c 100644 --- a/src/jtag3.h +++ b/src/jtag3.h @@ -139,6 +139,7 @@ enum jtag3consts PARM3_ARCH_TINY = 1, /* also small megaAVR with ISP/DW only */ PARM3_ARCH_MEGA = 2, PARM3_ARCH_XMEGA = 3, + PARM3_ARCH_UPDI = 5, PARM3_SESS_PURPOSE = 0x01, /* section 0, AVR scope, 1 byte */ PARM3_SESS_PROGRAMMING = 1, @@ -149,6 +150,7 @@ enum jtag3consts PARM3_CONN_JTAG = 4, PARM3_CONN_DW = 5, PARM3_CONN_PDI = 6, + PARM3_CONN_UPDI = 8, PARM3_JTAGCHAIN = 0x01, /* JTAG chain info, AVR scope (units * before/after, bits before/after), diff --git a/src/jtag3io.cc b/src/jtag3io.cc index f7544dc..024deb1 100644 --- a/src/jtag3io.cc +++ b/src/jtag3io.cc @@ -363,7 +363,12 @@ void jtag3::setDeviceDescriptor(jtag_device_def_type *dev) uchar *param, paramsize; jtag3_device_desc_type d3; - if (is_xmega) + if (proto == PROTO_UPDI) + { + param = (uchar *)&dev->dev_desc4; + paramsize = sizeof dev->dev_desc4; + } + else if (is_xmega) { param = (uchar *)&dev->dev_desc3 + 4; paramsize = sizeof dev->dev_desc3 - 4; @@ -456,6 +461,8 @@ void jtag3::startJtagLink(void) paramdata[0] = PARM3_ARCH_XMEGA; else if (proto == PROTO_DW) paramdata[0] = PARM3_ARCH_TINY; + else if (proto == PROTO_UPDI) + paramdata[0] = PARM3_ARCH_UPDI; else paramdata[0] = PARM3_ARCH_MEGA; setJtagParameter(SCOPE_AVR, 0, PARM3_ARCH, paramdata, 1); @@ -477,12 +484,37 @@ void jtag3::startJtagLink(void) case PROTO_PDI: paramdata[0] = PARM3_CONN_PDI; break; + + case PROTO_UPDI: + paramdata[0] = PARM3_CONN_UPDI; + break; } setJtagParameter(SCOPE_AVR, 1, PARM3_CONNECTION, paramdata, 1); if (proto == PROTO_JTAG) configDaisyChain(); + if (proto == PROTO_UPDI) + { + /* + * Unfortunately, for Xmega devices on UPDI, it's necessary + * to send the device descriptor before sign-on. However, + * in order to do this, the JTAGICE3 needs a valid device + * descriptor already. + * + * Hopefully, the values below will remain constant for all + * Xmega devices ... + */ + jtag_device_def_type desc = { "dummy", 0 }; + + u16_to_b2(desc.dev_desc4.prog_base, 0x4000); + desc.dev_desc4.flash_page_size = 128; + desc.dev_desc4.eeprom_page_size = 64; + u16_to_b2(desc.dev_desc4.nvm_base_addr, 0x1000); + u16_to_b2(desc.dev_desc4.ocd_base_addr, 0x0F80); + setDeviceDescriptor(&desc); + } + cmd[0] = SCOPE_AVR; cmd[1] = CMD3_SIGN_ON; cmd[2] = 0; @@ -505,6 +537,15 @@ void jtag3::startJtagLink(void) device_id = (did & 0x0FFFF000) >> 12; } + else if (proto == PROTO_UPDI) + { + debugOut("AVR sign-on responded with %c%c%c%c\n", + (did & 0x000000FF) >> 0, + (did & 0x0000FF00) >> 8, + (did & 0x00FF0000) >> 16, + (did & 0xFF000000) >> 24); + device_id = 0; + } else // debugWIRE { debugOut("AVR sign-on responded with device ID = 0x%0X\n", did); diff --git a/src/jtag3rw.cc b/src/jtag3rw.cc index ada7430..a3741ee 100644 --- a/src/jtag3rw.cc +++ b/src/jtag3rw.cc @@ -76,7 +76,7 @@ uchar jtag3::memorySpace(unsigned long &addr) case DATA_SPACE_ADDR_OFFSET: return MTYPE_SRAM; default: - if (is_xmega) + if (is_xmega || proto == PROTO_UPDI) return MTYPE_XMEGA_APP_FLASH; else if (proto == PROTO_DW || programmingEnabled) return MTYPE_FLASH_PAGE; @@ -103,6 +103,7 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes) whichSpace < MTYPE_XMEGA_REG; unsigned int pageSize = 0; unsigned int offset = 0; + unsigned int alignSize = 0; bool wasProgmode = programmingEnabled; if (needProgmode && !programmingEnabled) enableProgramming(); @@ -112,6 +113,12 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes) switch (whichSpace) { + case MTYPE_SIGN_JTAG: + // The signature needs to be read from its exact address, + // not just the signature space with address 0. + if (proto == PROTO_UPDI) + addr = 0x1100; + break; // Pad to even byte count for flash memory. // Even MTYPE_SPM appears to cause a RSP_FAILED // otherwise. @@ -132,6 +139,12 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes) cachePtr = eepromCache; cacheBaseAddr = &eepromCachePageAddr; break; + + case MTYPE_XMEGA_APP_FLASH: + // Flash for UPDI devices can only be accessed in word (16bit) chunks + if (proto == PROTO_UPDI) + alignSize = 2; + break; } uchar cmd[12]; @@ -197,8 +210,37 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes) pageAddr += pageSize; } } else { - u32_to_b4(cmd + 8, numBytes); - u32_to_b4(cmd + 4, addr); + unsigned int addrAdj = addr; + unsigned int numBytesAdj = numBytes; + // Access to some memories may only be allowed in chunks aligned + // to a certain size. If that is the case, properly align what is + // read from the device (thus reading more than asked), then only + // return to GDB the requested data. + if (alignSize != 0) + { + // Get address adjustment by rounding down to alignment size + // e.g. For alignmentSize of 10 + // 39 becomes 30 => adjustment of 9 + addrAdj = (addr / alignSize) * alignSize; + // Get length adjustment by rounding up to number of bytes + // e.g. For alignmentSize of 10 + // 39 becomes 40 => adjustment of 1 + numBytesAdj = ((numBytes + alignSize - 1) / alignSize) * alignSize; + + if (addr + numBytes > addrAdj + numBytesAdj) + { + // If both address and length are not aligned in request, our + // alignment may make us read less than requested range. + // Add alignmentSize to correct for this. + // e.g. For alignmentSize of 10 + // 39 bytes from address 39 => bytes #39-77 requested + // but 40 bytes from address 30 => bytes #30-69 read. + // Adding 10 => bytes #30-79 read which covers expected range + numBytesAdj += alignSize; + } + } + u32_to_b4(cmd + 8, numBytesAdj); + u32_to_b4(cmd + 4, addrAdj); int cnt = 0; again: @@ -225,6 +267,8 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes) e.what()); throw; } + responsesize -= (addr - addrAdj) + (numBytesAdj - numBytes); + offset = (addr - addrAdj); if (offset > 0) memmove(response, response + 3 + offset, responsesize - 1 - offset); else diff --git a/src/jtaggeneric.cc b/src/jtaggeneric.cc index 5da08e2..dd3764d 100644 --- a/src/jtaggeneric.cc +++ b/src/jtaggeneric.cc @@ -468,7 +468,7 @@ static unsigned int countFuses(unsigned int fusemap) { unsigned int nfuses = 0; - for (unsigned int i = 7, mask = 0x80; + for (unsigned int i = 15, mask = 0x8000; mask != 0; i--, mask >>= 1) { @@ -560,8 +560,8 @@ void jtag::jtagDisplayFuses(uchar *fuseBits) } else { - // Xmega: fuse0 ... fuse7 (or just some of them) - for (unsigned int i = 7, mask = 0x80; + // Xmega: fuse0 ... fuse15 (or just some of them) + for (unsigned int i = 15, mask = 0x8000; mask != 0; i--, mask >>= 1) { diff --git a/src/main.cc b/src/main.cc index 652c19c..71110ff 100644 --- a/src/main.cc +++ b/src/main.cc @@ -226,6 +226,8 @@ static void usage(const char *progname) " -r, --read-fuses Read fuses bytes.\n"); fprintf(stderr, " -R, --reset-srst External reset through nSRST signal.\n"); + fprintf(stderr, + " -u, --updi AVR part is an ATxmega device, using UPDI.\n"); fprintf(stderr, " -V, --version Print version information.\n"); #if ENABLE_TARGET_PROGRAMMING @@ -332,6 +334,7 @@ static struct option long_opts[] = { { "program", 0, 0, 'p' }, { "reset-srst", 0, 0, 'R' }, { "read-fuses", 0, 0, 'r' }, + { "updi", 0, 0, 'u' }, { "version", 0, 0, 'V' }, { "verify", 0, 0, 'v' }, { "debugwire", 0, 0, 'w' }, @@ -389,7 +392,7 @@ int main(int argc, char **argv) while (1) { - int c = getopt_long (argc, argv, "1234B:Cc:DdeE:f:ghIj:kL:lP:pRrVvwW:xX", + int c = getopt_long (argc, argv, "1234B:Cc:DdeE:f:ghIj:kL:lP:pRruVvwW:xX", long_opts, &option_index); if (c == -1) break; /* no more options */ @@ -475,6 +478,9 @@ int main(int argc, char **argv) case 'r': readFuses = true; break; + case 'u': + proto = PROTO_UPDI; + break; case 'V': exit(0); case 'v': diff --git a/src/remote.cc b/src/remote.cc index caa6b87..704f00c 100644 --- a/src/remote.cc +++ b/src/remote.cc @@ -1024,7 +1024,7 @@ void talkToGdb(void) } else if (strncmp(ptr, "Supported:", 10) == 0) { - strcpy(remcomOutBuffer, "qXfer:memory-map:read+"); + strcpy(remcomOutBuffer, "PacketSize=40;qXfer:memory-map:read+"); } else if (strncmp(ptr, "Xfer:memory-map:read::", 22) == 0) {